From patchwork Thu Jun 27 16:25:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 13714782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 380D9C2BD09 for ; Thu, 27 Jun 2024 16:26:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=zTVIbbXi0KpwSMhpFDWnmvkSkJwEPOm0jo+slsNFmgM=; b=F2Fybz3hJcDbHt1G4B+javqnl4 E5gtHh0pBnKVCQARz42HuZ81uZGNpbV4VtZvpud4ANMmbUydPPJAOyc6K4b1m+LvEV65OKCJuve3y meuS0CwHmBWM/9fmoie5yw9YNXyYNdr52eK0QROjNmYSy8XHJW6btyhz6alB9+V8fj/0MrBbcrbL2 lB5/Yv0ObwW0lSuIv/KjaNkMQnMq0REUOIZewo4+GSZypiPKUyEC4phJLArC2zD1hy6JUmeVZnzJ2 ytUxvfrsJGMwXJs1uIGE7X6ZMjn/x609PmFR2AP8ds/T80Z+aHTVMcVLsiIqTFTrohjaGG+ERuAIH /cUYQAAQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMrwk-0000000B1ru-3DKy; Thu, 27 Jun 2024 16:26:06 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMrwV-0000000B1lf-3VLu for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2024 16:25:54 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45RGPfMr049645; Thu, 27 Jun 2024 11:25:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1719505541; bh=zTVIbbXi0KpwSMhpFDWnmvkSkJwEPOm0jo+slsNFmgM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TX3CfPQiGNeXvCm38eyMwno21z2tm/z7YM+y9UIW+KLnzWjFhS135Q7yANbTXNigQ +DBcXoiXRjDu6WWeikIgLcbz6j3m5mYH3pq8PimI2seomBv1PJo2pxd3U0Sn0fBsC/ /kK2bm/crHFa7YRtvg7R5Db4ssUeQBo0E4dNuqTE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45RGPfMI023116 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Jun 2024 11:25:41 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 27 Jun 2024 11:25:41 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 27 Jun 2024 11:25:41 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45RGPfRF130220; Thu, 27 Jun 2024 11:25:41 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Vignesh Raghavendra CC: , , , Tero Kristo , Vaishnav Achath , Jared McArthur , Bryan Brattlof , Dhruva Gole , Nishanth Menon Subject: [PATCH V2 1/3] arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode Date: Thu, 27 Jun 2024 11:25:37 -0500 Message-ID: <20240627162539.691223-2-nm@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240627162539.691223-1-nm@ti.com> References: <20240627162539.691223-1-nm@ti.com> MIME-Version: 1.0 Organization: Texas Instruments, Inc. X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_092552_036406_32D654A5 X-CRM114-Status: UNSURE ( 9.53 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a GPIO mux mode macro for easier readability. All K3 devices use mux mode 7 to switch to GPIO mux and this allows the gpio-ranges to be defined for pinctrl-single clearly. Signed-off-by: Nishanth Menon --- Changes since V1: - Mux definition PIN_GPIO_RANGE_IOPAD instead of PIN_GPIO_MUX_MODE - Added documentation as well to clarify the usage. V1: https://lore.kernel.org/linux-arm-kernel/20240618173123.2592074-2-nm@ti.com/ arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index 4cd2df467d0b..22b8d73cfd32 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -38,6 +38,9 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) +/* Default mux configuration for gpio-ranges to use with pinctrl */ +#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) + #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) From patchwork Thu Jun 27 16:25:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 13714780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5331CC3064D for ; Thu, 27 Jun 2024 16:26:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QWLAeR0SbvPwAQvjXd9TFa3s9O6NKETMaJ1nSHrnJPo=; b=FtNSoe3fmKpj4K/Wfpym1MLPzJ rbS7WH8SJ+tiFuX57EmmKWa1YvZnWegliB32Rn/BJFpELveHRsGxm/rE4T39NBFPlNmlqitEvQKB5 Rj1gx1sZS38LLR2//UlnluMV75DeTiCrYfHRSrDikL/QFgt55IG2nNSSTVM3BR1htfUgRLRQJkXon vvjSf1jEO1qjvETkvh209afQseE8z/R6JotD8RwxlyFunChaCkPwnPATJffW/ZcLdYLvMd54BSxOD ftwbmndEXkhrgGWofKn/XQ3ocF67LvQ/KyXWy/ehzQEQ1vIQRs2WLE/S1CyAazQehHJUSXF7jGQrc VzPl0lUg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMrwY-0000000B1n2-2iG8; Thu, 27 Jun 2024 16:25:54 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMrwQ-0000000B1kH-03UX for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2024 16:25:48 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45RGPfn5033152; Thu, 27 Jun 2024 11:25:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1719505541; bh=QWLAeR0SbvPwAQvjXd9TFa3s9O6NKETMaJ1nSHrnJPo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aQ4pniGEnPDNfiBTn4vZkkag3fhbzRXtvAGqd9G5uhwcKqneE5DkhMlxpDlZlgX9C FtgJSh0W3fOQF4s6fRuFW96SBGA3Jqj8AbIdpbcYSE5cHp48h60Ie2INVi0ZTzylgV 38IZfhAdcdgxUCcL0w9T9iRx4xprJTK87p7q/UVk= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45RGPfHQ092933 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Jun 2024 11:25:41 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 27 Jun 2024 11:25:41 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 27 Jun 2024 11:25:41 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45RGPfHf095204; Thu, 27 Jun 2024 11:25:41 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Vignesh Raghavendra CC: , , , Tero Kristo , Vaishnav Achath , Jared McArthur , Bryan Brattlof , Dhruva Gole , Nishanth Menon Subject: [PATCH V2 2/3] arm64: dts: ti: k3-am62p: Add gpio-ranges properties Date: Thu, 27 Jun 2024 11:25:38 -0500 Message-ID: <20240627162539.691223-3-nm@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240627162539.691223-1-nm@ti.com> References: <20240627162539.691223-1-nm@ti.com> MIME-Version: 1.0 Organization: Texas Instruments, Inc. X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_092546_230352_656FB8A9 X-CRM114-Status: GOOD ( 12.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On the AM62P platform we have no single 1:1 relation regarding index of GPIO and pin controller. The GPIOs and pin controller registers have mapping and holes in the map. These have been extracted from the AM62P data sheet. MCU pinctrl definition is shared as it is common between AM62P and J722S, but that is not the case for main domain. Ref: AM62P Data sheet https://www.ti.com/lit/gpn/am62p Signed-off-by: Nishanth Menon --- Changes since V1: - Use PIN_GPIO_RANGE_IOPAD instead of PIN_GPIO_MUX_MODE - Refactored on top of next-20240626 (new common files) - Since the patch had to be refactored as well as new define used, I have skipped picking up Dhruva's Reviewed-by. V1: https://lore.kernel.org/linux-arm-kernel/20240618173123.2592074-3-nm@ti.com/ .../boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index 1d4e5fc8b4e0..e65db6ce02bf 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -12,7 +12,15 @@ mcu_pmx0: pinctrl@4084000 { #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,gpio-range = + <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>, + <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>, + <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>; bootph-all; + + mcu_pmx_range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; }; mcu_esm: esm@4100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index f8a7f0cbd327..57383bd2eaeb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -42,10 +42,27 @@ &inta_main_dmss { ti,interrupt-ranges = <5 69 35>; }; +&main_pmx0 { + pinctrl-single,gpio-range = + <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 33 92 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; + + main_pmx0_range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + &main_gpio0 { + gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, + <&main_pmx0 70 72 22>; ti,ngpio = <92>; }; &main_gpio1 { + gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>, + <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>; ti,ngpio = <52>; }; From patchwork Thu Jun 27 16:25:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 13714781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BEC3C2BD09 for ; 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Thu, 27 Jun 2024 11:25:41 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 27 Jun 2024 11:25:41 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45RGPfB9095207; Thu, 27 Jun 2024 11:25:41 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Vignesh Raghavendra CC: , , , Tero Kristo , Vaishnav Achath , Jared McArthur , Bryan Brattlof , Dhruva Gole , Nishanth Menon Subject: [PATCH V2 3/3] arm64: dts: ti: k3-j722s: Add gpio-ranges properties Date: Thu, 27 Jun 2024 11:25:39 -0500 Message-ID: <20240627162539.691223-4-nm@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240627162539.691223-1-nm@ti.com> References: <20240627162539.691223-1-nm@ti.com> MIME-Version: 1.0 Organization: Texas Instruments, Inc. X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_092551_699370_5068CAEB X-CRM114-Status: GOOD ( 12.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jared McArthur The AM67A/J722S/TDA4AEN platform is a derivative of AM62P platform and we have no single 1:1 relation regarding index of GPIO and pin controller. The GPIOs and pin controller registers have mapping and holes in the map. These have been extracted from the J722S data sheet. The MCU mapping is carried forward as is with J722S, however the main GPIO block has differences that needs to be accounted for. Mux mode input is selected as it is bi-directional. In case a specific pull type or a specific pin level drive setting is desired, the board device tree files will have to explicitly mux those pins for the GPIO with the desired setting. Ref: J722S Data sheet https://www.ti.com/lit/gpn/tda4aen-q1 Signed-off-by: Jared McArthur Signed-off-by: Nishanth Menon --- Changes since V1: - Use PIN_GPIO_RANGE_IOPAD instead of PIN_GPIO_MUX_MODE - Refactored on top of next-20240626 (refactored files) V1: https://lore.kernel.org/linux-arm-kernel/20240618173123.2592074-4-nm@ti.com/ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 228c6c89245c..28aac43aae45 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -181,10 +181,28 @@ &inta_main_dmss { ti,interrupt-ranges = <7 71 21>; }; +&main_pmx0 { + pinctrl-single,gpio-range = + <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 33 55 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; + + main_pmx0_range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + &main_gpio0 { + gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, + <&main_pmx0 70 72 17>; ti,ngpio = <87>; }; &main_gpio1 { + gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>, + <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>; ti,ngpio = <73>; };