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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Thu, 27 Jun 2024 22:46:51 +0000 Received: from rric.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 27 Jun 2024 17:46:47 -0500 From: Robert Richter To: Dan Williams , Davidlohr Bueso , Jonathan Cameron , "Dave Jiang" , Alison Schofield , Vishal Verma , Ira Weiny CC: , , "Robert Richter" Subject: [PATCH 1/5] cxl/hdm: Moving HDM specific code to core/hdm.c. Date: Fri, 28 Jun 2024 00:46:10 +0200 Message-ID: <20240627224615.854162-2-rrichter@amd.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240627224615.854162-1-rrichter@amd.com> References: <20240627224615.854162-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|PH7PR12MB6761:EE_ X-MS-Office365-Filtering-Correlation-Id: 4032ff15-8960-4feb-dc6f-08dc96fb08fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: Tc6XYdmDOhdoz7xnEwYgigFPdp7tfZBbZ1yZf/Yc+Z93BDCBg4OnatMs7t1qs+LLP1dhCD/AtlPxh/UdW5/rWU3DZ+Y889IsbglrDctoi4Wt6DfCDGs6PtBR8zTDpTFZdqchRhJW7556TMzOmIbKM3qPNpKjtAf7y8BcQiQ0mxInjihkJJR+UjgxImzk+Sh3Chcdzh9EZolvq7ZbQbmJs9wdKeH21akfBpLqNwayM46V8zlC2Uqn4FPi+XA3yx3sqsqb8cGJj4QG4bSv0XJDQQ7HIvoSKHZIYiId1hc8VKpgWeWE0QL9JXs9AdXrQARJ2C0sR/Kf6R0QNDfSQGq583emnRfvN+AMrbJZz+KcubnPFRMDs+30obkl7tlNpts30YK+x0JvQMnXh4OuB1yoZK8jyMo9cNKP0o66cZJzkELwLY453yee6lyTxN/EKbvTLiO+RCMCs/PZHhOt3vltt2mavyZ6SVjmFtO0AUe9jr8b+zzKUyajt+3v7X689RmPwpdX93EwvdUZij7JShgak6D1uddGw2QcQ8NkRs9bNHTc/Aj56xS1E3BDmxe+/txyACVsWkCg1eStwTN/XBPda+HnVeMyj7hM3eUQE/aCdKGQMP6Ce+TPgUGcm5mVCzG+VWfRSTiSqsWqJCvoneT5pJuHfjk9blOBVUyISuWynZeWIUNyLNmD7RVztq79CQpGgqeQRoaJiR5FElV7iBjvrTiKO2j417qYttD5TDdMeR9xy/wBM6g3m+l5Wf889rSgb5JazDaHIp3ssICs6/0ljRtqcirDWVMxMraDlixEA2fhdrJhjt9k9f6hTEklNdBbr1Dse4/idxnKS2hNZgASZPRhT5MeggWrnMXDOv3LOgFYemoTwd02tm2ovd6G37APeFIrtJDwixpwi0//wJmMzMJLYQdTTJoXJs2/ukYnCR/sr5MqvaeeG79Ud5whbOiIQnCfG9ofuhQzruoL5iScX92S8YPCB10qI4lpjreiVJGiB17lkt3JDELHX4JyHsDK+hYDKQhrlwaleiw7tzefpQmbzWKqAfPEB4RlqpAHBA4q68IX3O6NuywiCj7BeeWqAlZ4Pza1xPL8QAscJ55bLFLTezmAIfuvlXgxDcFTCp1pw0MPEl5PIAdOM5JcLCdM45f3HJgkQO/QV8XYm64ZYbXHbFKR10UFtPy8af1YcK6ydOGt8K3596qzLLbmrR6pnsrjYgdObPoGPg1ypgFtw8FS7UaA5AGfg1yXYeqPmT5tIMWLkbV8wY50Vlony3Bozfz1Oy15fAZFVzLM1yDVYv40BPbC8o/rqPOKeMCwlnMyzCSlutvHjtU8OMT1ytle1a51hAVf2k97c1cA+cqTM1NlMJ/FxAVWtYnKjtt/jJU52KKMDPq9jCVvV0nrWc9CoahRJyb5T/Esd5pfzoHEGjR312iwqzIjq3CQliq91BZ47POTYuzXP33qbThrmzYJ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 22:46:51.0799 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4032ff15-8960-4feb-dc6f-08dc96fb08fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6761 Code to handle HDM specifics is implemented in core/pci.c and core/hdm.c. In both files helper functions will be needed for address translation. To simplify the introduction of static helper functions, move all HDM code to core/hdm.c. The function devm_cxl_enable_mem() is no longer static and is shared now within the core module. No functional changes otherwise. Signed-off-by: Robert Richter --- drivers/cxl/core/core.h | 2 + drivers/cxl/core/hdm.c | 117 +++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/pci.c | 119 +--------------------------------------- drivers/cxl/cxlmem.h | 3 + drivers/cxl/cxlpci.h | 3 - 5 files changed, 123 insertions(+), 121 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 625394486459..d8c3c27ce100 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -70,6 +70,8 @@ int cxl_query_cmd(struct cxl_memdev *cxlmd, int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s); void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, resource_size_t length); +struct cxl_dev_state; +int devm_cxl_enable_mem(struct device *host, struct cxl_dev_state *cxlds); struct dentry *cxl_debugfs_create_dir(const char *dir); int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 784843fa2a22..605da9a55d89 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -1027,3 +1027,120 @@ int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, return 0; } EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_decoders, CXL); + +/* require dvsec ranges to be covered by a locked platform window */ +static int dvsec_range_allowed(struct device *dev, void *arg) +{ + struct range *dev_range = arg; + struct cxl_decoder *cxld; + + if (!is_root_decoder(dev)) + return 0; + + cxld = to_cxl_decoder(dev); + + if (!(cxld->flags & CXL_DECODER_F_RAM)) + return 0; + + return range_contains(&cxld->hpa_range, dev_range); +} + +static void disable_hdm(void *_cxlhdm) +{ + u32 global_ctrl; + struct cxl_hdm *cxlhdm = _cxlhdm; + void __iomem *hdm = cxlhdm->regs.hdm_decoder; + + global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); + writel(global_ctrl & ~CXL_HDM_DECODER_ENABLE, + hdm + CXL_HDM_DECODER_CTRL_OFFSET); +} + +static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm) +{ + void __iomem *hdm = cxlhdm->regs.hdm_decoder; + u32 global_ctrl; + + global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); + writel(global_ctrl | CXL_HDM_DECODER_ENABLE, + hdm + CXL_HDM_DECODER_CTRL_OFFSET); + + return devm_add_action_or_reset(host, disable_hdm, cxlhdm); +} + +/** + * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint + * @cxlds: Device state + * @cxlhdm: Mapped HDM decoder Capability + * @info: Cached DVSEC range registers info + * + * Try to enable the endpoint's HDM Decoder Capability + */ +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, + struct cxl_endpoint_dvsec_info *info) +{ + void __iomem *hdm = cxlhdm->regs.hdm_decoder; + struct cxl_port *port = cxlhdm->port; + struct device *dev = cxlds->dev; + struct cxl_port *root; + int i, rc, allowed; + u32 global_ctrl = 0; + + if (hdm) + global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); + + /* + * If the HDM Decoder Capability is already enabled then assume + * that some other agent like platform firmware set it up. + */ + if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) + return devm_cxl_enable_mem(&port->dev, cxlds); + else if (!hdm) + return -ENODEV; + + root = to_cxl_port(port->dev.parent); + while (!is_cxl_root(root) && is_cxl_port(root->dev.parent)) + root = to_cxl_port(root->dev.parent); + if (!is_cxl_root(root)) { + dev_err(dev, "Failed to acquire root port for HDM enable\n"); + return -ENODEV; + } + + for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) { + struct device *cxld_dev; + + cxld_dev = device_find_child(&root->dev, &info->dvsec_range[i], + dvsec_range_allowed); + if (!cxld_dev) { + dev_dbg(dev, "DVSEC Range%d denied by platform\n", i); + continue; + } + dev_dbg(dev, "DVSEC Range%d allowed by platform\n", i); + put_device(cxld_dev); + allowed++; + } + + if (!allowed && info->mem_enabled) { + dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n"); + return -ENXIO; + } + + /* + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base + * [High,Low] when HDM operation is enabled the range register values + * are ignored by the device, but the spec also recommends matching the + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges + * are expected even though Linux does not require or maintain that + * match. If at least one DVSEC range is enabled and allowed, skip HDM + * Decoder Capability Enable. + */ + if (info->mem_enabled) + return 0; + + rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); + if (rc) + return rc; + + return devm_cxl_enable_mem(&port->dev, cxlds); +} +EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 8567dd11eaac..4f67e3ae7a05 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -270,7 +270,7 @@ static void clear_mem_enable(void *cxlds) cxl_set_mem_enable(cxlds, 0); } -static int devm_cxl_enable_mem(struct device *host, struct cxl_dev_state *cxlds) +int devm_cxl_enable_mem(struct device *host, struct cxl_dev_state *cxlds) { int rc; @@ -282,46 +282,6 @@ static int devm_cxl_enable_mem(struct device *host, struct cxl_dev_state *cxlds) return devm_add_action_or_reset(host, clear_mem_enable, cxlds); } -/* require dvsec ranges to be covered by a locked platform window */ -static int dvsec_range_allowed(struct device *dev, void *arg) -{ - struct range *dev_range = arg; - struct cxl_decoder *cxld; - - if (!is_root_decoder(dev)) - return 0; - - cxld = to_cxl_decoder(dev); - - if (!(cxld->flags & CXL_DECODER_F_RAM)) - return 0; - - return range_contains(&cxld->hpa_range, dev_range); -} - -static void disable_hdm(void *_cxlhdm) -{ - u32 global_ctrl; - struct cxl_hdm *cxlhdm = _cxlhdm; - void __iomem *hdm = cxlhdm->regs.hdm_decoder; - - global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); - writel(global_ctrl & ~CXL_HDM_DECODER_ENABLE, - hdm + CXL_HDM_DECODER_CTRL_OFFSET); -} - -static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm) -{ - void __iomem *hdm = cxlhdm->regs.hdm_decoder; - u32 global_ctrl; - - global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); - writel(global_ctrl | CXL_HDM_DECODER_ENABLE, - hdm + CXL_HDM_DECODER_CTRL_OFFSET); - - return devm_add_action_or_reset(host, disable_hdm, cxlhdm); -} - int cxl_dvsec_rr_decode(struct device *dev, int d, struct cxl_endpoint_dvsec_info *info) { @@ -425,83 +385,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, } EXPORT_SYMBOL_NS_GPL(cxl_dvsec_rr_decode, CXL); -/** - * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint - * @cxlds: Device state - * @cxlhdm: Mapped HDM decoder Capability - * @info: Cached DVSEC range registers info - * - * Try to enable the endpoint's HDM Decoder Capability - */ -int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, - struct cxl_endpoint_dvsec_info *info) -{ - void __iomem *hdm = cxlhdm->regs.hdm_decoder; - struct cxl_port *port = cxlhdm->port; - struct device *dev = cxlds->dev; - struct cxl_port *root; - int i, rc, allowed; - u32 global_ctrl = 0; - - if (hdm) - global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); - - /* - * If the HDM Decoder Capability is already enabled then assume - * that some other agent like platform firmware set it up. - */ - if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) - return devm_cxl_enable_mem(&port->dev, cxlds); - else if (!hdm) - return -ENODEV; - - root = to_cxl_port(port->dev.parent); - while (!is_cxl_root(root) && is_cxl_port(root->dev.parent)) - root = to_cxl_port(root->dev.parent); - if (!is_cxl_root(root)) { - dev_err(dev, "Failed to acquire root port for HDM enable\n"); - return -ENODEV; - } - - for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) { - struct device *cxld_dev; - - cxld_dev = device_find_child(&root->dev, &info->dvsec_range[i], - dvsec_range_allowed); - if (!cxld_dev) { - dev_dbg(dev, "DVSEC Range%d denied by platform\n", i); - continue; - } - dev_dbg(dev, "DVSEC Range%d allowed by platform\n", i); - put_device(cxld_dev); - allowed++; - } - - if (!allowed && info->mem_enabled) { - dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n"); - return -ENXIO; - } - - /* - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base - * [High,Low] when HDM operation is enabled the range register values - * are ignored by the device, but the spec also recommends matching the - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges - * are expected even though Linux does not require or maintain that - * match. If at least one DVSEC range is enabled and allowed, skip HDM - * Decoder Capability Enable. - */ - if (info->mem_enabled) - return 0; - - rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); - if (rc) - return rc; - - return devm_cxl_enable_mem(&port->dev, cxlds); -} -EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); - #define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff #define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0 #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00 diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 19aba81cdf13..61d9f4e00921 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -862,4 +862,7 @@ struct cxl_hdm { struct seq_file; struct dentry *cxl_debugfs_create_dir(const char *dir); void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, + struct cxl_endpoint_dvsec_info *info); + #endif /* __CXL_MEM_H__ */ diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4da07727ab9c..fe01793af1cb 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -122,9 +122,6 @@ static inline bool cxl_pci_flit_256(struct pci_dev *pdev) } int devm_cxl_port_enumerate_dports(struct cxl_port *port); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 22:46:54.6472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27ad03b8-2f01-4eb8-9540-08dc96fb0b20 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5715 Default expectation of Linux is that HPA == SPA, which means that hardware addresses in the decoders are the same as the kernel sees them. However, there are platforms where this is not the case and an address translation between decoder's (HPA) and the system's physical addresses (SPA) is needed. The CXL driver stores all internal hardware address ranges as SPA. When accessing the HDM decoder's registers, hardware addresses must be translated back and forth. This is needed for the base addresses in the CXL Range Registers of the PCIe DVSEC for CXL Devices (CXL_DVSEC_RANGE_BASE*) or the CXL HDM Decoder Capability Structure (CXL_HDM_DECODER0_BASE*). To handle address translation the kernel needs to keep track of the system's base HPA the decoder bases on. The base can be different between memory domains, each port may have its own domain. Thus, the HPA base cannot be shared between CXL ports and its decoders, instead the base HPA must be stored per port. Each port has its own struct cxl_hdm to handle the sets of decoders and targets, that struct can also be used for storing the base. Add @base_hpa to struct cxl_hdm. Also Introduce helper functions for the translation and use them to convert the HDM decoder base addresses to or from an SPA. While at this, rename len to size for the common base/size naming used with ranges. Link: https://lore.kernel.org/all/65c6b8c9a42e4_d2d4294f1@dwillia2-xfh.jf.intel.com.notmuch/ Suggested-by: Dan Williams Signed-off-by: Robert Richter --- drivers/cxl/core/hdm.c | 69 ++++++++++++++++++++++++++++++++++-------- drivers/cxl/cxlmem.h | 1 + 2 files changed, 57 insertions(+), 13 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 605da9a55d89..50078013f4e3 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -125,6 +125,17 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) return true; } +static void setup_base_hpa(struct cxl_hdm *cxlhdm) +{ + /* + * Address translation is not needed on platforms with HPA == + * SPA. HDM decoder addresses all base on system addresses, + * there is no offset and the base is zero (cxlhdm->base_hpa + * == 0). Nothing to do here as it is already pre-initialized + * zero. + */ +} + /** * devm_cxl_setup_hdm - map HDM decoder component registers * @port: cxl_port to map @@ -144,6 +155,8 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, cxlhdm->port = port; dev_set_drvdata(dev, cxlhdm); + setup_base_hpa(cxlhdm); + /* Memory devices can configure device HDM using DVSEC range regs. */ if (reg_map->resource == CXL_RESOURCE_NONE) { if (!info || !info->mem_enabled) { @@ -611,6 +624,23 @@ static int cxld_await_commit(void __iomem *hdm, int id) return -ETIMEDOUT; } +/* + * Default expectation is that decoder base addresses match + * HPA resource values (that is cxlhdm->base_hpa == 0). + */ + +static inline resource_size_t cxl_xlat_to_hpa(resource_size_t base, + struct cxl_hdm *cxlhdm) +{ + return cxlhdm->base_hpa + base; +} + +static inline resource_size_t cxl_xlat_to_base(resource_size_t hpa, + struct cxl_hdm *cxlhdm) +{ + return hpa - cxlhdm->base_hpa; +} + static int cxl_decoder_commit(struct cxl_decoder *cxld) { struct cxl_port *port = to_cxl_port(cxld->dev.parent); @@ -655,7 +685,7 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld) ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id)); cxld_set_interleave(cxld, &ctrl); cxld_set_type(cxld, &ctrl); - base = cxld->hpa_range.start; + base = cxl_xlat_to_base(cxld->hpa_range.start, cxlhdm); size = range_len(&cxld->hpa_range); writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id)); @@ -746,22 +776,27 @@ static int cxl_setup_hdm_decoder_from_dvsec( struct cxl_port *port, struct cxl_decoder *cxld, u64 *dpa_base, int which, struct cxl_endpoint_dvsec_info *info) { + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); struct cxl_endpoint_decoder *cxled; - u64 len; + u64 base, size; int rc; if (!is_cxl_endpoint(port)) return -EOPNOTSUPP; cxled = to_cxl_endpoint_decoder(&cxld->dev); - len = range_len(&info->dvsec_range[which]); - if (!len) + size = range_len(&info->dvsec_range[which]); + if (!size) return -ENOENT; + base = cxl_xlat_to_hpa(info->dvsec_range[which].start, cxlhdm); cxld->target_type = CXL_DECODER_HOSTONLYMEM; cxld->commit = NULL; cxld->reset = NULL; - cxld->hpa_range = info->dvsec_range[which]; + cxld->hpa_range = (struct range) { + .start = base, + .end = base + size -1, + }; /* * Set the emulated decoder as locked pending additional support to @@ -770,14 +805,14 @@ static int cxl_setup_hdm_decoder_from_dvsec( cxld->flags |= CXL_DECODER_F_ENABLE | CXL_DECODER_F_LOCK; port->commit_end = cxld->id; - rc = devm_cxl_dpa_reserve(cxled, *dpa_base, len, 0); + rc = devm_cxl_dpa_reserve(cxled, *dpa_base, size, 0); if (rc) { dev_err(&port->dev, "decoder%d.%d: Failed to reserve DPA range %#llx - %#llx\n (%d)", - port->id, cxld->id, *dpa_base, *dpa_base + len - 1, rc); + port->id, cxld->id, *dpa_base, *dpa_base + size - 1, rc); return rc; } - *dpa_base += len; + *dpa_base += size; cxled->state = CXL_DECODER_STATE_AUTO; return 0; @@ -787,6 +822,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, int *target_map, void __iomem *hdm, int which, u64 *dpa_base, struct cxl_endpoint_dvsec_info *info) { + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); struct cxl_endpoint_decoder *cxled = NULL; u64 size, base, skip, dpa_size, lo, hi; bool committed; @@ -823,6 +859,9 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, if (info) cxled = to_cxl_endpoint_decoder(&cxld->dev); + + base = cxl_xlat_to_hpa(base, cxlhdm); + cxld->hpa_range = (struct range) { .start = base, .end = base + size - 1, @@ -1107,16 +1146,20 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, } for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) { - struct device *cxld_dev; - - cxld_dev = device_find_child(&root->dev, &info->dvsec_range[i], - dvsec_range_allowed); + u64 base = cxl_xlat_to_hpa(info->dvsec_range[i].start, cxlhdm); + u64 size = range_len(&info->dvsec_range[i]); + struct range hpa_range = { + .start = base, + .end = base + size -1, + }; + struct device *cxld_dev __free(put_device) = + cxld_dev = device_find_child(&root->dev, &hpa_range, + dvsec_range_allowed); if (!cxld_dev) { dev_dbg(dev, "DVSEC Range%d denied by platform\n", i); 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Thu, 27 Jun 2024 17:46:55 -0500 From: Robert Richter To: Dan Williams , Davidlohr Bueso , Jonathan Cameron , "Dave Jiang" , Alison Schofield , Vishal Verma , Ira Weiny CC: , , "Robert Richter" Subject: [PATCH 3/5] cxl/acpi: Add platform flag for HPA address translation Date: Fri, 28 Jun 2024 00:46:12 +0200 Message-ID: <20240627224615.854162-4-rrichter@amd.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240627224615.854162-1-rrichter@amd.com> References: <20240627224615.854162-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|SA0PR12MB7075:EE_ X-MS-Office365-Filtering-Correlation-Id: c5978da9-7fb2-4ddf-c1e0-08dc96fb0d2e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 22:46:58.1112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5978da9-7fb2-4ddf-c1e0-08dc96fb0d2e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7075 Adding an early check to detect platform specifics to (later) enable HPA address translation. The cxl_root structure is used to store that information. Note: The platform check will be added later when enabling address translation. Link: https://lore.kernel.org/all/65c68969903b1_afa429460@dwillia2-xfh.jf.intel.com.notmuch/ Cc: Dan Williams Signed-off-by: Robert Richter --- drivers/cxl/acpi.c | 7 +++++++ drivers/cxl/cxl.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 571069863c62..67f73a831bd3 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -536,6 +536,11 @@ static int cxl_get_chbs(struct device *dev, struct acpi_device *hb, return 0; } +static void setup_platform_quirks(struct cxl_root *root) +{ + root->hpa_xlat_enable = 0; +} + static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport) { struct acpi_device *hb = to_cxl_host_bridge(NULL, dev); @@ -838,6 +843,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) return PTR_ERR(cxl_root); root_port = &cxl_root->port; + setup_platform_quirks(cxl_root); + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, add_host_bridge_dport); if (rc < 0) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 603c0120cff8..95d054dc1af0 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -627,10 +627,12 @@ struct cxl_port { * * @port: cxl_port member * @ops: cxl root operations + * @hpa_xlat_enable: enable HPA translation */ struct cxl_root { struct cxl_port port; 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X-Microsoft-Antispam-Message-Info: HxHaHLsBLiTidAXOtXEnukSnW0trQCa7753p+fAr0wVMzzKjdXB4hJscvAHPLYYz2iWJYCeq/j2Ei0Vd9SYjNILOpHO427gq8Lf8d6BbocHojxDN2kOzyn7X5XmeaOnE/UjSCdX2zU3hRu2XsJgLCmea9VWcK0oAa2NlqKrP2m932yaeqdJBSxirihlcLr8znpjqNpGTRi+HBv1tnonKqIvRG+/OfzAGi7BpSyHVzTTQbCIKqDWQxn4M7QsEzvo/FjylCWCzWywKoatoBDB69SsoHovKRJEyv1JmFM7p/0uFCTvQMQSjSw4EbdQzOsPvYv4VkQX4SYYKQ9x5Srevl+jxiGh386RABU9akqTsqmx1RLkwq77R4FTaOVlcs2n+y8abOi0lz60J+VgnjJyyGuUCVbPnvUWmTypFlW86VhegzQDFOTZbXrG0o0JStAH+DJ3HDWsjuxS9QJjZgVoYMKpqvnMKBGvhVIRjUzmF+8eNw72KYEdghFpicDUlC8aTHtImF3TfgrDb+sIZlf43vRVfX2GwrVI+YlXoH0n7bZc4kIsMcuEakorOIFsAm7piocxoWj9Uc6/Z7mapdyIxeJ8Q694m7EzP+nQGLUF9n3Uu4WVPtDvyf6LgeqX+xPAQn9gnDeqcREKVapXaIN5xF5sPV2M4zHFwEE02Z70x7CDp73ZHnv2nF4u9/VFwo4SZpZUiC0vJM6hVje9aZS4m1jrmi9uqc0VjDdsf2XmjmB7ZN6zo+O9rvd0kq2YAA8IbFgorYcpywhNPVuI2XkiH1jJk6HRUJGjfz+N+Y9VcuuK631dSSYzVsa/dZYF05QqTVEamUrqK+991UU1pwAut8ML0xKrC742fOn9+bmSlquvEgBQEd0Z/7XlfyvJr87+FfFJr1JARsx8sjqEr3Fxlk65gnu1XzJJlOSnGywFZGYIyxU1FBRDykf1Ns3Q+pT/bib7VzSqLlc48CIVlddaSIYG67cPhrB9pmhnh5rCgJEOZiwRwC/d6r6SwSBX8mi08cy80L2y/zLi9M3ROrCJnHYuo3oPvqyD7aLeSz/hz518FvEAYuwr5xXwsyAPscTOw8vysR2H4pdX7qzfOj+5gDsBxsNHWtIXdQ6XLdn0hwApIItmX+A+rpTc+LhsI1f9P5M5l8x+P5BJW84rHmTsuYGpbUS+zmw8zuy+PkqXnIAAN4hpgx+oM0PpcNsTfEE7fwDyFW84CiJMwFBqaUl7Mnef3tmWW0pi6j2mce0U3068Jv6EbuS4eBix43aoOcj79QxJrEWqqJvLufWutaHtCvFwR2vdTlT7ea7D+6rQUhqNJ3cjZdBTWO4U6SZEhyYJOx1uHJuIV67jSeazQ7NOqoBtHss0iWDa4NfNcG6tH2CgwIHKb987nOYOFwsCHjAZIi/pUbGR0lyvbwBfmnppL2baODig38vgAW4ZE89kyxB/X6Pm5unxGlDUWZfSk2/KX X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 22:47:01.5565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd70183d-29b8-4c37-daba-08dc96fb0f3e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6133 There are platforms where an address translation between decoder's (HPA) and the system's physical addresses (SPA) is needed. The HPA window in the CFMWS can be used to determine the address offset for the translation. Each CXL endpoint or switch is uniquely attached to a CXL host bridge. The host bridge is assigned a unique HPA window in an CFMWS entry of the CEDT (host bridge is in target list). The hardware base addresses of a CFMWS is an SPA. With that, the offset can be determined using the HDM decoder's base address from the registers and the HPA window in the CFMWS entry of the corresponding CXL host bridge. The CFMWS entries are parsed during host bridge enablement and set up in the CXL root decoder during CXL decoder enumeration before a CXL endpoint is enabled. That is, the endpoint's host bridge's root decoder can be determined. The HPA range of it marks the beginning of the HDM decoder's base address and the offset between both can be used for later address translation. Setup HPA base address (@base_hpa) of a struct cxl_hdm by determining the offset as described. Use the port's host bridge and CXL root port to find the corresponding CXL root decoder containing the HPA window in the bridge's CFMWS entry. Only enable this for platforms with the @hpa_xlat_enable flag set. Signed-off-by: Robert Richter --- drivers/cxl/core/hdm.c | 69 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 50078013f4e3..5164ff807537 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -125,8 +125,73 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) return true; } +static int match_root_decoder(struct device *dev, void *dport_dev) +{ + struct cxl_switch_decoder *cxlsd; + + if (!is_switch_decoder(dev)) + return 0; + + cxlsd = to_cxl_switch_decoder(dev); + + guard(rwsem_read)(&cxl_region_rwsem); + + for (int i = 0; i < cxlsd->nr_targets; i++) { + if (dport_dev == cxlsd->target[i]->dport_dev) + return 1; + } + + return 0; +} + +static struct cxl_decoder *find_root_decoder(struct cxl_port *port, + struct device *dport_dev) +{ + struct device *dev; + + dev = device_find_child(&port->dev, dport_dev, match_root_decoder); + + return dev ? to_cxl_decoder(dev) : NULL; +} + +static void setup_base_hpa_cfmws(struct cxl_hdm *cxlhdm, + struct cxl_root *cxl_root) +{ + struct cxl_port *port = cxlhdm->port; + struct cxl_decoder *cxld; + u64 base; + + if (!port->host_bridge) { + dev_dbg(&port->dev, "No host bridge found for port.\n"); + return; + } + + cxld = find_root_decoder(&cxl_root->port, port->host_bridge); + if (!cxld) { + dev_dbg(&port->dev, + "CFMWS missing for host bridge %s, HPA range not found.\n", + dev_name(port->host_bridge)); + return; + } + + base = cxld->hpa_range.start; + dev_dbg(&port->dev, + "HPA translation for decoders enabled, base 0x%08llx\n", + base); + put_device(&cxld->dev); + + cxlhdm->base_hpa = base; +} + static void setup_base_hpa(struct cxl_hdm *cxlhdm) { + struct cxl_port *port = cxlhdm->port; + + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + + if (!cxl_root) + return; + /* * Address translation is not needed on platforms with HPA == * SPA. HDM decoder addresses all base on system addresses, @@ -134,6 +199,10 @@ static void setup_base_hpa(struct cxl_hdm *cxlhdm) * == 0). Nothing to do here as it is already pre-initialized * zero. */ + if (!cxl_root->hpa_xlat_enable) + return; + + setup_base_hpa_cfmws(cxlhdm, cxl_root); } /** From patchwork Thu Jun 27 22:46:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13715102 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2047.outbound.protection.outlook.com [40.107.94.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 553481A38F7; Thu, 27 Jun 2024 22:47:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719528431; cv=fail; b=UFgJPWBcueLW7tyVOHcvsGWSwJidSCchDiSHeqoUHLoEpPFwik3p2h8OrPBqmhLjxnQ/UgG96YrSylKhLdirUxuIkc12ptHI0jtAABqWVwRDZ85LGv0UZqqrTT5SS8qyOmnyipSJunqcMJEns0IYI2EFMzfyHFWH20LOvTZhu8I= ARC-Message-Signature: i=2; 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Link: https://lore.kernel.org/all/65c68969903b1_afa429460@dwillia2-xfh.jf.intel.com.notmuch/ Cc: Dan Williams Signed-off-by: Robert Richter --- drivers/cxl/acpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 67f73a831bd3..9e7b9629b98d 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -11,6 +11,10 @@ #include "cxlpci.h" #include "cxl.h" +#ifdef CONFIG_X86 +#include +#endif + #define CXL_RCRB_SIZE SZ_8K struct cxl_cxims_data { @@ -536,9 +540,14 @@ static int cxl_get_chbs(struct device *dev, struct acpi_device *hb, return 0; } +static bool is_amd_zen4(void) +{ + return (IS_ENABLED(CONFIG_X86) && boot_cpu_has(X86_FEATURE_ZEN4)); +} + static void setup_platform_quirks(struct cxl_root *root) { - root->hpa_xlat_enable = 0; + root->hpa_xlat_enable = is_amd_zen4(); } static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)