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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac10d1a82sm13530635ad.59.2024.06.28.04.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 04:49:45 -0700 (PDT) From: Andy Chiu Date: Fri, 28 Jun 2024 19:49:12 +0800 Subject: [PATCH] riscv: vector: treat VS_INITIAL as discard MIME-Version: 1.0 Message-Id: <20240628-dev-vstate_discard-v1-1-18e1c5d7997e@sifive.com> X-B4-Tracking: v=1; b=H4sIADejfmYC/x3MQQqAIBBA0avErBPKyqyrRITkVLOxcEQC8e5Jy 7f4PwGjJ2SYqwQeIzHdrqCtK9gv404UZItBNrJvlNTCYhSRgwm4WeLdeCuGUfdqkJPSpoMSPh4 Pev/psub8ATW0KgBkAAAA To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andy Chiu X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_044947_423318_9889180B X-CRM114-Status: GOOD ( 13.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The purpose of riscv_v_vstate_discard() is to invalidate v context at entries of syscalls. So users happen to use v after a syscall without re-configuring would see a failure. It was achieved by setting vector registers and CSRs to -1 and marking the context busy. However, this results in redundant saving of v-context if the process is scheduled out in a syscall. Moreover, restoring the invalidated context from memory is a costly operation. In fact, all can be prevented if we can delay vstate_discard before returning back to the user space. To be more specific, the kernel can mark v-context as INITIAL and set the restore flag at syscall entries. This is the indication for the vstate_restore, so it awares that the vstate has to be invalidated before returning back to the user space. After applying this patch, the context switch performance has improved 6.78% on vector enabled lmbench running on a FPGA with VLEN=512. The result was obtained by averaging the output from the following command. $ lat_ctx 2 Before the patch: 599.8357692 After the patch: 559.1748148 Signed-off-by: Andy Chiu --- arch/riscv/include/asm/vector.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) --- base-commit: 60a6707f582ebbdfb6b378f45d7bf929106a1cd5 change-id: 20240628-dev-vstate_discard-5784652968a3 Best regards, diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index be7d309cca8a..1221f8b8f564 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -170,8 +170,8 @@ static inline void riscv_v_vstate_discard(struct pt_regs *regs) if ((regs->status & SR_VS) == SR_VS_OFF) return; - __riscv_v_vstate_discard(); - __riscv_v_vstate_dirty(regs); + set_tsk_thread_flag(current, TIF_RISCV_V_DEFER_RESTORE); + riscv_v_vstate_on(regs); } static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, @@ -186,7 +186,9 @@ static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vstate, struct pt_regs *regs) { - if ((regs->status & SR_VS) != SR_VS_OFF) { + if ((regs->status & SR_VS) == SR_VS_INITIAL) { + __riscv_v_vstate_discard(); + } else if ((regs->status & SR_VS) != SR_VS_OFF) { __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -197,7 +199,7 @@ static inline void riscv_v_vstate_set_restore(struct task_struct *task, { if ((regs->status & SR_VS) != SR_VS_OFF) { set_tsk_thread_flag(task, TIF_RISCV_V_DEFER_RESTORE); - riscv_v_vstate_on(regs); + __riscv_v_vstate_clean(regs); } }