From patchwork Fri Jun 28 11:59:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13716013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A3B7C30658 for ; Fri, 28 Jun 2024 12:00:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qK6xIM0pV+FTE9Uo6kaAlY9Ea6JxGt7I6kcv7J0RJGg=; b=x979OclTan0ePw XnTCi8++0PGO9FSKZlnOxpBKqKLGcARNObp2jIVLxNEazArRO/cx+7C6dja8NayKSSMmS2PVhU2Vk 1kGdFylhiAEz0qBRknO1BemwbwAmawq4NrhSikexrIMt6LQr5pWocsigPejU8mR0Ep6AasCHUePCJ QATgm4Dr3eozKJeo+BQa6IvX2d9FAKWsvN79zGYzKxsffojqCeBd8Q1+JsPKNIOA86Slh5ZPWEYQs eNq7SO89jBfAcNQBIfEHWWtMqdbWTjZvKd1+GEhIq4IGTd4tmRwbPo8unwjMkOtzPnK7GQFao/xGq lBJ9x1k0dXyE17NGDz6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGt-0000000DcB6-3AWm; Fri, 28 Jun 2024 12:00:07 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGp-0000000Dc8e-1zTW for linux-riscv@lists.infradead.org; Fri, 28 Jun 2024 12:00:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719576003; x=1751112003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pnR4pmsg5MGAcoqhuGjuhjHJEgVUH86UycujeWipnZw=; b=izikoAxUa7ulJc9/fji5uks23VLbzs+g49up9E/X615W73oG6jXFfjyk 2AZtFNWEhORe8PsGDTOAE2tQuqsyOmizRpPKoXa8tlT7NMSKscKmq8uMj al1kto463RFX/mFaPc5I27EntahG97fZ3WHGS4ESoG5rP9qfwGPKFVr3t BFRBVgM7RxzLmJvbuz9zFvwvJ1O6dhJDUihw42YjOX5NClt8WpBm4UJef ulxaFtPFtziSP7RAEJ4n84gdEj8RkUPglJ8vMHtJG6iJucOko10eldZBF O+8vUtr8sB+rXTkYio21jFQNqKKvSUmgZMpz7FMTolM82z84n5W9cwGGZ Q==; X-CSE-ConnectionGUID: fhzcQ281QiKf1QfzQI0hzg== X-CSE-MsgGUID: 7a9N9JiwQoaqIAb8otbLqA== X-IronPort-AV: E=Sophos;i="6.09,169,1716274800"; d="scan'208";a="259502560" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 05:00:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 04:59:27 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 04:59:25 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 1/3] PCI: microchip: Fix outbound address translation tables Date: Fri, 28 Jun 2024 12:59:21 +0100 Message-ID: <20240628115923.4133286-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628115923.4133286-1-daire.mcnamara@microchip.com> References: <20240628115923.4133286-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_050003_619825_BD45CE7A X-CRM114-Status: GOOD ( 13.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. This necessitates changing a size_t in mc_pcie_setup_window to a resource_size_t to avoid a compile error on 32-bit platforms. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..47c397ae515a 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -23,6 +23,8 @@ /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -933,7 +935,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + resource_size_t size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +985,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1120,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win); From patchwork Fri Jun 28 11:59:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13716015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 322E9C3065B for ; Fri, 28 Jun 2024 12:00:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IxQvpadQ+CGFims6nigriCyrzJGScxsqJB62mAbm6/s=; b=sbXREbRsaE2gs3 oeTHG1MKaQ2o4tVjuiT7wmELxeZtlI10WqFQsKRvhLXgyEJiiWLXZBBov9B8aLC5kHT2MYywoervs bqFTEpQVZCUoYhnB2ZJ7Hy5BNeFkxgeJItWjgPhnlZFK7/RXJV5Rw6OAbb9FrtxJDtR3RZqpS2Jn5 ZTlKz0/amQym+4GYKfbD/DV5N5YaQkkvHdtWYFvVUyG4WE4ZyryAyNMFswWRj5W8IYY85whC4Vh6c 2hT8j4JUv1qGYIyiS2T6SeSPWjmY6l9zjCEhDyQBrBSBQa41yRnNQYHrIkaDSN1OqzsqZKyz3gIn0 lwCwU9EKOiCxpAVLiFlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGu-0000000DcBb-2OJK; Fri, 28 Jun 2024 12:00:08 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGp-0000000Dc9G-2F7u for linux-riscv@lists.infradead.org; Fri, 28 Jun 2024 12:00:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719576003; x=1751112003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2LGfejxUQh2ogeG58xChGdC3cor015XXbvEcy1WCcwc=; b=a7aXF6b3b6nlqIGHQHZ9TWE9qVlGb87vUTRZNc5T8CtGbqJbnPUi/icE coztY8Nd1S6IsxCRO3bk6hVFqssL3oHmpxhE6sVGZSwEyikwWuZEKo9vE YEbRfQFRi2UFghpRyzZOjirCIbHMsl95XpVQkcdnyLBMUlyHH8TW3povW zx591cxCBbaeSS+gLTFdxaLWMT6oBaav8dtS6olgVRQLfMSuR5Dt2ooJq VdtYEgDK9Px9Y8ckiYOk2ObxZcpzmHbSZhq6BycBOexuck8IqqMo08v0V J0bGV40nTkcCGxkmZQ7rH3sHxrLF/YS/LsVdEJ0Tclmks9ziJ6FKB61dd Q==; X-CSE-ConnectionGUID: fhzcQ281QiKf1QfzQI0hzg== X-CSE-MsgGUID: Ye5I7pgLSbGEftYhiCzhBw== X-IronPort-AV: E=Sophos;i="6.09,169,1716274800"; d="scan'208";a="259502561" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 05:00:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 04:59:30 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 04:59:27 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 2/3] PCI: microchip: Fix inbound address translation tables Date: Fri, 28 Jun 2024 12:59:22 +0100 Message-ID: <20240628115923.4133286-3-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628115923.4133286-1-daire.mcnamara@microchip.com> References: <20240628115923.4133286-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_050003_639431_F120732E X-CRM114-Status: GOOD ( 21.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC the PCIe Root Port can be behind one of three general purpose Fabric Interface Controller (FIC) buses that encapsulates an AXI-S bus. Depending on which FIC(s) the Root Port is connected through to CPU space, and what address translation is done by that FIC, the Root Port driver's inbound address translation may vary. For all current supported designs and all future expected designs, inbound address translation done by a FIC on PolarFire SoC varies depending on whether PolarFire SoC in operating in dma-coherent mode or dma-noncoherent mode. The setup of the outbound address translation tables in the root port driver only needs to handle these two cases. Setup the inbound address translation tables to one of two address translations, depending on whether the rootport is marked as dma-coherent or dma-noncoherent. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 106 +++++++++++++++++-- 1 file changed, 97 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 47c397ae515a..27bfa3b7a187 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -7,16 +7,20 @@ * Author: Daire McNamara */ +#include #include +#include #include #include #include +#include #include #include #include #include #include #include +#include #include "../pci.h" @@ -32,6 +36,9 @@ #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) +#define MC_MAX_NUM_INBOUND_WINDOWS 8 +#define MPFS_NC_BOUNCE_ADDR 0x80000000 + /* PCIe Bridge Phy Regs */ #define PCIE_PCI_IRQ_DW0 0xa8 #define MSIX_CAP_MASK BIT(31) @@ -99,14 +106,15 @@ /* PCIe AXI slave table init defines */ #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u -#define ATR_SIZE_SHIFT 1 -#define ATR_IMPL_ENABLE 1 +#define ATR_SIZE_MASK GENMASK(6, 1) +#define ATR_IMPL_ENABLE BIT(0) #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u #define PCIE_TX_RX_INTERFACE 0x00000000u #define PCIE_CONFIG_INTERFACE 0x00000001u +#define TRSL_ID_AXI4_MASTER_0 0x00000004u #define ATR_ENTRY_SIZE 32 @@ -933,6 +941,86 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) return mc_allocate_msi_domains(port); } +static void mc_pcie_setup_inbound_atr(int window_index, u64 axi_addr, u64 pcie_addr, u64 size) +{ + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + u32 table_offset = window_index * ATR_ENTRY_SIZE; + void __iomem *table_addr = bridge_base_addr + table_offset; + u32 atr_sz; + u32 val; + + atr_sz = ilog2(size) - 1; + + val = ALIGN_DOWN(lower_32_bits(pcie_addr), SZ_4K); + val |= FIELD_PREP(ATR_SIZE_MASK, atr_sz); + val |= ATR_IMPL_ENABLE; + + writel(val, table_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); + + writel(upper_32_bits(pcie_addr), table_addr + ATR0_PCIE_WIN0_SRC_ADDR); + + writel(lower_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_LSB); + writel(upper_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_UDW); + + writel(TRSL_ID_AXI4_MASTER_0, table_addr + ATR0_PCIE_WIN0_TRSL_PARAM); +} + +static int mc_pcie_setup_inbound_ranges(struct platform_device *pdev, struct mc_pcie *port) +{ + struct device *dev = &pdev->dev; + struct device_node *dn = dev->of_node; + struct of_range_parser parser; + struct of_range range; + int atr_index = 0; + + /* + * MPFS PCIe root port is 32-bit only, behind a Fabric Interface + * Controller FPGA logic block which contains the AXI-S interface. + * + * From the point of view of the PCIe root port, There are only + * two supported Root Port configurations + * + * Configuration 1: for use with fully coherent designs; supports a + * window from 0x0 (CPU space) to specified PCIe space. + * + * Configuration 2: for use with non-coherent designs; supports two + * 1 Gb wide windows to CPU space; one mapping cpu space 0 to pcie + * space 0x80000000 and mapping cpu space 0x40000000 to pcie + * space 0xc0000000. This cfg needs two windows because of how + * the MSI space is allocated in the AXI-S range on MPFS. + * + * The FIC interface outside the PCIe block *must* complete the inbound + * address translation as per MCHP MPFS FPGA design guidelines. + */ + if (device_property_read_bool(dev, "dma-noncoherent")) { + /* + * Always need same two tables in this case. Need two tables + * due to hardware interactions between address and size. + */ + mc_pcie_setup_inbound_atr(0, 0, MPFS_NC_BOUNCE_ADDR, SZ_1G); + mc_pcie_setup_inbound_atr(1, SZ_1G, MPFS_NC_BOUNCE_ADDR + SZ_1G, SZ_1G); + } else { + /* Find any dma-ranges */ + if (of_pci_dma_range_parser_init(&parser, dn)) { + /* No dma-range property - setup default */ + mc_pcie_setup_inbound_atr(0, 0, 0, SZ_4G); + return 0; + } + + for_each_of_range(&parser, &range) { + if (atr_index >= MC_MAX_NUM_INBOUND_WINDOWS) { + dev_err(dev, "too many inbound ranges; %d available tables\n", + MC_MAX_NUM_INBOUND_WINDOWS); + return -EINVAL; + } + mc_pcie_setup_inbound_atr(atr_index, 0, range.pci_addr, range.size); + atr_index++; + } + } + + return 0; +} + static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, resource_size_t size) @@ -948,8 +1036,9 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ATR0_AXI4_SLV0_TRSL_PARAM); - val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | - ATR_IMPL_ENABLE; + val = ALIGN_DOWN(lower_32_bits(axi_addr), SZ_4K); + val |= FIELD_PREP(ATR_SIZE_MASK, atr_sz); + val |= ATR_IMPL_ENABLE; writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ATR0_AXI4_SLV0_SRCADDR_PARAM); @@ -964,11 +1053,6 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, val = upper_32_bits(pci_addr); writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ATR0_AXI4_SLV0_TRSL_ADDR_UDW); - - val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); - val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); - writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); - writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); } static int mc_pcie_setup_windows(struct platform_device *pdev, @@ -1131,6 +1215,10 @@ static int mc_platform_init(struct pci_config_window *cfg) if (ret) return ret; + ret = mc_pcie_setup_inbound_ranges(pdev, port); + if (ret) + return ret; + /* Address translation is up; safe to enable interrupts */ ret = mc_init_interrupts(pdev, port); if (ret) From patchwork Fri Jun 28 11:59:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13716014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA436C3064D for ; Fri, 28 Jun 2024 12:00:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gPt8lQBUOldLppnxdjFBCxdG7ySO8ixWarlF8kkCM/A=; b=1OgnKMJbArxuF/ Al30PoK+JZ3WFqlSawxnoa3T6BpV7g/mzl8xme/SneBPkoDmwWWV0HfHajhl2CmjsfDYqnomoGqYz 5rvs/TseWA/5YEFy8UZRA1B1BmXYtVOfxHKOk7Etn3OQCg1d/vryKYhnINvXeLy0wUDy7AyhcQedO hyjCPmyCUUdkj/PyUMeX//RtlvfQX0MIWHQXXE523ojcjgAbFPMRm9bDdlJ47308ygNxW4ysg4fw4 AWX0shDKC+24ezt2TCO2chMyHcL3ZQ2tlgZYQCdrcGtYVhERiJpqR8uCh9H/VDXfJaytk4zauwsaM 9bElPjg8hczpUqM+wFkw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGv-0000000DcCL-1mmU; Fri, 28 Jun 2024 12:00:09 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGq-0000000Dc8e-3gi9 for linux-riscv@lists.infradead.org; Fri, 28 Jun 2024 12:00:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719576005; x=1751112005; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jiUij3wRRe5sE48zPdwi6+NvzYyJIr+GpOYj/SVthjg=; b=fnU25ytTjIV7buyNEcydSfbia5xiOOd5UuPtFFncKAbH6ebPfFQxg5id Crvw7bE5zf8JNX/7dV23/Ni0s4do55qihpToRB00g1J3TfT+Jfci5/IbM uY2e+rRcjU5hROKx78/aHV/xJ1GYvXJNoKdUun5+Z3QYQkgLon/3t63hc cQ4wBwtCmwZXrJABLwOvwvzcKAhrtW2nbglmiWs505obC2zXVXqTevU3c 9CvUddNDhtwEQQuFs3rE7LyU1iZ49nS6fVHYGeqK9sOz8VBNEr57L7Nj5 L9l9tmELdFGQzq4M5mPzqYisBlN+YAhDMzxc9n/NEf91xPSg8TDncosNp w==; X-CSE-ConnectionGUID: fhzcQ281QiKf1QfzQI0hzg== X-CSE-MsgGUID: R+AVEiQ/TTmD0N108NexvA== X-IronPort-AV: E=Sophos;i="6.09,169,1716274800"; d="scan'208";a="259502562" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 05:00:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 04:59:34 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 04:59:30 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent Date: Fri, 28 Jun 2024 12:59:23 +0100 Message-ID: <20240628115923.4133286-4-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628115923.4133286-1-daire.mcnamara@microchip.com> References: <20240628115923.4133286-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_050005_002078_472398BD X-CRM114-Status: UNSURE ( 7.48 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..c84e1ae20532 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -52,6 +52,8 @@ properties: items: pattern: '^fic[0-3]$' + dma-noncoherent: true + interrupts: minItems: 1 items: