From patchwork Fri Jun 28 12:01:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 13716018 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC90F158219; Fri, 28 Jun 2024 12:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576129; cv=none; b=sbXMZJd8PGuRsWsioX0sj3ynxrR376gclmTmrxyjZZk8QOSwUuEBGabt2T4KmJfkON4eBk3kKdzIoUJNM9H8CLtJ/y64Yl/HnUD3/phQzZbs7KKkOGiEBfwSCFQYjq594+rLPeAJ0H5UIxPj7De/i30lr3MLUlY/RToF7qwlBsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576129; c=relaxed/simple; bh=DFZ+DpUdYBlf0BVEHrX6jkQ9kCwsFKSKnquvFKSm0rM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kn85Ud3yrxjuppaPz7TLGePShr+bbD2WfPMs3kSk035aJ+LDCRIu2znEoQdmDPqt42rKk389DEfDwC6R0yUbZdiKWgL/o8hvfDjH9wUfc4CSmmZsKOaPDwCOCPNy2yvAj6+0wyPBUX1mLLJB3Sbc0kCSEqrYHZziGdXZ56Oded4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fXYkDGyM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fXYkDGyM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D25C7C32786; Fri, 28 Jun 2024 12:02:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719576128; bh=DFZ+DpUdYBlf0BVEHrX6jkQ9kCwsFKSKnquvFKSm0rM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fXYkDGyMDzU4+C2TVpGEXXbVPBU8xjVTNtUUMRHEIWpjOV1da5C6QQftpwc+4ORyN IMuHjad8i0Qab5w6mJgG+fzg1amK0u1588ZnLQh1JsqecFjJUuqNS8tlRYRA7F696u wjPhaoDv3mSp8VKIz6aTUPSfl1gHu8esCjhl2ISxzzjpi3eFnXppydykdwAUv6eXju V2L1KB0vThwSEhWJciiJzxrMjGCkC9QbFkhyjPXPtdNbAqMau2kydZzZGfzccZkqWs GAiLwiiFO5FUaKX72oizZYYFcbUZ2TaBGJWnrpn10i3pLaT4g2CBl4b0zBwUsvIf4+ DkGNyMC+EliKg== From: Roger Quadros Date: Fri, 28 Jun 2024 15:01:50 +0300 Subject: [PATCH net-next v2 1/7] net: ethernet: ti: am65-cpsw: Introduce multi queue Rx Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240628-am65-cpsw-multi-rx-v2-1-c399cb77db56@kernel.org> References: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> In-Reply-To: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=31448; i=rogerq@kernel.org; h=from:subject:message-id; bh=DFZ+DpUdYBlf0BVEHrX6jkQ9kCwsFKSKnquvFKSm0rM=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4KI+qa2ZdDHBrlS/suRyhSLRmSUgxcg/eS YaKyYoM0JSJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw k0C0D/9Iybzzq4h1XXVDwtS5dIiT/zmZzaSj/qazpDqSrDgC9t1xTYtgeLg97ClWXRYQyIoiTlG mJX1otOScaoknrlagxUr2j9fF/7fO5KzGZuW5KYh+yOrZ9L01xpjc/3MxcFD2mRF5SBwnyVhsd0 JGcN8Z0410ritFf1QYBqL4BqE+0AiY6YPpZpWgV5HrnyhqwDd0Wt31Y+OxBXLebXA8O8BbTWvGc bybtmoPzQka1I1BqOTecBfgazXxCb61g2rZ/vB061Uja+uF9SGoFbEHuqCzX4QPr547Y1fFWl1s 5veTSFEmaw87hFdn1+kcnpBPnmcCutIHySfAE1kz/8v7jPprhQHpZGJ+KMocQSdaybYv7kX7jS+ mlpjq8dJRjqgAZblrAKvMEvp9hIZqGsAVScxx1cu5bWWbkmqQ2RpSDwQxB3zW4vynOr8/9uHvUt t52dCcSwMi4sGbHJGXCEyIJO1glFrY5QTkHNF8/vci1un3iXjVArVgIf1B7oOhhujWkjrq83iWD YLfRO0gueNum78ZtzzMf7jVIBjLyp4ten2x5H/LYDVc9gLrNfs+uSOECP3p5TbMNkOspws3x7EJ d5HZgitIcTBvwnsDwohgNFf3BjJx+SQRgukz41nL62NF0DCrcRLMK6pQ1700JO6YCBdCR6tpZ6X kZQoXEpiVy51XPA== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 am65-cpsw can support up to 8 queues at Rx. Use a macro AM65_CPSW_MAX_RX_QUEUES to indicate that. As there is only one DMA channel for RX traffic, the 8 queues come as 8 flows in that channel. By default, we will start with 1 flow as defined by the macro AM65_CPSW_DEFAULT_RX_CHN_FLOWS. User can change the number of flows by ethtool like so 'ethtool -L ethx rx ' All traffic will still come on flow 0. To get traffic on different flows the Classifiers will need to be set up. Signed-off-by: Roger Quadros Reviewed-by: Simon Horman --- drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 59 +++-- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 358 ++++++++++++++++------------ drivers/net/ethernet/ti/am65-cpsw-nuss.h | 35 +-- 3 files changed, 272 insertions(+), 180 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c index a1d0935d1ebe..3106bf07eb1a 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c +++ b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c @@ -429,7 +429,7 @@ static void am65_cpsw_get_channels(struct net_device *ndev, ch->max_rx = AM65_CPSW_MAX_RX_QUEUES; ch->max_tx = AM65_CPSW_MAX_TX_QUEUES; - ch->rx_count = AM65_CPSW_MAX_RX_QUEUES; + ch->rx_count = common->rx_ch_num_flows; ch->tx_count = common->tx_ch_num; } @@ -448,8 +448,9 @@ static int am65_cpsw_set_channels(struct net_device *ndev, return -EBUSY; am65_cpsw_nuss_remove_tx_chns(common); + am65_cpsw_nuss_remove_rx_chns(common); - return am65_cpsw_nuss_update_tx_chns(common, chs->tx_count); + return am65_cpsw_nuss_update_tx_rx_chns(common, chs->tx_count, chs->rx_count); } static void @@ -921,10 +922,12 @@ static int am65_cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coales { struct am65_cpsw_common *common = am65_ndev_to_common(ndev); struct am65_cpsw_tx_chn *tx_chn; + struct am65_cpsw_rx_flow *rx_flow; tx_chn = &common->tx_chns[0]; + rx_flow = &common->rx_chns.flows[0]; - coal->rx_coalesce_usecs = common->rx_pace_timeout / 1000; + coal->rx_coalesce_usecs = rx_flow->rx_pace_timeout / 1000; coal->tx_coalesce_usecs = tx_chn->tx_pace_timeout / 1000; return 0; @@ -935,13 +938,24 @@ static int am65_cpsw_get_per_queue_coalesce(struct net_device *ndev, u32 queue, { struct am65_cpsw_common *common = am65_ndev_to_common(ndev); struct am65_cpsw_tx_chn *tx_chn; + struct am65_cpsw_rx_flow *rx_flow; - if (queue >= AM65_CPSW_MAX_TX_QUEUES) + if (queue >= AM65_CPSW_MAX_TX_QUEUES && queue >= AM65_CPSW_MAX_RX_QUEUES) return -EINVAL; - tx_chn = &common->tx_chns[queue]; + if (queue < AM65_CPSW_MAX_TX_QUEUES) { + tx_chn = &common->tx_chns[queue]; + coal->tx_coalesce_usecs = tx_chn->tx_pace_timeout / 1000; + } else { + coal->tx_coalesce_usecs = ~0; + } - coal->tx_coalesce_usecs = tx_chn->tx_pace_timeout / 1000; + if (queue < AM65_CPSW_MAX_RX_QUEUES) { + rx_flow = &common->rx_chns.flows[queue]; + coal->rx_coalesce_usecs = rx_flow->rx_pace_timeout / 1000; + } else { + coal->rx_coalesce_usecs = ~0; + } return 0; } @@ -952,8 +966,10 @@ static int am65_cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coales { struct am65_cpsw_common *common = am65_ndev_to_common(ndev); struct am65_cpsw_tx_chn *tx_chn; + struct am65_cpsw_rx_flow *rx_flow; tx_chn = &common->tx_chns[0]; + rx_flow = &common->rx_chns.flows[0]; if (coal->rx_coalesce_usecs && coal->rx_coalesce_usecs < 20) return -EINVAL; @@ -961,7 +977,7 @@ static int am65_cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coales if (coal->tx_coalesce_usecs && coal->tx_coalesce_usecs < 20) return -EINVAL; - common->rx_pace_timeout = coal->rx_coalesce_usecs * 1000; + rx_flow->rx_pace_timeout = coal->rx_coalesce_usecs * 1000; tx_chn->tx_pace_timeout = coal->tx_coalesce_usecs * 1000; return 0; @@ -972,19 +988,34 @@ static int am65_cpsw_set_per_queue_coalesce(struct net_device *ndev, u32 queue, { struct am65_cpsw_common *common = am65_ndev_to_common(ndev); struct am65_cpsw_tx_chn *tx_chn; + struct am65_cpsw_rx_flow *rx_flow; - if (queue >= AM65_CPSW_MAX_TX_QUEUES) + if (queue >= AM65_CPSW_MAX_TX_QUEUES && queue >= AM65_CPSW_MAX_RX_QUEUES) return -EINVAL; - tx_chn = &common->tx_chns[queue]; + if (queue < AM65_CPSW_MAX_TX_QUEUES) { + tx_chn = &common->tx_chns[queue]; + + if (coal->tx_coalesce_usecs && coal->tx_coalesce_usecs < 20) { + dev_info(common->dev, "defaulting to min value of 20us for tx-usecs for tx-%u\n", + queue); + coal->tx_coalesce_usecs = 20; + } - if (coal->tx_coalesce_usecs && coal->tx_coalesce_usecs < 20) { - dev_info(common->dev, "defaulting to min value of 20us for tx-usecs for tx-%u\n", - queue); - coal->tx_coalesce_usecs = 20; + tx_chn->tx_pace_timeout = coal->tx_coalesce_usecs * 1000; } - tx_chn->tx_pace_timeout = coal->tx_coalesce_usecs * 1000; + if (queue < AM65_CPSW_MAX_RX_QUEUES) { + rx_flow = &common->rx_chns.flows[queue]; + + if (coal->rx_coalesce_usecs && coal->rx_coalesce_usecs < 20) { + dev_info(common->dev, "defaulting to min value of 20us for rx-usecs for rx-%u\n", + queue); + coal->rx_coalesce_usecs = 20; + } + + rx_flow->rx_pace_timeout = coal->rx_coalesce_usecs * 1000; + } return 0; } diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 81d9f21086ec..f6c664dfc1fa 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -138,7 +138,7 @@ AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 -/* Number of TX/RX descriptors */ +/* Number of TX/RX descriptors per channel/flow */ #define AM65_CPSW_MAX_TX_DESC 500 #define AM65_CPSW_MAX_RX_DESC 500 @@ -150,6 +150,7 @@ NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) #define AM65_CPSW_DEFAULT_TX_CHNS 8 +#define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 /* CPPI streaming packet interface */ #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF @@ -330,7 +331,7 @@ static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, } static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, - struct page *page) + struct page *page, u32 flow_idx) { struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; struct cppi5_host_desc_t *desc_rx; @@ -363,7 +364,8 @@ static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, swdata = cppi5_hdesc_get_swdata(desc_rx); *((void **)swdata) = page_address(page); - return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); + return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, + desc_rx, desc_dma); } void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) @@ -398,22 +400,27 @@ static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); static void am65_cpsw_destroy_xdp_rxqs(struct am65_cpsw_common *common) { struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; + struct am65_cpsw_rx_flow *flow; struct xdp_rxq_info *rxq; - int i; + int id, port; - for (i = 0; i < common->port_num; i++) { - if (!common->ports[i].ndev) - continue; + for (id = 0; id < common->rx_ch_num_flows; id++) { + flow = &rx_chn->flows[id]; - rxq = &common->ports[i].xdp_rxq; + for (port = 0; port < common->port_num; port++) { + if (!common->ports[port].ndev) + continue; - if (xdp_rxq_info_is_reg(rxq)) - xdp_rxq_info_unreg(rxq); - } + rxq = &common->ports[port].xdp_rxq[id]; - if (rx_chn->page_pool) { - page_pool_destroy(rx_chn->page_pool); - rx_chn->page_pool = NULL; + if (xdp_rxq_info_is_reg(rxq)) + xdp_rxq_info_unreg(rxq); + } + + if (flow->page_pool) { + page_pool_destroy(flow->page_pool); + flow->page_pool = NULL; + } } } @@ -427,31 +434,42 @@ static int am65_cpsw_create_xdp_rxqs(struct am65_cpsw_common *common) .nid = dev_to_node(common->dev), .dev = common->dev, .dma_dir = DMA_BIDIRECTIONAL, - .napi = &common->napi_rx, + /* .napi set dynamically */ }; + struct am65_cpsw_rx_flow *flow; struct xdp_rxq_info *rxq; struct page_pool *pool; - int i, ret; - - pool = page_pool_create(&pp_params); - if (IS_ERR(pool)) - return PTR_ERR(pool); + int id, port, ret; + + for (id = 0; id < common->rx_ch_num_flows; id++) { + flow = &rx_chn->flows[id]; + pp_params.napi = &flow->napi_rx; + pool = page_pool_create(&pp_params); + if (IS_ERR(pool)) { + ret = PTR_ERR(pool); + goto err; + } - rx_chn->page_pool = pool; + flow->page_pool = pool; - for (i = 0; i < common->port_num; i++) { - if (!common->ports[i].ndev) - continue; + /* using same page pool is allowed as no running rx handlers + * simultaneously for both ndevs + */ + for (port = 0; port < common->port_num; port++) { + if (!common->ports[port].ndev) + continue; - rxq = &common->ports[i].xdp_rxq; + rxq = &common->ports[port].xdp_rxq[id]; - ret = xdp_rxq_info_reg(rxq, common->ports[i].ndev, i, 0); - if (ret) - goto err; + ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, + id, flow->napi_rx.napi_id); + if (ret) + goto err; - ret = xdp_rxq_info_reg_mem_model(rxq, MEM_TYPE_PAGE_POOL, pool); - if (ret) - goto err; + ret = xdp_rxq_info_reg_mem_model(rxq, MEM_TYPE_PAGE_POOL, pool); + if (ret) + goto err; + } } return 0; @@ -496,25 +514,27 @@ static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_ch desc_idx); } -static inline void am65_cpsw_put_page(struct am65_cpsw_rx_chn *rx_chn, +static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, struct page *page, bool allow_direct, int desc_idx) { - page_pool_put_full_page(rx_chn->page_pool, page, allow_direct); - rx_chn->pages[desc_idx] = NULL; + page_pool_put_full_page(flow->page_pool, page, allow_direct); + flow->pages[desc_idx] = NULL; } static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) { - struct am65_cpsw_rx_chn *rx_chn = data; + struct am65_cpsw_rx_flow *flow = data; struct cppi5_host_desc_t *desc_rx; + struct am65_cpsw_rx_chn *rx_chn; dma_addr_t buf_dma; u32 buf_dma_len; void *page_addr; void **swdata; int desc_idx; + rx_chn = &flow->common->rx_chns; desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); swdata = cppi5_hdesc_get_swdata(desc_rx); page_addr = *swdata; @@ -525,7 +545,7 @@ static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, rx_chn->dsize_log2); - am65_cpsw_put_page(rx_chn, virt_to_page(page_addr), false, desc_idx); + am65_cpsw_put_page(flow, virt_to_page(page_addr), false, desc_idx); } static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, @@ -601,7 +621,8 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) struct am65_cpsw_host *host_p = am65_common_get_host(common); struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; - int port_idx, i, ret, tx; + int port_idx, i, ret, tx, flow_idx; + struct am65_cpsw_rx_flow *flow; u32 val, port_mask; struct page *page; @@ -669,27 +690,32 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) return ret; } - for (i = 0; i < rx_chn->descs_num; i++) { - page = page_pool_dev_alloc_pages(rx_chn->page_pool); - if (!page) { - ret = -ENOMEM; - if (i) - goto fail_rx; + for (flow_idx = 0; flow_idx < common->rx_ch_num_flows; flow_idx++) { + flow = &rx_chn->flows[flow_idx]; + for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { + page = page_pool_dev_alloc_pages(flow->page_pool); + if (!page) { + dev_err(common->dev, "cannot allocate page in flow %d\n", + flow_idx); + ret = -ENOMEM; + if (i) + goto fail_rx; - return ret; - } - rx_chn->pages[i] = page; + return ret; + } + flow->pages[i] = page; - ret = am65_cpsw_nuss_rx_push(common, page); - if (ret < 0) { - dev_err(common->dev, - "cannot submit page to channel rx: %d\n", - ret); - am65_cpsw_put_page(rx_chn, page, false, i); - if (i) - goto fail_rx; + ret = am65_cpsw_nuss_rx_push(common, page, flow_idx); + if (ret < 0) { + dev_err(common->dev, + "cannot submit page to rx channel flow %d, error %d\n", + flow_idx, ret); + am65_cpsw_put_page(flow, page, false, i); + if (i) + goto fail_rx; - return ret; + return ret; + } } } @@ -699,6 +725,14 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) goto fail_rx; } + for (i = 0; i < common->rx_ch_num_flows ; i++) { + napi_enable(&common->rx_chns.flows[i].napi_rx); + if (common->rx_chns.flows[i].irq_disabled) { + common->rx_chns.flows[i].irq_disabled = false; + enable_irq(common->rx_chns.flows[i].irq); + } + } + for (tx = 0; tx < common->tx_ch_num; tx++) { ret = k3_udma_glue_enable_tx_chn(tx_chn[tx].tx_chn); if (ret) { @@ -710,12 +744,6 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) napi_enable(&tx_chn[tx].napi_tx); } - napi_enable(&common->napi_rx); - if (common->rx_irq_disabled) { - common->rx_irq_disabled = false; - enable_irq(rx_chn->irq); - } - dev_dbg(common->dev, "cpsw_nuss started\n"); return 0; @@ -726,11 +754,24 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) tx--; } + for (flow_idx = 0; i < common->rx_ch_num_flows; flow_idx++) { + flow = &rx_chn->flows[flow_idx]; + if (!flow->irq_disabled) { + disable_irq(flow->irq); + flow->irq_disabled = true; + } + napi_disable(&flow->napi_rx); + } + k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); fail_rx: - k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, 0, rx_chn, - am65_cpsw_nuss_rx_cleanup, 0); + for (i = 0; i < common->rx_ch_num_flows; i--) + k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, &rx_chn->flows[i], + am65_cpsw_nuss_rx_cleanup, !!i); + + am65_cpsw_destroy_xdp_rxqs(common); + return ret; } @@ -779,12 +820,12 @@ static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) dev_err(common->dev, "rx teardown timeout\n"); } - napi_disable(&common->napi_rx); - hrtimer_cancel(&common->rx_hrtimer); - - for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) - k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, rx_chn, + for (i = 0; i < common->rx_ch_num_flows; i++) { + napi_disable(&common->rx_chns.flows[i].napi_rx); + hrtimer_cancel(&common->rx_chns.flows[i].rx_hrtimer); + k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, &rx_chn->flows[i], am65_cpsw_nuss_rx_cleanup, !!i); + } k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); @@ -793,10 +834,6 @@ static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); - for (i = 0; i < rx_chn->descs_num; i++) { - if (rx_chn->pages[i]) - am65_cpsw_put_page(rx_chn, rx_chn->pages[i], false, i); - } am65_cpsw_destroy_xdp_rxqs(common); dev_dbg(common->dev, "cpsw_nuss stopped\n"); @@ -867,7 +904,7 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) goto runtime_put; } - ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); + ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); if (ret) { dev_err(common->dev, "cannot set real number of rx queues\n"); goto runtime_put; @@ -990,12 +1027,12 @@ static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, return ret; } -static int am65_cpsw_run_xdp(struct am65_cpsw_common *common, +static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, struct am65_cpsw_port *port, struct xdp_buff *xdp, int desc_idx, int cpu, int *len) { - struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; + struct am65_cpsw_common *common = flow->common; struct net_device *ndev = port->ndev; int ret = AM65_CPSW_XDP_CONSUMED; struct am65_cpsw_tx_chn *tx_chn; @@ -1055,7 +1092,7 @@ static int am65_cpsw_run_xdp(struct am65_cpsw_common *common, } page = virt_to_head_page(xdp->data); - am65_cpsw_put_page(rx_chn, page, true, desc_idx); + am65_cpsw_put_page(flow, page, true, desc_idx); out: return ret; @@ -1094,11 +1131,11 @@ static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) } } -static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, - u32 flow_idx, int cpu) +static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, int cpu) { - struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; + struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; u32 buf_dma_len, pkt_len, port_id = 0, csum_info; + struct am65_cpsw_common *common = flow->common; struct am65_cpsw_ndev_priv *ndev_priv; struct am65_cpsw_ndev_stats *stats; struct cppi5_host_desc_t *desc_rx; @@ -1108,6 +1145,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, struct am65_cpsw_port *port; int headroom, desc_idx, ret; struct net_device *ndev; + u32 flow_idx = flow->id; struct sk_buff *skb; struct xdp_buff xdp; void *page_addr; @@ -1161,12 +1199,12 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, } if (port->xdp_prog) { - xdp_init_buff(&xdp, AM65_CPSW_MAX_PACKET_SIZE, &port->xdp_rxq); + xdp_init_buff(&xdp, AM65_CPSW_MAX_PACKET_SIZE, &port->xdp_rxq[flow->id]); xdp_prepare_buff(&xdp, page_addr, skb_headroom(skb), pkt_len, false); - ret = am65_cpsw_run_xdp(common, port, &xdp, desc_idx, + ret = am65_cpsw_run_xdp(flow, port, &xdp, desc_idx, cpu, &pkt_len); if (ret != AM65_CPSW_XDP_PASS) return ret; @@ -1184,7 +1222,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, skb_mark_for_recycle(skb); skb->protocol = eth_type_trans(skb, ndev); am65_cpsw_nuss_rx_csum(skb, csum_info); - napi_gro_receive(&common->napi_rx, skb); + napi_gro_receive(&flow->napi_rx, skb); stats = this_cpu_ptr(ndev_priv->stats); @@ -1193,21 +1231,21 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, stats->rx_bytes += pkt_len; u64_stats_update_end(&stats->syncp); - new_page = page_pool_dev_alloc_pages(rx_chn->page_pool); + new_page = page_pool_dev_alloc_pages(flow->page_pool); if (unlikely(!new_page)) return -ENOMEM; - rx_chn->pages[desc_idx] = new_page; + flow->pages[desc_idx] = new_page; if (netif_dormant(ndev)) { - am65_cpsw_put_page(rx_chn, new_page, true, desc_idx); + am65_cpsw_put_page(flow, new_page, true, desc_idx); ndev->stats.rx_dropped++; return 0; } requeue: - ret = am65_cpsw_nuss_rx_push(common, new_page); + ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); if (WARN_ON(ret < 0)) { - am65_cpsw_put_page(rx_chn, new_page, true, desc_idx); + am65_cpsw_put_page(flow, new_page, true, desc_idx); ndev->stats.rx_errors++; ndev->stats.rx_dropped++; } @@ -1217,38 +1255,32 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) { - struct am65_cpsw_common *common = - container_of(timer, struct am65_cpsw_common, rx_hrtimer); + struct am65_cpsw_rx_flow *flow = + container_of(timer, struct am65_cpsw_rx_flow, rx_hrtimer); - enable_irq(common->rx_chns.irq); + enable_irq(flow->irq); return HRTIMER_NORESTART; } static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) { - struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); - int flow = AM65_CPSW_MAX_RX_FLOWS; + struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); + struct am65_cpsw_common *common = flow->common; int cpu = smp_processor_id(); bool xdp_redirect = false; int cur_budget, ret; int num_rx = 0; - /* process every flow */ - while (flow--) { - cur_budget = budget - num_rx; - - while (cur_budget--) { - ret = am65_cpsw_nuss_rx_packets(common, flow, cpu); - if (ret) { - if (ret == AM65_CPSW_XDP_REDIRECT) - xdp_redirect = true; - break; - } - num_rx++; - } - - if (num_rx >= budget) + /* process only this flow */ + cur_budget = budget; + while (cur_budget--) { + ret = am65_cpsw_nuss_rx_packets(flow, cpu); + if (ret) { + if (ret == AM65_CPSW_XDP_REDIRECT) + xdp_redirect = true; break; + } + num_rx++; } if (xdp_redirect) @@ -1257,14 +1289,14 @@ static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { - if (common->rx_irq_disabled) { - common->rx_irq_disabled = false; - if (unlikely(common->rx_pace_timeout)) { - hrtimer_start(&common->rx_hrtimer, - ns_to_ktime(common->rx_pace_timeout), + if (flow->irq_disabled) { + flow->irq_disabled = false; + if (unlikely(flow->rx_pace_timeout)) { + hrtimer_start(&flow->rx_hrtimer, + ns_to_ktime(flow->rx_pace_timeout), HRTIMER_MODE_REL_PINNED); } else { - enable_irq(common->rx_chns.irq); + enable_irq(flow->irq); } } } @@ -1512,11 +1544,11 @@ static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) { - struct am65_cpsw_common *common = dev_id; + struct am65_cpsw_rx_flow *flow = dev_id; - common->rx_irq_disabled = true; + flow->irq_disabled = true; disable_irq_nosync(irq); - napi_schedule(&common->napi_rx); + napi_schedule(&flow->napi_rx); return IRQ_HANDLED; } @@ -2315,19 +2347,23 @@ static void am65_cpsw_nuss_free_rx_chns(void *data) k3_udma_glue_release_rx_chn(rx_chn->rx_chn); } -static void am65_cpsw_nuss_remove_rx_chns(void *data) +void am65_cpsw_nuss_remove_rx_chns(void *data) { struct am65_cpsw_common *common = data; struct device *dev = common->dev; struct am65_cpsw_rx_chn *rx_chn; + struct am65_cpsw_rx_flow *flows; + int i; rx_chn = &common->rx_chns; + flows = rx_chn->flows; devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); - if (!(rx_chn->irq < 0)) - devm_free_irq(dev, rx_chn->irq, common); - - netif_napi_del(&common->napi_rx); + for (i = 0; i < common->rx_ch_num_flows; i++) { + if (!(flows[i].irq < 0)) + devm_free_irq(dev, flows[i].irq, &flows[i]); + netif_napi_del(&flows[i].napi_rx); + } am65_cpsw_nuss_free_rx_chns(common); @@ -2340,6 +2376,7 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; struct device *dev = common->dev; + struct am65_cpsw_rx_flow *flow; u32 hdesc_size, hdesc_size_out; u32 fdqring_id; int i, ret = 0; @@ -2348,12 +2385,21 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) AM65_CPSW_NAV_SW_DATA_SIZE); rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; - rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; + rx_cfg.flow_id_num = common->rx_ch_num_flows; rx_cfg.flow_id_base = common->rx_flow_id_base; /* init all flows */ rx_chn->dev = dev; - rx_chn->descs_num = max_desc_num; + rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; + + for (i = 0; i < common->rx_ch_num_flows; i++) { + flow = &rx_chn->flows[i]; + flow->page_pool = NULL; + flow->pages = devm_kcalloc(dev, AM65_CPSW_MAX_RX_DESC, + sizeof(*flow->pages), GFP_KERNEL); + if (!flow->pages) + return -ENOMEM; + } rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); if (IS_ERR(rx_chn->rx_chn)) { @@ -2376,13 +2422,6 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) rx_chn->dsize_log2 = __fls(hdesc_size_out); WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); - rx_chn->page_pool = NULL; - - rx_chn->pages = devm_kcalloc(dev, rx_chn->descs_num, - sizeof(*rx_chn->pages), GFP_KERNEL); - if (!rx_chn->pages) - return -ENOMEM; - common->rx_flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); @@ -2406,6 +2445,10 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, }; + flow = &rx_chn->flows[i]; + flow->id = i; + flow->common = common; + rx_flow_cfg.ring_rxfdq0_id = fdqring_id; rx_flow_cfg.rx_cfg.size = max_desc_num; rx_flow_cfg.rxfdq_cfg.size = max_desc_num; @@ -2422,28 +2465,31 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, i); - rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); - - if (rx_chn->irq < 0) { + flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); + if (flow->irq <= 0) { dev_err(dev, "Failed to get rx dma irq %d\n", - rx_chn->irq); - ret = rx_chn->irq; + flow->irq); + ret = flow->irq; goto err; } - } - netif_napi_add(common->dma_ndev, &common->napi_rx, - am65_cpsw_nuss_rx_poll); - hrtimer_init(&common->rx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); - common->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; + snprintf(flow->name, + sizeof(flow->name), "%s-rx%d", + dev_name(dev), i); + netif_napi_add(common->dma_ndev, &flow->napi_rx, + am65_cpsw_nuss_rx_poll); + hrtimer_init(&flow->rx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); + flow->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; - ret = devm_request_irq(dev, rx_chn->irq, - am65_cpsw_nuss_rx_irq, - IRQF_TRIGGER_HIGH, dev_name(dev), common); - if (ret) { - dev_err(dev, "failure requesting rx irq %u, %d\n", - rx_chn->irq, ret); - goto err; + ret = devm_request_irq(dev, flow->irq, + am65_cpsw_nuss_rx_irq, + IRQF_TRIGGER_HIGH, + flow->name, flow); + if (ret) { + dev_err(dev, "failure requesting rx %d irq %u, %d\n", + i, flow->irq, ret); + goto err; + } } err: @@ -3287,8 +3333,8 @@ static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); } - for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) - k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, rx_chan, + for (i = 0; i < common->rx_ch_num_flows; i++) + k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, &rx_chan->flows[i], am65_cpsw_nuss_rx_cleanup, !!i); k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); @@ -3330,12 +3376,17 @@ static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) return ret; } -int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) +int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, int num_tx, int num_rx) { int ret; common->tx_ch_num = num_tx; + common->rx_ch_num_flows = num_rx; ret = am65_cpsw_nuss_init_tx_chns(common); + if (ret) + return ret; + + ret = am65_cpsw_nuss_init_rx_chns(common); return ret; } @@ -3465,6 +3516,7 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) common->rx_flow_id_base = -1; init_completion(&common->tdown_complete); common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; + common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; common->pf_p0_rx_ptype_rrobin = false; common->default_vlan = 1; @@ -3656,8 +3708,10 @@ static int am65_cpsw_nuss_resume(struct device *dev) return ret; /* If RX IRQ was disabled before suspend, keep it disabled */ - if (common->rx_irq_disabled) - disable_irq(common->rx_chns.irq); + for (i = 0; i < common->rx_ch_num_flows; i++) { + if (common->rx_chns.flows[i].irq_disabled) + disable_irq(common->rx_chns.flows[i].irq); + } am65_cpts_resume(common->cpts); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index e2ce2be320bd..a644bd09a071 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -22,8 +22,7 @@ struct am65_cpts; #define HOST_PORT_NUM 0 #define AM65_CPSW_MAX_TX_QUEUES 8 -#define AM65_CPSW_MAX_RX_QUEUES 1 -#define AM65_CPSW_MAX_RX_FLOWS 1 +#define AM65_CPSW_MAX_RX_QUEUES 8 #define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014 @@ -58,7 +57,7 @@ struct am65_cpsw_port { struct am65_cpsw_qos qos; struct devlink_port devlink_port; struct bpf_prog *xdp_prog; - struct xdp_rxq_info xdp_rxq; + struct xdp_rxq_info xdp_rxq[AM65_CPSW_MAX_RX_QUEUES]; /* Only for suspend resume context */ u32 vid_context; }; @@ -94,16 +93,27 @@ struct am65_cpsw_tx_chn { u32 rate_mbps; }; +struct am65_cpsw_rx_flow { + u32 id; + struct napi_struct napi_rx; + struct am65_cpsw_common *common; + int irq; + bool irq_disabled; + struct hrtimer rx_hrtimer; + unsigned long rx_pace_timeout; + struct page_pool *page_pool; + struct page **pages; + char name[32]; +}; + struct am65_cpsw_rx_chn { struct device *dev; struct device *dma_dev; struct k3_cppi_desc_pool *desc_pool; struct k3_udma_glue_rx_channel *rx_chn; - struct page_pool *page_pool; - struct page **pages; u32 descs_num; unsigned char dsize_log2; - int irq; + struct am65_cpsw_rx_flow flows[AM65_CPSW_MAX_RX_QUEUES]; }; #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0) @@ -149,12 +159,8 @@ struct am65_cpsw_common { struct completion tdown_complete; atomic_t tdown_cnt; + int rx_ch_num_flows; struct am65_cpsw_rx_chn rx_chns; - struct napi_struct napi_rx; - - bool rx_irq_disabled; - struct hrtimer rx_hrtimer; - unsigned long rx_pace_timeout; u32 nuss_ver; u32 cpsw_ver; @@ -203,8 +209,8 @@ struct am65_cpsw_ndev_priv { #define am65_common_get_host(common) (&(common)->host) #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1]) -#define am65_cpsw_napi_to_common(pnapi) \ - container_of(pnapi, struct am65_cpsw_common, napi_rx) +#define am65_cpsw_napi_to_rx_flow(pnapi) \ + container_of(pnapi, struct am65_cpsw_rx_flow, napi_rx) #define am65_cpsw_napi_to_tx_chn(pnapi) \ container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx) @@ -216,7 +222,8 @@ extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave; void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common); void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common); -int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx); +void am65_cpsw_nuss_remove_rx_chns(void *data); +int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, int num_tx, int num_rx); bool am65_cpsw_port_dev_check(const struct net_device *dev); From patchwork Fri Jun 28 12:01:51 2024 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7430; i=rogerq@kernel.org; h=from:subject:message-id; bh=CbIB5qO2jhGkVedTF0ZhVMpobXs6Dehu/8Fb+mwzfxw=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4NAkury5OcdAFq/qu4zron7Mtmud2j35J9 CrKlbY+UwaJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw k034D/4/Ck5SWOgwJ045RfpikUywcsAxK4P6V6NTZElcqYqAz4o3gPIZdXvtX5SHNzkbDKDqrCP PzfCMKxmCe8a6axqkALICK8va9igYevs5Z9V2Mo+PIT3/K1d3nYTBIiA5o5Ei9RWsQ/YA9Prp+Z B1fSsYH08dqiLOmty2BCZY/s0pXNBVw5Z282Q1hfJletg8e4HwQeGK9wl7xK1IWcGpOpGqHsdWB genBSuXs7p0lu4FPJgnb/1QZmPbjmbMobGFyiC1HZlT2669CiT/F85VvkutHXGRPD9OzbbN4MIm PSmheoQO9i1GF03/sSmxc+pi++TEZSRDVXRLY/yDMvW4YmqubCV4u+GuS99wIBhnaRixqVheXAx Xq5IkHd5b27l1fD/yLggJKtPx5ciJykLMaqPZ/1Mb3yH/L/8cX6TJQNImuVWYXZhK8w5LA30Ek5 K8DXQmgVnzAvymR8I46kxrVz6Uso6Ok3FHYbKBx5bExysktKHRDT+vjocLjpjjYOnz500lNgwtr Rnp4yjH+MRRgl03SGhsyngmiOxWR01d9QDjIvbPDf13WRcedH9AExGS6wGgkIacikvNZFV8AnST NRJSUMiy0Q+t7STgwy8nvr0uvBXTYxPlOPmmwP+vOjJDEGZSTprDJTrtNAcaD5pErkNM3nOZDEO LjSZcqqAKPXNR0w== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Map the entire ALE registerspace using regmap. Add regfields for Major and Minor Version fields. Signed-off-by: Roger Quadros Reviewed-by: Simon Horman --- drivers/net/ethernet/ti/cpsw_ale.c | 83 +++++++++++++++++++++++++++++--------- drivers/net/ethernet/ti/cpsw_ale.h | 17 ++++++-- 2 files changed, 78 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 64bf22cd860c..5afe9fdd6402 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -76,7 +77,7 @@ enum { * @dev_id: ALE version/SoC id * @features: features supported by ALE * @tbl_entries: number of ALE entries - * @major_ver_mask: mask of ALE Major Version Value in ALE_IDVER reg. + * @reg_fields: pointer to array of register field configuration * @nu_switch_ale: NU Switch ALE * @vlan_entry_tbl: ALE vlan entry fields description tbl */ @@ -84,7 +85,7 @@ struct cpsw_ale_dev_id { const char *dev_id; u32 features; u32 tbl_entries; - u32 major_ver_mask; + const struct reg_field *reg_fields; bool nu_switch_ale; const struct ale_entry_fld *vlan_entry_tbl; }; @@ -1292,25 +1293,37 @@ void cpsw_ale_stop(struct cpsw_ale *ale) cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } +static const struct reg_field ale_fields_cpsw[] = { + /* CPSW_ALE_IDVER_REG */ + [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), + [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15), +}; + +static const struct reg_field ale_fields_cpsw_nu[] = { + /* CPSW_ALE_IDVER_REG */ + [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), + [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10), +}; + static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { { /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */ .dev_id = "cpsw", .tbl_entries = 1024, - .major_ver_mask = 0xff, + .reg_fields = ale_fields_cpsw, .vlan_entry_tbl = vlan_entry_cpsw, }, { /* 66ak2h_xgbe */ .dev_id = "66ak2h-xgbe", .tbl_entries = 2048, - .major_ver_mask = 0xff, + .reg_fields = ale_fields_cpsw, .vlan_entry_tbl = vlan_entry_cpsw, }, { .dev_id = "66ak2el", .features = CPSW_ALE_F_STATUS_REG, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, @@ -1318,7 +1331,7 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .dev_id = "66ak2g", .features = CPSW_ALE_F_STATUS_REG, .tbl_entries = 64, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, @@ -1326,20 +1339,20 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .dev_id = "am65x-cpsw2g", .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, .tbl_entries = 64, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, { .dev_id = "j721e-cpswxg", .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .vlan_entry_tbl = vlan_entry_k3_cpswxg, }, { .dev_id = "am64-cpswxg", .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .vlan_entry_tbl = vlan_entry_k3_cpswxg, .tbl_entries = 512, }, @@ -1361,41 +1374,75 @@ cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id, return NULL; } +static const struct regmap_config ale_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .name = "cpsw-ale", +}; + +static int cpsw_ale_regfield_init(struct cpsw_ale *ale) +{ + struct regmap *regmap = ale->regmap; + struct device *dev = ale->params.dev; + const struct reg_field *reg_fields = ale->params.reg_fields; + int i; + + for (i = 0; i < ALE_FIELDS_MAX; i++) { + ale->fields[i] = devm_regmap_field_alloc(dev, regmap, + reg_fields[i]); + if (IS_ERR(ale->fields[i])) { + dev_err(dev, "Unable to allocate regmap field %d\n", i); + return PTR_ERR(ale->fields[i]); + } + } + + return 0; +} + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) { const struct cpsw_ale_dev_id *ale_dev_id; struct cpsw_ale *ale; - u32 rev, ale_entries; + u32 ale_entries, rev_major, rev_minor; + int ret; ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); if (!ale_dev_id) return ERR_PTR(-EINVAL); params->ale_entries = ale_dev_id->tbl_entries; - params->major_ver_mask = ale_dev_id->major_ver_mask; params->nu_switch_ale = ale_dev_id->nu_switch_ale; + params->reg_fields = ale_dev_id->reg_fields; ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); if (!ale) return ERR_PTR(-ENOMEM); + ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs, &ale_regmap_cfg); + if (IS_ERR(ale->regmap)) { + dev_err(params->dev, "Couldn't create CPSW ALE regmap\n"); + return ERR_PTR(-ENOMEM); + } + + ale->params = *params; + ret = cpsw_ale_regfield_init(ale); + if (ret) + return ERR_PTR(ret); ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID, GFP_KERNEL); if (!ale->p0_untag_vid_mask) return ERR_PTR(-ENOMEM); - ale->params = *params; ale->ageout = ale->params.ale_ageout * HZ; ale->features = ale_dev_id->features; ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl; - rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); - ale->version = - (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) | - ALE_VERSION_MINOR(rev); + regmap_field_read(ale->fields[MINOR_VER], &rev_minor); + regmap_field_read(ale->fields[MAJOR_VER], &rev_major); + ale->version = rev_major << 8 | rev_minor; dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", - ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask), - ALE_VERSION_MINOR(rev)); + rev_major, rev_minor); if (ale->features & CPSW_ALE_F_STATUS_REG && !ale->params.ale_entries) { diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 6779ee111d57..58d377dd7496 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -8,6 +8,8 @@ #ifndef __TI_CPSW_ALE_H__ #define __TI_CPSW_ALE_H__ +struct reg_fields; + struct cpsw_ale_params { struct device *dev; void __iomem *ale_regs; @@ -20,19 +22,26 @@ struct cpsw_ale_params { * to identify this hardware. */ bool nu_switch_ale; - /* mask bit used in NU Switch ALE is 3 bits instead of 8 bits. So - * pass it from caller. - */ - u32 major_ver_mask; + const struct reg_field *reg_fields; const char *dev_id; unsigned long bus_freq; }; struct ale_entry_fld; +struct regmap; + +enum ale_fields { + MINOR_VER, + MAJOR_VER, + /* terminator */ + ALE_FIELDS_MAX, +}; struct cpsw_ale { struct cpsw_ale_params params; struct timer_list timer; + struct regmap *regmap; + struct regmap_field *fields[ALE_FIELDS_MAX]; unsigned long ageout; u32 version; u32 features; From patchwork Fri Jun 28 12:01:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 13716020 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9AD0158D7E; Fri, 28 Jun 2024 12:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576135; cv=none; b=pOcJKWE1/NcwRrFBCcR22Ii3VMSkwDRRFatdsteR/X2FkA4kWXAvcLutgvyT7N/ImyeNG7JV24YZUQ7nb2ZkfeO9ImGiVlJSdyB+vnVaz6dG7Y8N0TpaiuC8J0v75do7XGj9TAToaldZm32cw/ijf7at7scVGbqfGTQqTQULr80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576135; c=relaxed/simple; bh=08Dx61MyaxKGlSkozABy5WMPBJ2CLpDC+4zlJix+0JA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=P/uJ9fxi81bZ2xUNEC4dLa/davonxA1JTPHwNVcu4eyQSjC4wv2ODPdDZOPR6GTLOKd86mW9lpweDohcKRBBxLzYE+nmH/BLM0zWgZDAvr+wHNtQrmiiuCds1JjEct7xu2cvpYqANHxBDAW7+DOSl3J/5KFitQTP40nJA5lX4N8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RzYQq506; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RzYQq506" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7CD57C116B1; Fri, 28 Jun 2024 12:02:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719576135; bh=08Dx61MyaxKGlSkozABy5WMPBJ2CLpDC+4zlJix+0JA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RzYQq506UcW/kdIQvGp2LOORzyS3ZKUdNn+XuW7QuqfMg1KDVqMhx38pCGBlTGpSb KD6o0IoCWXb31KVykr5MpDoqJU+0IiFTb866z5iVV+GvQwg9GD3DD39N4brldlULGJ HzuN6ccs1A7pw7Eno7MrxBUy5QwknTN4JblVaA834mb3V9e2ByIuTprFdm2/AdOi1s gu6nLlj/ORx2PVHH7jqW8pxj/gzssrsq9bsxXd3YIEvVJJHhAFZuQPs4ppw/K3LR5x vHPkgRfqx0nQGAztAlpoHJIQHbUM4UjTUHtydbDdSD2GC0kGdgi8LcrgVFVPdxuSY1 hWABbRAfvvNug== From: Roger Quadros Date: Fri, 28 Jun 2024 15:01:52 +0300 Subject: [PATCH net-next v2 3/7] net: ethernet: ti: cpsw_ale: use regfields for number of Entries and Policers Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240628-am65-cpsw-multi-rx-v2-3-c399cb77db56@kernel.org> References: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> In-Reply-To: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3704; i=rogerq@kernel.org; h=from:subject:message-id; bh=08Dx61MyaxKGlSkozABy5WMPBJ2CLpDC+4zlJix+0JA=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4ikMcAIbn90+7REkmcxoDIU4AtE/QpZcqw v8O/wSgAZWJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw k6UDD/9RIseQJBe3R4kKzM0TS0gP2bKiu9e/EMUpLTEQcKm7QBxYhKrTvrydcV4+duBlYWBuKnx TjVOz3XlkS0aQtIHdb2e5gFJDdJh1ERlpLUIHTEjm5hi+wjJFoJC8oS2hrD4BWxqmXKISovAFSJ yZZPIuKlyDBuciB0BwQQnT4P1W02LrJT/AHVOCklclyzBsZbplX71FMppmbh8fMYPysTh8+BMWX C45EoLZDlxmtZv/bb7t/2VVWNES62qfd6TILNknyVQzg5ZaDUl4tEhWgjLDp3Mvuqiv9//U2Yg7 Z1UAuzkVHco5hxgw3xXbYST7ch8KTWQLgnOWgW/m37lp78CJTC3uf7h501JsQuwW1zKU61j8PPG O83c3kTtoufIeGPd2+iNZbkZgcB8sB3aR8e/VmzWBTWwKXqmwrO6lmgodvLohbuyi2QkyP3/yrW 76A96LTU9Q2PFIFWdOIRU+AGUzM8t4k0BG2ZN3V/NiMHPjXFWv7TFryN7gVis0PQQXkET1mvyDT nw6Z4X2QY9ZHZawwhskd7lmQa2zDMgs8I+0QV36BtsAEYcDwWnyL2Lg0aouVDKPmm8rOvBigMSG /NuJAC4lxY4+UmcIm3ZBOGpWvRa8rGo5CZI6h1xQD4I0X0glR7IKY3S854QcujATsIYSJITN5PV zP/3v1jmoMD0xDQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Use regfields for number of ALE Entries and Policers. The variants that support Policers/Classifiers have the number of policers encoded in the ALE_STATUS register. Use that and show the number of Policers in the ALE info message. Signed-off-by: Roger Quadros Reviewed-by: Simon Horman --- drivers/net/ethernet/ti/cpsw_ale.c | 25 +++++++++++++++++++------ drivers/net/ethernet/ti/cpsw_ale.h | 3 +++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 5afe9fdd6402..ca66c89c1f12 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -103,7 +103,7 @@ struct cpsw_ale_dev_id { #define ALE_UCAST_TOUCHED 3 #define ALE_TABLE_SIZE_MULTIPLIER 1024 -#define ALE_STATUS_SIZE_MASK 0x1f +#define ALE_POLICER_SIZE_MULTIPLIER 8 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) { @@ -1303,6 +1303,9 @@ static const struct reg_field ale_fields_cpsw_nu[] = { /* CPSW_ALE_IDVER_REG */ [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10), + /* CPSW_ALE_STATUS_REG */ + [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7), + [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15), }; static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { @@ -1404,7 +1407,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) { const struct cpsw_ale_dev_id *ale_dev_id; struct cpsw_ale *ale; - u32 ale_entries, rev_major, rev_minor; + u32 ale_entries, rev_major, rev_minor, policers; int ret; ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); @@ -1446,9 +1449,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) if (ale->features & CPSW_ALE_F_STATUS_REG && !ale->params.ale_entries) { - ale_entries = - readl_relaxed(ale->params.ale_regs + ALE_STATUS) & - ALE_STATUS_SIZE_MASK; + regmap_field_read(ale->fields[ALE_ENTRIES], &ale_entries); /* ALE available on newer NetCP switches has introduced * a register, ALE_STATUS, to indicate the size of ALE * table which shows the size as a multiple of 1024 entries. @@ -1462,8 +1463,20 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; ale->params.ale_entries = ale_entries; } + + if (ale->features & CPSW_ALE_F_STATUS_REG && + !ale->params.num_policers) { + regmap_field_read(ale->fields[ALE_POLICERS], &policers); + if (!policers) + return ERR_PTR(-EINVAL); + + policers *= ALE_POLICER_SIZE_MULTIPLIER; + ale->params.num_policers = policers; + } + dev_info(ale->params.dev, - "ALE Table size %ld\n", ale->params.ale_entries); + "ALE Table size %ld, Policers %ld\n", ale->params.ale_entries, + ale->params.num_policers); /* set default bits for existing h/w */ ale->port_mask_bits = ale->params.ale_ports; diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 58d377dd7496..e12bb2caf016 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -15,6 +15,7 @@ struct cpsw_ale_params { void __iomem *ale_regs; unsigned long ale_ageout; /* in secs */ unsigned long ale_entries; + unsigned long num_policers; unsigned long ale_ports; /* NU Switch has specific handling as number of bits in ALE entries * are different than other versions of ALE. Also there are specific @@ -33,6 +34,8 @@ struct regmap; enum ale_fields { MINOR_VER, MAJOR_VER, + ALE_ENTRIES, + ALE_POLICERS, /* terminator */ ALE_FIELDS_MAX, }; From patchwork Fri Jun 28 12:01:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 13716021 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDDF615956C; Fri, 28 Jun 2024 12:02:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576139; cv=none; b=SX0/mTE0qmpJmClUqysos0VmfRN8OlvUd7754WSI+3oCOzreYFa+n4Pplw3kdxeTgzA6xHRR40LK4uudgFEKFSQIyMn9L8o1UspGOGvABSmGGNGrtO8w+8fwIeNThVE4Mq7CCMrJ+brxbpgTjjyaT7Er14jxQu/PH1gjoD0hpOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576139; c=relaxed/simple; bh=3k9ZkwgGpMPZn2tsQoz44Is7MxHK8Dik11rJoEG98i8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G5d3TMYJ0Nt5e33mbDSw2/xtfEpPvSTcM/+r8hEsgWS8BBHhh6gvSSsU3iurYiJx9hJN3zEU0yfV9caflHU1firEqhnqL7mXtgMRTHkA+JTWVacbFRL+QiLc9uAYVQigdGwvjTZ64ABCsO9fBDH7bpqJblP3PLm4v8ojUt2V4VE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oSaA8PPu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oSaA8PPu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32CA7C4AF0A; Fri, 28 Jun 2024 12:02:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719576139; bh=3k9ZkwgGpMPZn2tsQoz44Is7MxHK8Dik11rJoEG98i8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oSaA8PPuU8Boh8baTcIZ8MpdGH8oP+d2K2R2rTirZOXjez8qfAtCHkEN2xaxLkZE3 rkskWQIOfKpLvJbW7qI7Gy435AaXELUciQJ8VIV+L4Qqqm9SJVGnoFODDQ2FUuyNMu HCplFiQj3BuvezwaD02c7OlwPoXVqPk5Gx7+EL0NRsh+B0jduQbuAtIya18hsLqVhK kqKVcc3oSU2wlbRLuCVfX+MnbwcbdwDfuMJ8/Civc5huK3n+bDEjpVMzejKbR79yDj qprfxe704/2aDWZcztYYDButdfOCJ5RfWq7d01eAHgcqO8uXDxlTepNYOOJEinIjAX ry2I20WjWAb7Q== From: Roger Quadros Date: Fri, 28 Jun 2024 15:01:53 +0300 Subject: [PATCH net-next v2 4/7] net: ethernet: ti: cpsw_ale: add Policer and Thread control register fields Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240628-am65-cpsw-multi-rx-v2-4-c399cb77db56@kernel.org> References: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> In-Reply-To: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5932; i=rogerq@kernel.org; h=from:subject:message-id; bh=3k9ZkwgGpMPZn2tsQoz44Is7MxHK8Dik11rJoEG98i8=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4kQ1AO5a5vgA7hzp1QCN2xuUctz8iLY8RX 6PyNuSH2UWJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw kyuuD/9AnEZuAQ1uue9Fx76eZAAuKt6E02b5VBtQqm9/SBp9cZCFU3bv8QG6FnkqRW4Bb4NIUGB P5A+TFfjUzMtd7fUtgZA2C/mEj3fW1/9DTZtLh5UQkjxzjaqs2AXLgqU9DRUCVfOjqqSJs5/ouV zKhJTGG95EUYAHOjHo8aXvTZ6Z4EZFi8t4C4aek9h5OzLafsl+NFyO2tklmYee9nV4qZt9DRikz YiMP1OPDEGAoI3pXz8a4gjyPhzJrDebT0IHK8lHM1m2L2MNBudGCHr5/aeAzl41NKALcBwscY36 mqnz5OU2oSp881BeLJ6GT0BOr/pQwk7ZEZUPKNzxGDd4Ei3/yFVbJ4i3vurK0fHss3lDK/0JHGs jJNHJGu6cusT3e717InE8OELjaIGCdE6K3/p3gZpBbCmdMVjcr/qiSiQC2cewmO29NOpRb80kSC b9Q9pKxspbLL6RQ2B05iHd1n88qB2B8bGTQmXDJkqNAPaRu1Pc6mCphnJQM9OBWWMWe9xzMFlWO 0TL6Dx4He6tBPo1hEXFPplnErd02rRSzT0QTGsTggRNUZfZ1l/XX0x7vasE9zUzYXOruuV+Dt24 QOGTsZ2FLnTMg5IsAYe+j2jA0O5Jt1WGSxC3ziNBdAyimbMhzIrGjB1zBnkMzD8ljBmi1d6xaLY jDl+wrucbWgdsGA== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Adds regfileds for Policer registers and Thread mapping/control registers. Signed-off-by: Roger Quadros Reviewed-by: Simon Horman --- drivers/net/ethernet/ti/cpsw_ale.c | 86 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 41 ++++++++++++++++++ 2 files changed, 127 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index ca66c89c1f12..7bd0dc20f894 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -46,6 +46,24 @@ #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) +#define ALE_POLICER_PORT_OUI 0x100 +#define ALE_POLICER_DA_SA 0x104 +#define ALE_POLICER_VLAN 0x108 +#define ALE_POLICER_ETHERTYPE_IPSA 0x10c +#define ALE_POLICER_IPDA 0x110 +#define ALE_POLICER_PIR 0x118 +#define ALE_POLICER_CIR 0x11c +#define ALE_POLICER_TBL_CTL 0x120 +#define ALE_POLICER_CTL 0x124 +#define ALE_POLICER_TEST_CTL 0x128 +#define ALE_POLICER_HIT_STATUS 0x12c +#define ALE_THREAD_DEF 0x134 +#define ALE_THREAD_CTL 0x138 +#define ALE_THREAD_VAL 0x13c + +#define ALE_POLICER_TBL_WRITE_ENABLE BIT(31) +#define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0) + #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 /* ALE_AGING_TIMER */ @@ -1306,6 +1324,74 @@ static const struct reg_field ale_fields_cpsw_nu[] = { /* CPSW_ALE_STATUS_REG */ [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7), [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15), + /* CPSW_ALE_POLICER_PORT_OUI_REG */ + [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31), + [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30), + [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25), + [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19), + [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18), + [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15), + [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5), + + /* CPSW_ALE_POLICER_DA_SA_REG */ + [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31), + [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21), + [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15), + [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5), + + /* CPSW_ALE_POLICER_VLAN_REG */ + [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31), + [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21), + [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15), + [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5), + + /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */ + [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31), + [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21), + [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15), + [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5), + + /* CPSW_ALE_POLICER_IPDA_REG */ + [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31), + [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21), + + /* CPSW_ALE_POLICER_TBL_CTL_REG */ + /** + * REG_FIELDS not defined for this as fields cannot be correctly + * used independently + */ + + /* CPSW_ALE_POLICER_CTL_REG */ + [POL_EN] = REG_FIELD(ALE_POLICER_CTL, 31, 31), + [POL_RED_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 29, 29), + [POL_YELLOW_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 28, 28), + [POL_YELLOW_THRESH] = REG_FIELD(ALE_POLICER_CTL, 24, 26), + [POL_POL_MATCH_MODE] = REG_FIELD(ALE_POLICER_CTL, 22, 23), + [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21), + [POL_MAC_ONLY_DEF_DIS] = REG_FIELD(ALE_POLICER_CTL, 20, 20), + + /* CPSW_ALE_POLICER_TEST_CTL_REG */ + [POL_TEST_CLR] = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31), + [POL_TEST_CLR_RED] = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30), + [POL_TEST_CLR_YELLOW] = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29), + [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28), + [POL_TEST_ENTRY] = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4), + + /* CPSW_ALE_POLICER_HIT_STATUS_REG */ + [POL_STATUS_HIT] = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31), + [POL_STATUS_HIT_RED] = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30), + [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29), + + /* CPSW_ALE_THREAD_DEF_REG */ + [ALE_DEFAULT_THREAD_EN] = REG_FIELD(ALE_THREAD_DEF, 15, 15), + [ALE_DEFAULT_THREAD_VAL] = REG_FIELD(ALE_THREAD_DEF, 0, 5), + + /* CPSW_ALE_THREAD_CTL_REG */ + [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4), + + /* CPSW_ALE_THREAD_VAL_REG */ + [ALE_THREAD_ENABLE] = REG_FIELD(ALE_THREAD_VAL, 15, 15), + [ALE_THREAD_VALUE] = REG_FIELD(ALE_THREAD_VAL, 0, 5), }; static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index e12bb2caf016..2cb76acc6d16 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -36,6 +36,47 @@ enum ale_fields { MAJOR_VER, ALE_ENTRIES, ALE_POLICERS, + POL_PORT_MEN, + POL_TRUNK_ID, + POL_PORT_NUM, + POL_PRI_MEN, + POL_PRI_VAL, + POL_OUI_MEN, + POL_OUI_INDEX, + POL_DST_MEN, + POL_DST_INDEX, + POL_SRC_MEN, + POL_SRC_INDEX, + POL_OVLAN_MEN, + POL_OVLAN_INDEX, + POL_IVLAN_MEN, + POL_IVLAN_INDEX, + POL_ETHERTYPE_MEN, + POL_ETHERTYPE_INDEX, + POL_IPSRC_MEN, + POL_IPSRC_INDEX, + POL_IPDST_MEN, + POL_IPDST_INDEX, + POL_EN, + POL_RED_DROP_EN, + POL_YELLOW_DROP_EN, + POL_YELLOW_THRESH, + POL_POL_MATCH_MODE, + POL_PRIORITY_THREAD_EN, + POL_MAC_ONLY_DEF_DIS, + POL_TEST_CLR, + POL_TEST_CLR_RED, + POL_TEST_CLR_YELLOW, + POL_TEST_CLR_SELECTED, + POL_TEST_ENTRY, + POL_STATUS_HIT, + POL_STATUS_HIT_RED, + POL_STATUS_HIT_YELLOW, + ALE_DEFAULT_THREAD_EN, + ALE_DEFAULT_THREAD_VAL, + ALE_THREAD_CLASS_INDEX, + ALE_THREAD_ENABLE, + ALE_THREAD_VALUE, /* terminator */ ALE_FIELDS_MAX, }; From patchwork Fri Jun 28 12:01:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 13716022 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A21158869; Fri, 28 Jun 2024 12:02:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576143; cv=none; b=cbSfOux2CSOqImsXfdQCj5Zjm7qPjPb0GqV3DQwN+y/bUQusWG1zdqZB/3ekzahzJEBCKkdqiMrKL5PDXwjHYGB3cFihEovdtAnqPnA52Amm5TpDDPBEz0N6ma7NXqG22qosSm8OHPW2BhTuHBnWf2XnbgawvF8CA+gbmx18tFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576143; c=relaxed/simple; bh=/9Lt+Y2ipJumUvIw6ijMSebRDlayn4PCS0/cbKxgNnw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=npK2vBI1XZeclDtEzOGkypQ6AluaNn1OdGaDQzyPLx03XhwalcpyOWpL/mVwVib7HR9M06z3Q19bVn06IFwW1LkJd8LrnkJrt5senl8rgSE21mT4bMfxxK1WwFW8a0/VkN7QbxgOVa3J/o4stvbjpUXdpKc/JZNVWc5vpJT5Tjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n7di2ye6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n7di2ye6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4C7FC116B1; Fri, 28 Jun 2024 12:02:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719576143; bh=/9Lt+Y2ipJumUvIw6ijMSebRDlayn4PCS0/cbKxgNnw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=n7di2ye65waKaibL2G6UWSWXSiScNTPkwAZEVj4LfpGsyTyR5GLacziHqt1BwuWCG 8wp71b4roGuS0O3HBoIFp4MMy7mbmMObVT2BZr5ZyK+905fy7Y78w5Rz80SFdSA/i4 0XHAfOlN8ghvnjjnX7viEy0npFTE3zUfYNv9ADNHNY0OuoeoAfj5QoKAgzwbao5tTw esCdfyPlTh9E4i47OnUygJBqE5UjlszM2nAk8WRgsRJP8yP6xm9fCrSpj2+H9LpoKx 4aJA/bXgbx8mgchIiJ53ocjUwKd9ikSXxr+BSY4c9kRx7ha9q5/jAjhVluxWyZl4ip TnT+ncAqNuzmg== From: Roger Quadros Date: Fri, 28 Jun 2024 15:01:54 +0300 Subject: [PATCH net-next v2 5/7] net: ethernet: ti: cpsw_ale: add policer/classifier helpers Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240628-am65-cpsw-multi-rx-v2-5-c399cb77db56@kernel.org> References: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> In-Reply-To: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2002; i=rogerq@kernel.org; h=from:subject:message-id; bh=/9Lt+Y2ipJumUvIw6ijMSebRDlayn4PCS0/cbKxgNnw=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4jBg9K0RLrnJcWqwBGROzM3C6hO01BRDyf zMwZYyjAueJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw kzgtEACsS+xeiFTY2VSuipIosA5mDCQKpHFvyPsPrX993Av8hkBAb75IxWZu7KU0O0FtsUhma9l FEnDz7bfXLmezu9fZhsQGL7lQk/Q2FMi16ikLV+KyXUyaGXyJqxZWq4V5qXYHIWYmQjjs651muI CQo6ktqNOs+SPsA8Y7xh5QT/7ZXyc/JXMkQ3UFUj/2Ath/JEtgQRplmcGrn8FRrn4YgGMlPFt9M FHn6yPZ/21QgP/dRe4e6wc8tvXl08wuZdMIr+kRLBGz2VpXbjAdbYmOgwSm68sAPtnsBQUKJcqI 7WOn684jFRkv1g0vRnV7+EMANmnguQY7wVOrmYgrt+mq2BA2FuIcsLJgIlpV/kjZPGM8sViNbVV jX/RR4Cr1D9CWS9NXAe+H2iYLiyHaiv+OBX+mCyTdq11/5hlsGbUKxjThcVSeRbIy04Mv/5JLFo 5F+Y1r45IzEl+Izhv8BldAN65b1MwqjyY6Lw4cBrj5+5Xkv1DWvtxQ/80ITzGZp3DP6pRgych3H g0B6oJvewdx2uV+/w6LVfr0xXTrZ74lwaZsjyASHHM6ts6SCQjdEl+OH8WgphuS/bMx4JHFqgOb neTSBgGDEVmGwIehzNkoFEP/mpuH7GvGCiSeJTXhWZMp0UxyCGRCXztGkOmf4uhK0Cq4PrVakOy X/DzE8Rm6e8fU+g== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 The Policer registers in the ALE register space are just shadow registers and use an index field in the policer table control register to read/write to the actual Polier registers. Add helper functions to Read and Write to Policer registers. Also add a helper function to set the thread value to classifier/policer mapping. Any packet that first matches the classifier will be sent to the thread (flow) that is set in the classifer to thread mapping table. If not set then it goes to the default flow. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7bd0dc20f894..75a17184d34c 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1626,3 +1626,27 @@ u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) { return ale ? ale->params.ale_entries : 0; } + +/* Reads the specified policer index into ALE POLICER registers */ +static void cpsw_ale_policer_read_idx(struct cpsw_ale *ale, u32 idx) +{ + idx &= ALE_POLICER_TBL_INDEX_MASK; + writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); +} + +/* Writes the ALE POLICER registers into the specified policer index */ +static void cpsw_ale_policer_write_idx(struct cpsw_ale *ale, u32 idx) +{ + idx &= ALE_POLICER_TBL_INDEX_MASK; + idx |= ALE_POLICER_TBL_WRITE_ENABLE; + writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); +} + +/* enables/disables the custom thread value for the specified policer index */ +static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, + u32 thread_id, bool enable) +{ + regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx); + regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id); + regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); +} From patchwork Fri Jun 28 12:01:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 13716023 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1E2F158869; Fri, 28 Jun 2024 12:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576146; cv=none; b=lNb5yiKNH02/0xPEyA2rkUEqmgq9QKEOhAvgvTNrZzqmrvpGWS0Af1na+J4+quwCLqikZ1zwDfZlaK07FFQOOSoh01JF0JvJvJLgHiQED91tNJcUTZBnlixPQ3AVkqLeBcWrh+91KyP2Vsx/Ee4YpofcBnqssWAjyfyu7qgq0LM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576146; c=relaxed/simple; bh=9e1IIdoq3zKz4bXr6Ah7y7i87LLSXX4VOZlTwPXFM+4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YrAxTgn9RlEqt/LJHxPX5kVR78p9S+/Cnbn76uljIwdZrcZk+z6frKNKsRwW/Lxje5MwSh4jGFA9ZuI6/hw7AgMKDZE6BFT2L55Sm5qzfn3oPmgjIxTnWwaC3/POjrWVu7WbigDj5GOdH5wGA+etojd8cxtjEhYS+wMGF8O16qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IKyL6JM+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IKyL6JM+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86412C32786; Fri, 28 Jun 2024 12:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719576146; bh=9e1IIdoq3zKz4bXr6Ah7y7i87LLSXX4VOZlTwPXFM+4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IKyL6JM+2J6hMySlzE0atG86WuPdhkBBd2GG89+0fyueDwVcjTrUNnSEdn1Q+Rtb2 wkIjJ/l0jDH+8molaGylP8D/vAztyT/CqZIRNEPwYt8MBuru3euvKsf5Ab3E2AHFMd GvmUeeIfLf6/en+Bf75HmNKDqZYqNNyuB6P5nOb+Aspto8wjGLi8vR/tKucl4Q4dES TcryvgOfFWH23pRMXNVWrIs6W9kBVAyLZ1hNd7CqQ9CrP7d38TLSzmGQKzQaLjYngF mi1FkZikdNfBvx5sYcm3DP8gWfab/ki3YW3Qi3J6+vK44dTM4nWgaqwHcmVZ6+lolf FVWYegks+Lp3A== From: Roger Quadros Date: Fri, 28 Jun 2024 15:01:55 +0300 Subject: [PATCH net-next v2 6/7] net: ethernet: ti: cpsw_ale: add helper to setup classifier defaults Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240628-am65-cpsw-multi-rx-v2-6-c399cb77db56@kernel.org> References: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> In-Reply-To: <20240628-am65-cpsw-multi-rx-v2-0-c399cb77db56@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3566; i=rogerq@kernel.org; h=from:subject:message-id; bh=9e1IIdoq3zKz4bXr6Ah7y7i87LLSXX4VOZlTwPXFM+4=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4wUYJr7lqP7I+5xyKhlnkdOjpvrQ80p8EL PyiJ6lKI0qJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw k3LlD/9Plman1i97ZmmF/2NZNmhJIfRT6nc/Aa4dDdZPE6b6YtalFqGFrbXmYT5YYEDl0sUnlwf wWxD4l71XnkZm0Cn+VL+cuBvV2kBzxZPDRxsppCkXOWF9v/+WuzmTrhjM4GklNzdBsuvCZYbi75 C1HlEOp0cg3upfJ4fB5EmVCGOufwz9YuexxYKM0FN7m4vviBGYnorDEA3o8Tay0XwD5y4br9UAa ytYQin0bsTmXwucVWirLr12NVRXIQ8H1S53824W+c3FzNq0a0lqM5wvYLD+S9iWMhaG2UZCkyRc Livbm9gNo0FGY9EDxzLAcINNK6VnRK9PiG8zzpbfexqY3+cb5lJYY3tQwiLvZ48s11pHbid//t/ 0CgoYOU4rf/0IwQHp9Xsc9jdFaNja2W4vdMNsVFAwWRvDPSfEN3XTW026xsi3cEloEq1eYgvJ33 3ssInuBqw4/rhObS3fI7Y9ML53aEbOCb/9BDAiedLD7ogO8d3OLC+BOJLAwpo4nLI+NHcm9qr5n Ejt1CexYUeDQNLhzJYliSfCdY8qzMBoZl1r/qVMcJQkuzAgCJTYEksoh1owCL2NMHYhBg+J96V/ VmWb22zCOyUI93AmLJmcZiWC0SstMU97EAjzAYRPEWNqKPREVKQaDWtnckL0efz6s/l+pMHGvTj 4lKXObaEsO68I1w== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Default behaviour is to have 8 classifiers to map 8 DSCP/PCP priorities to N receive threads (flows). N depends on number of RX channels enabled for the port. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 57 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 1 + 2 files changed, 58 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 75a17184d34c..51da527388df 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1650,3 +1650,60 @@ static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id); regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); } + +/* Disable all policer entries and thread mappings */ +static void cpsw_ale_policer_reset(struct cpsw_ale *ale) +{ + int i; + + for (i = 0; i < ale->params.num_policers ; i++) { + cpsw_ale_policer_read_idx(ale, i); + regmap_field_write(ale->fields[POL_PORT_MEN], 0); + regmap_field_write(ale->fields[POL_PRI_MEN], 0); + regmap_field_write(ale->fields[POL_OUI_MEN], 0); + regmap_field_write(ale->fields[POL_DST_MEN], 0); + regmap_field_write(ale->fields[POL_SRC_MEN], 0); + regmap_field_write(ale->fields[POL_OVLAN_MEN], 0); + regmap_field_write(ale->fields[POL_IVLAN_MEN], 0); + regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0); + regmap_field_write(ale->fields[POL_IPSRC_MEN], 0); + regmap_field_write(ale->fields[POL_IPDST_MEN], 0); + regmap_field_write(ale->fields[POL_EN], 0); + regmap_field_write(ale->fields[POL_RED_DROP_EN], 0); + regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0); + regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0); + + cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0); + } +} + +/* Default classifer is to map 8 user priorities to N receive channels */ +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) +{ + int pri, idx; + int pri_thread_map[8][9] = { { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 1, 1, 1, 1, }, + { 0, 0, 0, 0, 1, 1, 2, 2, }, + { 1, 0, 0, 1, 2, 2, 3, 3, }, + { 1, 0, 0, 1, 2, 3, 4, 4, }, + { 1, 0, 0, 2, 3, 4, 5, 5, }, + { 1, 0, 0, 2, 3, 4, 5, 6, }, + { 2, 0, 1, 3, 4, 5, 6, 7, } }; + + cpsw_ale_policer_reset(ale); + + /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */ + for (pri = 0; pri < 8; pri++) { + idx = pri; + + /* Classifier 'idx' match on priority 'pri' */ + cpsw_ale_policer_read_idx(ale, idx); + regmap_field_write(ale->fields[POL_PRI_VAL], pri); + regmap_field_write(ale->fields[POL_PRI_MEN], 1); + cpsw_ale_policer_write_idx(ale, idx); + + /* Map Classifier 'idx' to thread provided by the map */ + cpsw_ale_policer_thread_idx_enable(ale, idx, + pri_thread_map[num_rx_ch - 1][pri], 1); + } +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 2cb76acc6d16..1e4e9a3dd234 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -193,5 +193,6 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask); void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); #endif From patchwork Fri Jun 28 12:01:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 13716024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83926158869; Fri, 28 Jun 2024 12:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576150; cv=none; b=WhoEYK+4vEoMpx2Cm2quli6UL21nlglrTz4bIyqtv9VEeS6+X1ObsBeN5CjrFA8G/HCgDvxh6AS3FmpJuI4m6HSZ5bEWu6Z3xPk2VTngWgw0bmRLh1sadlQzpRGJJAPq/MtmIMRC/RhO54rwUHEq3WJ92FFdMPYcyTJbnVKj3lM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli , Julien Panis Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=973; i=rogerq@kernel.org; h=from:subject:message-id; bh=FKcirLR/pWoh2OgNGlCJD8YMQ8eyfijmKpfX7z0DNkk=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmfqY4mV0BG4LD3+QOVeLqgS4vNdoucjP24yHt/ r0sqyzoirOJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZn6mOAAKCRDSWmvTvnYw k+jvEAC5gkLelvUnn2oekW5QJf/B4N4rJcbVFF4MKJ4JTr8e5+Ck/m0OIhdb5QxzVEqvtbfdIUJ VuidoxD+MSvvC3/vOi3+jXLKCDYywovWfl9H8mRNW2M7wFfx+sPkGR+nainGjv7EzlMzr7VnYgp G2ktKg2TXgAtDz1M5EAIMYA97Hc8QyKCUOPt/i1Mvgpqha+CNs1oYVyS7J2MNuGtrNkwmjk/NDV 8uWXZwYEsgKu8Th4dI88HU9aSML9RntP0I6idU1JI0Uqr8AgUedRrLJdPczQfdgMVLeM+kRuqup fVEvNVCWaNy/LynXHogJ+qJYd00ex1v/+q0i1GMBAG9FTQ1K1O2xDd744oYtr9l+/VFjZejxpAh RmDg1wR/D1u80tFs2tUpJRW0iUip4dTDD2QVLAuGq0F8EZ8ZTheRIyDXrg5uyv+OXbIMNipZ/zE fbYNQ/N6mu4QuNkgyucjRq+BIUszuVzT+7YyVGKp9OEWn7kbHsWpxQyPhw6TRQBuVECe9ilSLC6 duiW953aKB8zlHB9cu8NkIlm8DP6uJ9GiJaARLd/4uztRA8uRpMOa28FRS/ioCkvlNn7gElulqP gGgssrAiuwN1pfxBLMzvH70Y4uL2qjcwzFvqdH4TcrozoszasIcofvlOZCupvpGGNEtfmWUAAHi Iydf/6vTqH6pNZQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Now that we support multiple RX queues, enable default priority to flow mapping so that higher priority packets come on higher channels (flows). The Classifier checks for PCP/DSCP priority in the packet and routes them to the appropriate flow. Signed-off-by: Roger Quadros Reviewed-by: Simon Horman --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index f6c664dfc1fa..49925ccd6b31 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2492,6 +2492,9 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) } } + /* setup classifier to route priorities to flows */ + cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); + err: i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); if (i) {