From patchwork Fri Jun 28 12:44:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhaoxiong Lv X-Patchwork-Id: 13716080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7004AC3064D for ; Fri, 28 Jun 2024 12:45:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 757C910EC2A; Fri, 28 Jun 2024 12:45:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="zrn1fT4S"; dkim-atps=neutral Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94E6C10EC2E for ; Fri, 28 Jun 2024 12:45:03 +0000 (UTC) Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-1f9fb3ca81bso3339365ad.3 for ; Fri, 28 Jun 2024 05:45:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20230601.gappssmtp.com; s=20230601; t=1719578703; x=1720183503; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OeseQiv7/DSaLni1dvL6OOnrfuUA5o+HEQL8eICjloc=; b=zrn1fT4SqwHfx7leSQgGKewusrvIL6ME1c0FB+ttjekGzqUTIJy/tc+Y+SaHBAE4OV yKT5MQsnfn5DSXbEa0vHGDFW2gshcPG4Oh7RuXmAFGrrrLAZYreow0OzU6WD7JrpIvyh qTv1IdffkHL8LhCdV9ti8Ikx/OBidSnGhPMKN/apxofjIK38JtQVVKGI3V+uIoJUfG4w wp42SQe1Kvng5QM5HeyMx57p2xsfRADGx1jOzEd6/khLNNj6jeo9C04rXRBNrdvfNDGM 1p4WBVA8Del497Al1Ix+iynuu4iWlfKdS9FkPCBmnF1j4wXFC5WSK4p970ovRodF4ufr /TRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719578703; x=1720183503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OeseQiv7/DSaLni1dvL6OOnrfuUA5o+HEQL8eICjloc=; b=XUA8/dVQ9TubxcHyZWLz8ccKM+bL5Pi5DzQSGO9uhHRN6LJpfWLDTGZ0nw4yxovtNI VHknrSuanLuxJXBs249Byna4kCdn/T6oUC1tPnN+OqIQ6WvRZG+jE2v0WYq2WGZS5Pqo dvAfd54VwSCUS30uHnzJ56F5XhrklsNiz8gpFPOhi/UZXVH0npMoBfI742sbHCtDRea/ MXhi/3t33wUxWc62rocZ3nQoxhuzuwnVJ4Nd1oQGc7fzaVT6l0Y0eOATc14PQMlhjnvY kHvnDbU80hOOviVQDvE5HTl0j8uBIiZ7rz+VSpZM5MXRnD+zNeOIg0DDZsubL3ydTaWD r5MA== X-Gm-Message-State: AOJu0Yw7/tIp1Oq6OMg320x0ykfCzlp8VHx1/U43RxbgwIDBwOiQbiQZ 1r9D/eFK+Za+mrg49Fm9sGZqrm02WCQhM6+01LG3odc95gRjFQ9rEuvWUnhyOjM= X-Google-Smtp-Source: AGHT+IGWadE2l1MOGIvcH+qhTXfxLERu8D+lorl26DB268SY32VCtG8S/9RsP0BCd2bpECNPNyPGVw== X-Received: by 2002:a17:902:dac6:b0:1f9:d279:a870 with SMTP id d9443c01a7336-1fa23fb2949mr156225565ad.25.1719578702961; Fri, 28 Jun 2024 05:45:02 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac15695b4sm14346255ad.225.2024.06.28.05.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 05:45:02 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v6 1/5] drm/panel: jd9365da: Modify the method of sending commands Date: Fri, 28 Jun 2024 20:44:40 +0800 Message-Id: <20240628124444.28152-2-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, the init_code of the jd9365da driver is placed in the enable() function and sent, but this seems to take a long time. It takes 17ms to send each instruction (an init code consists of about 200 instructions), so it takes about 3.5s to send the init_code. So we moved the sending of the inti_code to the prepare() function, and each instruction seemed to take only 25μs. We checked the DSI host and found that the difference in command sending time is caused by the different modes of the DSI host in prepare() and enable() functions. Our DSI Host only supports sending cmd in LP mode, The prepare() function can directly send init_code (LP->cmd) in LP mode, but the enable() function is in HS mode and needs to switch to LP mode before sending init code (HS->LP->cmd->HS). Therefore, it takes longer to send the command. Signed-off-by: Zhaoxiong Lv Reviewed-by: Douglas Anderson --- Changes between V6 and V5: - 1. No changes. V5:https://lore.kernel.org/all/20240624141926.5250-2-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V5 and V4: - 1. No changes. V4:https://lore.kernel.org/all/20240620080509.18504-2-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V4 and V3: - 1. Only move mipi_dsi_dcs_write_buffer from enable() function to prepare() function, - and no longer use mipi_dsi_dcs_write_seq_multi. V3:https://lore.kernel.org/all/20240614145510.22965-2-lvzhaoxiong@huaqin.corp-partner.google.com/ --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 4879835fe101..a9c483a7b3fa 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -52,21 +52,9 @@ static int jadard_enable(struct drm_panel *panel) { struct device *dev = panel->dev; struct jadard *jadard = panel_to_jadard(panel); - const struct jadard_panel_desc *desc = jadard->desc; struct mipi_dsi_device *dsi = jadard->dsi; - unsigned int i; int err; - msleep(10); - - for (i = 0; i < desc->num_init_cmds; i++) { - const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; - - err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); - if (err < 0) - return err; - } - msleep(120); err = mipi_dsi_dcs_exit_sleep_mode(dsi); @@ -100,6 +88,8 @@ static int jadard_disable(struct drm_panel *panel) static int jadard_prepare(struct drm_panel *panel) { struct jadard *jadard = panel_to_jadard(panel); + const struct jadard_panel_desc *desc = jadard->desc; + unsigned int i; int ret; ret = regulator_enable(jadard->vccio); @@ -117,7 +107,15 @@ static int jadard_prepare(struct drm_panel *panel) msleep(10); gpiod_set_value(jadard->reset, 1); - msleep(120); + msleep(130); + + for (i = 0; i < desc->num_init_cmds; i++) { + const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; + + ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); + if (ret < 0) + return ret; + } return 0; } From patchwork Fri Jun 28 12:44:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhaoxiong Lv X-Patchwork-Id: 13716081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 716EEC2BD09 for ; Fri, 28 Jun 2024 12:45:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 970C410EC2E; Fri, 28 Jun 2024 12:45:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="QECNFTS9"; dkim-atps=neutral Received: from mail-pg1-f174.google.com (mail-pg1-f174.google.com [209.85.215.174]) by gabe.freedesktop.org (Postfix) with ESMTPS id 239A710EC34 for ; Fri, 28 Jun 2024 12:45:10 +0000 (UTC) Received: by mail-pg1-f174.google.com with SMTP id 41be03b00d2f7-713fa1aea36so240741a12.1 for ; Fri, 28 Jun 2024 05:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20230601.gappssmtp.com; s=20230601; t=1719578709; x=1720183509; darn=lists.freedesktop.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=rg3tdU7ppY8HgCadeya2IfmEx35gEyixCgdQukzslp8=; b=QECNFTS90X7jOV+7tQMZIATdTKaaA2ARPuO3++pmVlsx36f9saTONmTpXmJCU8CnGA 5B4C4L1Rt4lvaA1c2IE7ddzF1EH+zXuzGoOXt9JhhmD+DZsF2h9HUDaxHxnVDvW1mKu7 Qm8yHZB9Pw9EA0O6c0mpHXNxBYOHtxJJmLNXf4R6Oq4pUWKhSlMMlwWq67L5u/UtWXew nVlIWTMtbXJ91atS6ZBv9/PYxyRCpv9ct+JbVhCTkolHUfK/+flmRBWHCYxE6H27BSOq 1is/F/y4qb8H7y6eI65+P77BcuZ7Ter85QgbbMyNr8KBpKTRFVcPM1ZcA7bLCrZysIDR 7UiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719578709; x=1720183509; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rg3tdU7ppY8HgCadeya2IfmEx35gEyixCgdQukzslp8=; b=MkMVvx57wKO6FVXT931jMzwsbgRpeAFweyhKpkbPmKHdiwAeGj66SI+5CrjtXAZJTV QpHtnYx+/2FeQXI6BZzr1exjfso6YMuVdatHmQkpyT4vDtDwVR8hsVIrqJdJoXNtZn4f jWaR316iU++KD3YphAQLIoIQJvTPgSIrBOLCXhZAabQjx5gOvyxEnSw68IUZdlZ16ZkP IuLEAoaV9/BP3b6K7ewYN6zoi1fMUEkuodrg1TMvcdIX2vTQffhUT4QEr2v3kAurLIR8 NTvE2qhATYuOY2zXm+ly4+2eMH2cnCvf5DlaJjiXKwsrGgM1HnJDk31TILJSaKd1i5ib PKkg== X-Gm-Message-State: AOJu0YwYeHFMVckrMbcw1l9eeFO72hc1fn7EUXSEmQSb/h1NShQpqgN+ Ni2K/vgE+V2mmRjklD2uy0BRE2Fs7QC9iHyh4SLwAdCXBF6wh5f8YgFbuXe/pd8= X-Google-Smtp-Source: AGHT+IGi1fGSVYxtAxmFf/MTdTm122/UI6yNXUDQyXrOEFT3f8SKiRbbUQL8tC6sqxHVlH4xLvD96Q== X-Received: by 2002:a05:6a20:72a0:b0:1be:eae8:9975 with SMTP id adf61e73a8af0-1beeae89b72mr627357637.15.1719578709482; Fri, 28 Jun 2024 05:45:09 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac15695b4sm14346255ad.225.2024.06.28.05.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 05:45:09 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v6 2/5] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Date: Fri, 28 Jun 2024 20:44:41 +0800 Message-Id: <20240628124444.28152-3-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The kingdisplay-kd101ne3 is a 10.1" WXGA TFT-LCD panel with jadard-jd9365da controller. Hence, we add a new compatible with panel specific config. Signed-off-by: Zhaoxiong Lv Acked-by: Conor Dooley --- Changes between V6 and V5: - 1. No changes. V5:https://lore.kernel.org/all/20240624141926.5250-3-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V5 and V4: - 1. No changes. V4:https://lore.kernel.org/all/20240620080509.18504-3-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V4 and V3: - 1. Move positions to keep the list sorted. V3:https://lore.kernel.org/all/20240614145510.22965-3-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V3 and V2: - 1. Abandon the V2 patch and add kingdisplay kd101ne3-40ti binding to - jadard,jd9365da-h3.yaml again. V2:https://lore.kernel.org/all/20240601084528.22502-2-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V2 and V1: - Drop some properties that have already been defined in panel-common. - The header file 'dt-bindings/gpio/gpio.h' is not used, delete it V1: https://lore.kernel.org/all/20240418081548.12160-2-lvzhaoxiong@huaqin.corp-partner.google.com/ --- .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml index 41eb7fbf7715..2b977292dc48 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - chongzhou,cz101b4001 + - kingdisplay,kd101ne3-40ti - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 - const: jadard,jd9365da-h3 From patchwork Fri Jun 28 12:44:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhaoxiong Lv X-Patchwork-Id: 13716082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77B8AC3064D for ; Fri, 28 Jun 2024 12:45:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 939D010EC38; Fri, 28 Jun 2024 12:45:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="yUbX4zh2"; dkim-atps=neutral Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CFA510EC34 for ; Fri, 28 Jun 2024 12:45:19 +0000 (UTC) Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1f9b523a15cso3954455ad.0 for ; Fri, 28 Jun 2024 05:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20230601.gappssmtp.com; s=20230601; t=1719578719; x=1720183519; darn=lists.freedesktop.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=tuDunQvtG/SUyhwA7yNBiZ77ORIPkpr9AJ7uT4xV9p4=; b=yUbX4zh2POntzwfpb6QH/2/CkyFeHfbxbkRbj4FscSwRaBXYlInZY1Kv9LyYohjmGO 2uJuBdR2lXsXuTv/kq6MgBmhZBOKGI61IGWiTv4DFMe6y/AvIh/afmvtbKYAzHsFg6/8 /HNlPOkxh3wvZJNlNx3kTW6P4u41SQVsY3XipRW2jHDAhRsvsA93CEv3jhgexp5ctlcF OziiijvvrpzEEiHoeKBqt0Qvd/cN43kxPPF1XiTEZsLRrycv17G8KrAJ+fhZS/x0pItk fhlBpelLqMJ8B3HnstWs0tR4cupdjlazmfnKFBeFCEAlEAp2m1L02Dvw1c6D76Sx20jG QLKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719578719; x=1720183519; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tuDunQvtG/SUyhwA7yNBiZ77ORIPkpr9AJ7uT4xV9p4=; b=QFeT+W7Jr/NMdP6xU+WnZRve6dweJ1pooUO40fznMbZmqii/zRU24OVqommYnc+GaH gQcKbpTQ6DDmBHH72lqeNmeUEea6ZrcV/qVUa5B1pqxcNvDjXJrOT9WRAyRPOne/QhrE QG/IVQ0HcM3Bt0Y/hJ4t5gibXlYGFgZIjOx9bhvyPTq7dh989LLA/Fd3g6YFCfLT43BR fhHWROIUumqjFHAU358qxX6CAmJGmgit7RfPhzdT06UFPCuknUW7Se2pkPc8kKVGaSaG JElErCuBAEZ8h+UJd63D15ZDBFh5rNIOuC/91RJ5AcTuyCe0VxKhTlVaLhhpwTWChg4h hR9w== X-Gm-Message-State: AOJu0YzcWKeoAMGuhYKYiwcqaPDHWw6o1XC81evXnCZ2q32PLHdS/HqA 6kIXqKrTXVWndCap8w0XYIxHRDi9BLJDFe15IqMx0pjnYo7nkK6zDug6G2sIV3Q= X-Google-Smtp-Source: AGHT+IHAdbigbrlcf+3AeJjYGHIdE2GN0atj1xD07/ssCJ2VGi6ClkGSR2VDV6RmNNk7IOU7i93r1Q== X-Received: by 2002:a17:903:40d0:b0:1fa:38f4:b5d0 with SMTP id d9443c01a7336-1fac7e4c28emr22845805ad.13.1719578718814; Fri, 28 Jun 2024 05:45:18 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac15695b4sm14346255ad.225.2024.06.28.05.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 05:45:18 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v6 3/5] drm/panel: panel-jadard-jd9365da-h3: use wrapped MIPI DCS functions Date: Fri, 28 Jun 2024 20:44:42 +0800 Message-Id: <20240628124444.28152-4-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to simplify driver's init/enable/exit code. Signed-off-by: Zhaoxiong Lv Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Reviewed-by: Jessica Zhang --- Changes between V6 and V5: - 1. Convert the hex in init_code from UPPERCASE to lowercase. V4:https://lore.kernel.org/all/20240624141926.5250-4-lvzhaoxiong@huaqin.corp-partner.google.com/ --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 793 +++++++++--------- 1 file changed, 390 insertions(+), 403 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index a9c483a7b3fa..ff232a83297f 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -19,17 +19,13 @@ #include #include -#define JD9365DA_INIT_CMD_LEN 2 - -struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; -}; +struct jadard; struct jadard_panel_desc { const struct drm_display_mode mode; unsigned int lanes; enum mipi_dsi_pixel_format format; - const struct jadard_init_cmd *init_cmds; + int (*init)(struct jadard *jadard); u32 num_init_cmds; }; @@ -50,46 +46,33 @@ static inline struct jadard *panel_to_jadard(struct drm_panel *panel) static int jadard_enable(struct drm_panel *panel) { - struct device *dev = panel->dev; struct jadard *jadard = panel_to_jadard(panel); - struct mipi_dsi_device *dsi = jadard->dsi; - int err; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; msleep(120); - err = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (err < 0) - DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); - err = mipi_dsi_dcs_set_display_on(dsi); - if (err < 0) - DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - return 0; + return dsi_ctx.accum_err; } static int jadard_disable(struct drm_panel *panel) { - struct device *dev = panel->dev; struct jadard *jadard = panel_to_jadard(panel); - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; - ret = mipi_dsi_dcs_set_display_off(jadard->dsi); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); - ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); - return 0; + return dsi_ctx.accum_err; } static int jadard_prepare(struct drm_panel *panel) { struct jadard *jadard = panel_to_jadard(panel); - const struct jadard_panel_desc *desc = jadard->desc; - unsigned int i; int ret; ret = regulator_enable(jadard->vccio); @@ -109,13 +92,9 @@ static int jadard_prepare(struct drm_panel *panel) gpiod_set_value(jadard->reset, 1); msleep(130); - for (i = 0; i < desc->num_init_cmds; i++) { - const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; - - ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); - if (ret < 0) - return ret; - } + ret = jadard->desc->init(jadard); + if (ret) + return ret; return 0; } @@ -165,176 +144,181 @@ static const struct drm_panel_funcs jadard_funcs = { .get_modes = jadard_get_modes, }; -static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = { - { .data = { 0xE0, 0x00 } }, - { .data = { 0xE1, 0x93 } }, - { .data = { 0xE2, 0x65 } }, - { .data = { 0xE3, 0xF8 } }, - { .data = { 0x80, 0x03 } }, - { .data = { 0xE0, 0x01 } }, - { .data = { 0x00, 0x00 } }, - { .data = { 0x01, 0x7E } }, - { .data = { 0x03, 0x00 } }, - { .data = { 0x04, 0x65 } }, - { .data = { 0x0C, 0x74 } }, - { .data = { 0x17, 0x00 } }, - { .data = { 0x18, 0xB7 } }, - { .data = { 0x19, 0x00 } }, - { .data = { 0x1A, 0x00 } }, - { .data = { 0x1B, 0xB7 } }, - { .data = { 0x1C, 0x00 } }, - { .data = { 0x24, 0xFE } }, - { .data = { 0x37, 0x19 } }, - { .data = { 0x38, 0x05 } }, - { .data = { 0x39, 0x00 } }, - { .data = { 0x3A, 0x01 } }, - { .data = { 0x3B, 0x01 } }, - { .data = { 0x3C, 0x70 } }, - { .data = { 0x3D, 0xFF } }, - { .data = { 0x3E, 0xFF } }, - { .data = { 0x3F, 0xFF } }, - { .data = { 0x40, 0x06 } }, - { .data = { 0x41, 0xA0 } }, - { .data = { 0x43, 0x1E } }, - { .data = { 0x44, 0x0F } }, - { .data = { 0x45, 0x28 } }, - { .data = { 0x4B, 0x04 } }, - { .data = { 0x55, 0x02 } }, - { .data = { 0x56, 0x01 } }, - { .data = { 0x57, 0xA9 } }, - { .data = { 0x58, 0x0A } }, - { .data = { 0x59, 0x0A } }, - { .data = { 0x5A, 0x37 } }, - { .data = { 0x5B, 0x19 } }, - { .data = { 0x5D, 0x78 } }, - { .data = { 0x5E, 0x63 } }, - { .data = { 0x5F, 0x54 } }, - { .data = { 0x60, 0x49 } }, - { .data = { 0x61, 0x45 } }, - { .data = { 0x62, 0x38 } }, - { .data = { 0x63, 0x3D } }, - { .data = { 0x64, 0x28 } }, - { .data = { 0x65, 0x43 } }, - { .data = { 0x66, 0x41 } }, - { .data = { 0x67, 0x43 } }, - { .data = { 0x68, 0x62 } }, - { .data = { 0x69, 0x50 } }, - { .data = { 0x6A, 0x57 } }, - { .data = { 0x6B, 0x49 } }, - { .data = { 0x6C, 0x44 } }, - { .data = { 0x6D, 0x37 } }, - { .data = { 0x6E, 0x23 } }, - { .data = { 0x6F, 0x10 } }, - { .data = { 0x70, 0x78 } }, - { .data = { 0x71, 0x63 } }, - { .data = { 0x72, 0x54 } }, - { .data = { 0x73, 0x49 } }, - { .data = { 0x74, 0x45 } }, - { .data = { 0x75, 0x38 } }, - { .data = { 0x76, 0x3D } }, - { .data = { 0x77, 0x28 } }, - { .data = { 0x78, 0x43 } }, - { .data = { 0x79, 0x41 } }, - { .data = { 0x7A, 0x43 } }, - { .data = { 0x7B, 0x62 } }, - { .data = { 0x7C, 0x50 } }, - { .data = { 0x7D, 0x57 } }, - { .data = { 0x7E, 0x49 } }, - { .data = { 0x7F, 0x44 } }, - { .data = { 0x80, 0x37 } }, - { .data = { 0x81, 0x23 } }, - { .data = { 0x82, 0x10 } }, - { .data = { 0xE0, 0x02 } }, - { .data = { 0x00, 0x47 } }, - { .data = { 0x01, 0x47 } }, - { .data = { 0x02, 0x45 } }, - { .data = { 0x03, 0x45 } }, - { .data = { 0x04, 0x4B } }, - { .data = { 0x05, 0x4B } }, - { .data = { 0x06, 0x49 } }, - { .data = { 0x07, 0x49 } }, - { .data = { 0x08, 0x41 } }, - { .data = { 0x09, 0x1F } }, - { .data = { 0x0A, 0x1F } }, - { .data = { 0x0B, 0x1F } }, - { .data = { 0x0C, 0x1F } }, - { .data = { 0x0D, 0x1F } }, - { .data = { 0x0E, 0x1F } }, - { .data = { 0x0F, 0x5F } }, - { .data = { 0x10, 0x5F } }, - { .data = { 0x11, 0x57 } }, - { .data = { 0x12, 0x77 } }, - { .data = { 0x13, 0x35 } }, - { .data = { 0x14, 0x1F } }, - { .data = { 0x15, 0x1F } }, - { .data = { 0x16, 0x46 } }, - { .data = { 0x17, 0x46 } }, - { .data = { 0x18, 0x44 } }, - { .data = { 0x19, 0x44 } }, - { .data = { 0x1A, 0x4A } }, - { .data = { 0x1B, 0x4A } }, - { .data = { 0x1C, 0x48 } }, - { .data = { 0x1D, 0x48 } }, - { .data = { 0x1E, 0x40 } }, - { .data = { 0x1F, 0x1F } }, - { .data = { 0x20, 0x1F } }, - { .data = { 0x21, 0x1F } }, - { .data = { 0x22, 0x1F } }, - { .data = { 0x23, 0x1F } }, - { .data = { 0x24, 0x1F } }, - { .data = { 0x25, 0x5F } }, - { .data = { 0x26, 0x5F } }, - { .data = { 0x27, 0x57 } }, - { .data = { 0x28, 0x77 } }, - { .data = { 0x29, 0x35 } }, - { .data = { 0x2A, 0x1F } }, - { .data = { 0x2B, 0x1F } }, - { .data = { 0x58, 0x40 } }, - { .data = { 0x59, 0x00 } }, - { .data = { 0x5A, 0x00 } }, - { .data = { 0x5B, 0x10 } }, - { .data = { 0x5C, 0x06 } }, - { .data = { 0x5D, 0x40 } }, - { .data = { 0x5E, 0x01 } }, - { .data = { 0x5F, 0x02 } }, - { .data = { 0x60, 0x30 } }, - { .data = { 0x61, 0x01 } }, - { .data = { 0x62, 0x02 } }, - { .data = { 0x63, 0x03 } }, - { .data = { 0x64, 0x6B } }, - { .data = { 0x65, 0x05 } }, - { .data = { 0x66, 0x0C } }, - { .data = { 0x67, 0x73 } }, - { .data = { 0x68, 0x09 } }, - { .data = { 0x69, 0x03 } }, - { .data = { 0x6A, 0x56 } }, - { .data = { 0x6B, 0x08 } }, - { .data = { 0x6C, 0x00 } }, - { .data = { 0x6D, 0x04 } }, - { .data = { 0x6E, 0x04 } }, - { .data = { 0x6F, 0x88 } }, - { .data = { 0x70, 0x00 } }, - { .data = { 0x71, 0x00 } }, - { .data = { 0x72, 0x06 } }, - { .data = { 0x73, 0x7B } }, - { .data = { 0x74, 0x00 } }, - { .data = { 0x75, 0xF8 } }, - { .data = { 0x76, 0x00 } }, - { .data = { 0x77, 0xD5 } }, - { .data = { 0x78, 0x2E } }, - { .data = { 0x79, 0x12 } }, - { .data = { 0x7A, 0x03 } }, - { .data = { 0x7B, 0x00 } }, - { .data = { 0x7C, 0x00 } }, - { .data = { 0x7D, 0x03 } }, - { .data = { 0x7E, 0x7B } }, - { .data = { 0xE0, 0x04 } }, - { .data = { 0x00, 0x0E } }, - { .data = { 0x02, 0xB3 } }, - { .data = { 0x09, 0x60 } }, - { .data = { 0x0E, 0x2A } }, - { .data = { 0x36, 0x59 } }, - { .data = { 0xE0, 0x00 } }, +static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xb7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xb7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x7b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + + return dsi_ctx.accum_err; }; static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { @@ -357,205 +341,209 @@ static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { }, .lanes = 4, .format = MIPI_DSI_FMT_RGB888, - .init_cmds = radxa_display_8hd_ad002_init_cmds, - .num_init_cmds = ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds), + .init = radxa_display_8hd_ad002_init_cmds, }; -static const struct jadard_init_cmd cz101b4001_init_cmds[] = { - { .data = { 0xE0, 0x00 } }, - { .data = { 0xE1, 0x93 } }, - { .data = { 0xE2, 0x65 } }, - { .data = { 0xE3, 0xF8 } }, - { .data = { 0x80, 0x03 } }, - { .data = { 0xE0, 0x01 } }, - { .data = { 0x00, 0x00 } }, - { .data = { 0x01, 0x3B } }, - { .data = { 0x0C, 0x74 } }, - { .data = { 0x17, 0x00 } }, - { .data = { 0x18, 0xAF } }, - { .data = { 0x19, 0x00 } }, - { .data = { 0x1A, 0x00 } }, - { .data = { 0x1B, 0xAF } }, - { .data = { 0x1C, 0x00 } }, - { .data = { 0x35, 0x26 } }, - { .data = { 0x37, 0x09 } }, - { .data = { 0x38, 0x04 } }, - { .data = { 0x39, 0x00 } }, - { .data = { 0x3A, 0x01 } }, - { .data = { 0x3C, 0x78 } }, - { .data = { 0x3D, 0xFF } }, - { .data = { 0x3E, 0xFF } }, - { .data = { 0x3F, 0x7F } }, - { .data = { 0x40, 0x06 } }, - { .data = { 0x41, 0xA0 } }, - { .data = { 0x42, 0x81 } }, - { .data = { 0x43, 0x14 } }, - { .data = { 0x44, 0x23 } }, - { .data = { 0x45, 0x28 } }, - { .data = { 0x55, 0x02 } }, - { .data = { 0x57, 0x69 } }, - { .data = { 0x59, 0x0A } }, - { .data = { 0x5A, 0x2A } }, - { .data = { 0x5B, 0x17 } }, - { .data = { 0x5D, 0x7F } }, - { .data = { 0x5E, 0x6B } }, - { .data = { 0x5F, 0x5C } }, - { .data = { 0x60, 0x4F } }, - { .data = { 0x61, 0x4D } }, - { .data = { 0x62, 0x3F } }, - { .data = { 0x63, 0x42 } }, - { .data = { 0x64, 0x2B } }, - { .data = { 0x65, 0x44 } }, - { .data = { 0x66, 0x43 } }, - { .data = { 0x67, 0x43 } }, - { .data = { 0x68, 0x63 } }, - { .data = { 0x69, 0x52 } }, - { .data = { 0x6A, 0x5A } }, - { .data = { 0x6B, 0x4F } }, - { .data = { 0x6C, 0x4E } }, - { .data = { 0x6D, 0x20 } }, - { .data = { 0x6E, 0x0F } }, - { .data = { 0x6F, 0x00 } }, - { .data = { 0x70, 0x7F } }, - { .data = { 0x71, 0x6B } }, - { .data = { 0x72, 0x5C } }, - { .data = { 0x73, 0x4F } }, - { .data = { 0x74, 0x4D } }, - { .data = { 0x75, 0x3F } }, - { .data = { 0x76, 0x42 } }, - { .data = { 0x77, 0x2B } }, - { .data = { 0x78, 0x44 } }, - { .data = { 0x79, 0x43 } }, - { .data = { 0x7A, 0x43 } }, - { .data = { 0x7B, 0x63 } }, - { .data = { 0x7C, 0x52 } }, - { .data = { 0x7D, 0x5A } }, - { .data = { 0x7E, 0x4F } }, - { .data = { 0x7F, 0x4E } }, - { .data = { 0x80, 0x20 } }, - { .data = { 0x81, 0x0F } }, - { .data = { 0x82, 0x00 } }, - { .data = { 0xE0, 0x02 } }, - { .data = { 0x00, 0x02 } }, - { .data = { 0x01, 0x02 } }, - { .data = { 0x02, 0x00 } }, - { .data = { 0x03, 0x00 } }, - { .data = { 0x04, 0x1E } }, - { .data = { 0x05, 0x1E } }, - { .data = { 0x06, 0x1F } }, - { .data = { 0x07, 0x1F } }, - { .data = { 0x08, 0x1F } }, - { .data = { 0x09, 0x17 } }, - { .data = { 0x0A, 0x17 } }, - { .data = { 0x0B, 0x37 } }, - { .data = { 0x0C, 0x37 } }, - { .data = { 0x0D, 0x47 } }, - { .data = { 0x0E, 0x47 } }, - { .data = { 0x0F, 0x45 } }, - { .data = { 0x10, 0x45 } }, - { .data = { 0x11, 0x4B } }, - { .data = { 0x12, 0x4B } }, - { .data = { 0x13, 0x49 } }, - { .data = { 0x14, 0x49 } }, - { .data = { 0x15, 0x1F } }, - { .data = { 0x16, 0x01 } }, - { .data = { 0x17, 0x01 } }, - { .data = { 0x18, 0x00 } }, - { .data = { 0x19, 0x00 } }, - { .data = { 0x1A, 0x1E } }, - { .data = { 0x1B, 0x1E } }, - { .data = { 0x1C, 0x1F } }, - { .data = { 0x1D, 0x1F } }, - { .data = { 0x1E, 0x1F } }, - { .data = { 0x1F, 0x17 } }, - { .data = { 0x20, 0x17 } }, - { .data = { 0x21, 0x37 } }, - { .data = { 0x22, 0x37 } }, - { .data = { 0x23, 0x46 } }, - { .data = { 0x24, 0x46 } }, - { .data = { 0x25, 0x44 } }, - { .data = { 0x26, 0x44 } }, - { .data = { 0x27, 0x4A } }, - { .data = { 0x28, 0x4A } }, - { .data = { 0x29, 0x48 } }, - { .data = { 0x2A, 0x48 } }, - { .data = { 0x2B, 0x1F } }, - { .data = { 0x2C, 0x01 } }, - { .data = { 0x2D, 0x01 } }, - { .data = { 0x2E, 0x00 } }, - { .data = { 0x2F, 0x00 } }, - { .data = { 0x30, 0x1F } }, - { .data = { 0x31, 0x1F } }, - { .data = { 0x32, 0x1E } }, - { .data = { 0x33, 0x1E } }, - { .data = { 0x34, 0x1F } }, - { .data = { 0x35, 0x17 } }, - { .data = { 0x36, 0x17 } }, - { .data = { 0x37, 0x37 } }, - { .data = { 0x38, 0x37 } }, - { .data = { 0x39, 0x08 } }, - { .data = { 0x3A, 0x08 } }, - { .data = { 0x3B, 0x0A } }, - { .data = { 0x3C, 0x0A } }, - { .data = { 0x3D, 0x04 } }, - { .data = { 0x3E, 0x04 } }, - { .data = { 0x3F, 0x06 } }, - { .data = { 0x40, 0x06 } }, - { .data = { 0x41, 0x1F } }, - { .data = { 0x42, 0x02 } }, - { .data = { 0x43, 0x02 } }, - { .data = { 0x44, 0x00 } }, - { .data = { 0x45, 0x00 } }, - { .data = { 0x46, 0x1F } }, - { .data = { 0x47, 0x1F } }, - { .data = { 0x48, 0x1E } }, - { .data = { 0x49, 0x1E } }, - { .data = { 0x4A, 0x1F } }, - { .data = { 0x4B, 0x17 } }, - { .data = { 0x4C, 0x17 } }, - { .data = { 0x4D, 0x37 } }, - { .data = { 0x4E, 0x37 } }, - { .data = { 0x4F, 0x09 } }, - { .data = { 0x50, 0x09 } }, - { .data = { 0x51, 0x0B } }, - { .data = { 0x52, 0x0B } }, - { .data = { 0x53, 0x05 } }, - { .data = { 0x54, 0x05 } }, - { .data = { 0x55, 0x07 } }, - { .data = { 0x56, 0x07 } }, - { .data = { 0x57, 0x1F } }, - { .data = { 0x58, 0x40 } }, - { .data = { 0x5B, 0x30 } }, - { .data = { 0x5C, 0x16 } }, - { .data = { 0x5D, 0x34 } }, - { .data = { 0x5E, 0x05 } }, - { .data = { 0x5F, 0x02 } }, - { .data = { 0x63, 0x00 } }, - { .data = { 0x64, 0x6A } }, - { .data = { 0x67, 0x73 } }, - { .data = { 0x68, 0x1D } }, - { .data = { 0x69, 0x08 } }, - { .data = { 0x6A, 0x6A } }, - { .data = { 0x6B, 0x08 } }, - { .data = { 0x6C, 0x00 } }, - { .data = { 0x6D, 0x00 } }, - { .data = { 0x6E, 0x00 } }, - { .data = { 0x6F, 0x88 } }, - { .data = { 0x75, 0xFF } }, - { .data = { 0x77, 0xDD } }, - { .data = { 0x78, 0x3F } }, - { .data = { 0x79, 0x15 } }, - { .data = { 0x7A, 0x17 } }, - { .data = { 0x7D, 0x14 } }, - { .data = { 0x7E, 0x82 } }, - { .data = { 0xE0, 0x04 } }, - { .data = { 0x00, 0x0E } }, - { .data = { 0x02, 0xB3 } }, - { .data = { 0x09, 0x61 } }, - { .data = { 0x0E, 0x48 } }, - { .data = { 0xE0, 0x00 } }, - { .data = { 0xE6, 0x02 } }, - { .data = { 0xE7, 0x0C } }, +static int cz101b4001_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xaf); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xaf); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xdd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x0c); + + return dsi_ctx.accum_err; }; static const struct jadard_panel_desc cz101b4001_desc = { @@ -578,8 +566,7 @@ static const struct jadard_panel_desc cz101b4001_desc = { }, .lanes = 4, .format = MIPI_DSI_FMT_RGB888, - .init_cmds = cz101b4001_init_cmds, - .num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds), + .init = cz101b4001_init_cmds, }; static int jadard_dsi_probe(struct mipi_dsi_device *dsi) From patchwork Fri Jun 28 12:44:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhaoxiong Lv X-Patchwork-Id: 13716083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4B04C30658 for ; Fri, 28 Jun 2024 12:45:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 130C810EC34; Fri, 28 Jun 2024 12:45:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="E5/jEJiH"; dkim-atps=neutral Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8578610EC34 for ; Fri, 28 Jun 2024 12:45:51 +0000 (UTC) Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1f480624d0fso3438315ad.1 for ; Fri, 28 Jun 2024 05:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20230601.gappssmtp.com; s=20230601; t=1719578751; x=1720183551; darn=lists.freedesktop.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=klRQXqJY3KktJ6k1yD9MBmpg/ejmcwgU6PkV3TJWnho=; b=E5/jEJiHk0de+Q/uQ1GFC9U2uE73FbWhu9Ly9fxs4bLxKniA4Eh2BBQ6tAAdQpt0tB /gfH12XVgvJwJsimqNmNNJkXlfGQQHmLE0AHbby2Uvn7SJvmgj9hxr6qfDYc6OjIcCa6 hXqxlftz7UyfN8wPGEWmDeq0XNRXPSTi/3LFy/s7eSTCQJnWPfxyk7VK2YNX8fFxtYJA fE9me9/lfS4m8tiQc5KckXy51+f+2SHwvKEHetAexyBUxMZPJDm9EqUToRi7tdFB11IE J6XKkO3191v9pL4zwDwUUFKapBtQau+PtT8s3nNYXgJWj4sJ+Sqf0OR18RXmLjPyp9mO 8zFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719578751; x=1720183551; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=klRQXqJY3KktJ6k1yD9MBmpg/ejmcwgU6PkV3TJWnho=; b=rOc5cebU7LwF+G+m7POIA9JyVfP8lw6B6ujWiKcyYHqFwUA3+pI3JUcwb/ZWRH6gM2 x0Fl92CU5sf0Xp2V4LoFDgG3E7tYCLc8mNUDlv55w1VpVXM9vWDk5BWrO0b/e7KVF5Vm apYiAky8zDSULEHVyQR1jE37SuIxJKrnPB/EPg5qPbDAQhvVoFRXyoZiJNCamrLqj6wF CzYBdrI74zGbeMXAaLoGHtVoF9bkkD743xKTj5yXpmcar2Z2MDUWxH2Mm2DU5bXGPfOG 7I+VvRdBsowTcr2qNRDlEBafYLF1aeUjBK134MSvT6qguSgJ2Ge/Z8C1TgoJtdx4Evmn JwLw== X-Gm-Message-State: AOJu0YzLamfKHKHTVrvTIq8DBcdbaiUNjEyQ2fx6vYZfrEBfglN4wOT8 7zpTZ0nlbcpFE45ia7wTVM5zllQVHcR/+UFqX9hDWI3OxZupLYGe5c0FMnFi8f8= X-Google-Smtp-Source: AGHT+IGTFb3gmYVkw9lDpDQPZWekyB3UUTtUCdQWgHzRB8+Xj13hkgumOG35cnHzPBToFoa/wt2FMg== X-Received: by 2002:a17:902:d4cf:b0:1fa:acf0:72c8 with SMTP id d9443c01a7336-1faacf07699mr34789995ad.18.1719578750982; Fri, 28 Jun 2024 05:45:50 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac15695b4sm14346255ad.225.2024.06.28.05.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 05:45:50 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v6 4/5] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel Date: Fri, 28 Jun 2024 20:44:43 +0800 Message-Id: <20240628124444.28152-5-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The K&d kd101ne3-40ti is a 10.1" WXGA TFT-LCD panel, use jd9365da controller,which fits in nicely with the existing panel-jadard-jd9365da-h3 driver.Hence,we add a new compatible with panel specific config. Although they have the same control IC, the two panels are different, and the timing will be slightly different, so we added some variables in struct jadard_panel_desc to control the timing. Signed-off-by: Zhaoxiong Lv Reviewed-by: Douglas Anderson Acked-by: Jessica Zhang --- Changes between V6 and V5: - 1. No changes. V5:https://lore.kernel.org/all/20240624141926.5250-5-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V5 and V4: - 1. Add a "_ms" suffix to the variables. - 2. Use more "_multi" in the enable/disable function - 3. Use mipi_dsi_dcs_write_seq_multi() in the init() function. V4:https://lore.kernel.org/all/20240620080509.18504-4-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V4 and V3: - 1. Use mipi_dsi_msleep. - 2. Adjust the ".clock" assignment format. - 3. Adjust "compatible" positions to keep the list sorted. V3:https://lore.kernel.org/all/20240614145510.22965-4-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V3 and V2: - 1. Give up creating a new driver and re-add K&d kd101ne3-40ti - configuration to the panel-jadard-jd9365da-h3.c driver. V2:https://lore.kernel.org/all/20240601084528.22502-3-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V2 and V1: - 1. Use the new mipi_dsi_dcs_write_seq_multi() function. - 2. Modify Move mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sleep_mode() to disable(), - and drop kingdisplay_panel_enter_sleep_mode(). - 3. If prepare fails, disable GPIO before regulators. - 4. This function drm_connector_set_panel_orientation() is no longer used. Delete it. - 5. Drop ".shutdown = kingdisplay_panel_shutdown". --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 277 ++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index ff232a83297f..b5265d95be4e 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -27,6 +27,15 @@ struct jadard_panel_desc { enum mipi_dsi_pixel_format format; int (*init)(struct jadard *jadard); u32 num_init_cmds; + bool lp11_before_reset; + bool reset_before_power_off_vcioo; + unsigned int vcioo_to_lp11_delay_ms; + unsigned int lp11_to_reset_delay_ms; + unsigned int exit_sleep_to_display_on_delay_ms; + unsigned int display_on_delay_ms; + unsigned int backlight_off_to_display_off_delay_ms; + unsigned int display_off_to_enter_sleep_delay_ms; + unsigned int enter_sleep_to_reset_down_delay_ms; }; struct jadard { @@ -53,8 +62,14 @@ static int jadard_enable(struct drm_panel *panel) mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + if (jadard->desc->exit_sleep_to_display_on_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->exit_sleep_to_display_on_delay_ms); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + if (jadard->desc->display_on_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_on_delay_ms); + return dsi_ctx.accum_err; } @@ -63,10 +78,19 @@ static int jadard_disable(struct drm_panel *panel) struct jadard *jadard = panel_to_jadard(panel); struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + if (jadard->desc->backlight_off_to_display_off_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->backlight_off_to_display_off_delay_ms); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + if (jadard->desc->display_off_to_enter_sleep_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_off_to_enter_sleep_delay_ms); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + if (jadard->desc->enter_sleep_to_reset_down_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->enter_sleep_to_reset_down_delay_ms); + return dsi_ctx.accum_err; } @@ -83,6 +107,18 @@ static int jadard_prepare(struct drm_panel *panel) if (ret) return ret; + if (jadard->desc->vcioo_to_lp11_delay_ms) + msleep(jadard->desc->vcioo_to_lp11_delay_ms); + + if (jadard->desc->lp11_before_reset) { + ret = mipi_dsi_dcs_nop(jadard->dsi); + if (ret) + return ret; + } + + if (jadard->desc->lp11_to_reset_delay_ms) + msleep(jadard->desc->lp11_to_reset_delay_ms); + gpiod_set_value(jadard->reset, 1); msleep(5); @@ -106,6 +142,12 @@ static int jadard_unprepare(struct drm_panel *panel) gpiod_set_value(jadard->reset, 1); msleep(120); + if (jadard->desc->reset_before_power_off_vcioo) { + gpiod_set_value(jadard->reset, 0); + + usleep_range(1000, 2000); + } + regulator_disable(jadard->vdd); regulator_disable(jadard->vccio); @@ -569,6 +611,237 @@ static const struct jadard_panel_desc cz101b4001_desc = { .init = cz101b4001_init_cmds, }; +static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + + return dsi_ctx.accum_err; +}; + +static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = { + .mode = { + .clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000, + + .hdisplay = 800, + .hsync_start = 800 + 24, + .hsync_end = 800 + 24 + 24, + .htotal = 800 + 24 + 24 + 24, + + .vdisplay = 1280, + .vsync_start = 1280 + 30, + .vsync_end = 1280 + 30 + 4, + .vtotal = 1280 + 30 + 4 + 8, + + .width_mm = 135, + .height_mm = 216, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init = kingdisplay_kd101ne3_init_cmds, + .lp11_before_reset = true, + .reset_before_power_off_vcioo = true, + .vcioo_to_lp11_delay_ms = 5, + .lp11_to_reset_delay_ms = 10, + .exit_sleep_to_display_on_delay_ms = 120, + .display_on_delay_ms = 20, + .backlight_off_to_display_off_delay_ms = 100, + .display_off_to_enter_sleep_delay_ms = 50, + .enter_sleep_to_reset_down_delay_ms = 100, +}; + static int jadard_dsi_probe(struct mipi_dsi_device *dsi) { struct device *dev = &dsi->dev; @@ -637,6 +910,10 @@ static const struct of_device_id jadard_of_match[] = { .compatible = "chongzhou,cz101b4001", .data = &cz101b4001_desc }, + { + .compatible = "kingdisplay,kd101ne3-40ti", + .data = &kingdisplay_kd101ne3_40ti_desc + }, { .compatible = "radxa,display-10hd-ad001", .data = &cz101b4001_desc From patchwork Fri Jun 28 12:44:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhaoxiong Lv X-Patchwork-Id: 13716084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34AEAC3064D for ; Fri, 28 Jun 2024 12:46:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E54B10EC35; Fri, 28 Jun 2024 12:45:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="t6g2mT0h"; dkim-atps=neutral Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) by gabe.freedesktop.org (Postfix) with ESMTPS id F3F5510EC35 for ; Fri, 28 Jun 2024 12:45:57 +0000 (UTC) Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-1f480624d10so3606555ad.1 for ; Fri, 28 Jun 2024 05:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20230601.gappssmtp.com; s=20230601; t=1719578757; x=1720183557; darn=lists.freedesktop.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=NYdcAWuXYTWQAAXUNDXbS02yL9oAgEK+cNVTslAtCcU=; b=t6g2mT0hA0nuTiL3uZF9v2J1d8O58huz70fJ2lbQZS+qY3TQxDUf7s//qbPasWxSQj 3ntpWNi3ymfDP6vfQ47kSQeB7ARYb4STCMgBnqN4kq0irlnADmDMxH74qtvMGczigJH8 yL7Wusjzpp2OWB2NWg8iQhduMNSg2ENWPxF7wSp2j4wCLvsaG1iOwF9CKDK/YRofJTzN zkD6b7EWucDilIp7CyKlyuN9atejRhX3fZ6umTToA5bWltMcBUjW9AEdlVHqFq5b+9Gj PKAE7ZcOp9Q+67ia8Lp8TJFaKnD1ErYp7miQoic24WXSUUo6kyjrPVr5gYMgmOQtaqmr ybdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719578757; x=1720183557; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NYdcAWuXYTWQAAXUNDXbS02yL9oAgEK+cNVTslAtCcU=; b=YQuWjgxTNyfbCIinmKF46kgd/urfm2UNgZ0u1f2Al9pDuSHLhBKZ7l4CZIU0djlBHB NR4JAVNW3V01DSRWbN0yrszTrm+sn/bV+Dwyj18Ii4JfA/d9Z2LEUb+LAsU3pLTUN0OH 1uEeCI4pnsod5nM5AtvSIMkAN+KGlAJKtadF3wl8xZYQw/a7CzBJIcUUJGZ/pHA3H+vH rWxXRjDVHokh5q3i05ser5e06FK3WIPznMYYvFsL1QmxQzgt0j+LXuoBr1Z7QvWSmKLs UJVqRq8jzMWCbOcU4mMbV54U909YRKbZ+Ny//y+s/TTpJ4N6hWoIisDTXm9D2+Gm8NbT +e6w== X-Gm-Message-State: AOJu0YwaUnBNy1j3/T7pyTxZmUopB9MFPo/XCEZZx4UUtpo2uxaWXImX Vj9ErLOyZQ5lOBg2z/mH4D+twOZyXNmWpwWdxBRm5Ln+yxLBg6vO6NAyqW0RIvI= X-Google-Smtp-Source: AGHT+IG+25MIgZJbSQk/taFj6VG+AknyVI+V2GARb6Z9W0SrNi26/KVVGwlFQTZ6sulU8JHp9mZozQ== X-Received: by 2002:a17:902:ea11:b0:1f9:b697:b246 with SMTP id d9443c01a7336-1fa1d3de553mr202286995ad.5.1719578757393; Fri, 28 Jun 2024 05:45:57 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac15695b4sm14346255ad.225.2024.06.28.05.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 05:45:56 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v6 5/5] drm/panel: jd9365da: Add the function of adjusting orientation Date: Fri, 28 Jun 2024 20:44:44 +0800 Message-Id: <20240628124444.28152-6-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240628124444.28152-1-lvzhaoxiong@huaqin.corp-partner.google.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This driver does not have the function to adjust the orientation, so this function is added. Signed-off-by: Zhaoxiong Lv Reviewed-by: Douglas Anderson Reviewed-by: Jessica Zhang --- Changes between V6 and V5: - 1. No changes. V5: https://lore.kernel.org/all/20240624141926.5250-6-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V5 and V4: - 1. Change dev_err() to dev_err_probe(). V4: https://lore.kernel.org/all/20240620080509.18504-5-lvzhaoxiong@huaqin.corp-partner.google.com/ Changes between V4 and V3: - No changes. --- drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index b5265d95be4e..f002a80527b1 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -42,7 +42,7 @@ struct jadard { struct drm_panel panel; struct mipi_dsi_device *dsi; const struct jadard_panel_desc *desc; - + enum drm_panel_orientation orientation; struct regulator *vdd; struct regulator *vccio; struct gpio_desc *reset; @@ -178,12 +178,20 @@ static int jadard_get_modes(struct drm_panel *panel, return 1; } +static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_panel *panel) +{ + struct jadard *jadard = panel_to_jadard(panel); + + return jadard->orientation; +} + static const struct drm_panel_funcs jadard_funcs = { .disable = jadard_disable, .unprepare = jadard_unprepare, .prepare = jadard_prepare, .enable = jadard_enable, .get_modes = jadard_get_modes, + .get_orientation = jadard_panel_get_orientation, }; static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) @@ -880,6 +888,10 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi) drm_panel_init(&jadard->panel, dev, &jadard_funcs, DRM_MODE_CONNECTOR_DSI); + ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get orientation\n"); + ret = drm_panel_of_backlight(&jadard->panel); if (ret) return ret;