From patchwork Mon Jul 1 08:25:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13717653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2493C2BD09 for ; Mon, 1 Jul 2024 08:25:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.751339.1159255 (Exim 4.92) (envelope-from ) id 1sOCLf-0006Rm-V6; Mon, 01 Jul 2024 08:25:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 751339.1159255; Mon, 01 Jul 2024 08:25:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sOCLf-0006RE-SF; Mon, 01 Jul 2024 08:25:19 +0000 Received: by outflank-mailman (input) for mailman id 751339; Mon, 01 Jul 2024 08:25:18 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sOCLe-0006R3-Mx for xen-devel@lists.xenproject.org; Mon, 01 Jul 2024 08:25:18 +0000 Received: from pb-smtp20.pobox.com (pb-smtp20.pobox.com [173.228.157.52]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 70e2b01a-3783-11ef-b4bb-af5377834399; Mon, 01 Jul 2024 10:25:16 +0200 (CEST) Received: from pb-smtp20.pobox.com (unknown [127.0.0.1]) by pb-smtp20.pobox.com (Postfix) with ESMTP id E4BFD19E1B; Mon, 1 Jul 2024 04:25:13 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp20.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp20.pobox.com (Postfix) with ESMTP id DD30B19E1A; Mon, 1 Jul 2024 04:25:13 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [46.211.5.251]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp20.pobox.com (Postfix) with ESMTPSA id 7E52C19E19; Mon, 1 Jul 2024 04:25:10 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 70e2b01a-3783-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:mime-version:content-transfer-encoding; s=sasl; bh=zjWAT/kxmJqbEXZbahfspC9tyZt5NOyCrJQMNAB7xII=; b=QKhg b2EyWYiV6veseM4oqBBaR4p97pnzokLTOTvbidu8KkEjntBDqozb0TJVEX0x8uTk fOEheJWizca+89NkMVWzi7EWX4uNlMXrEMprYuMeXgnlVSM8Jwwuq4jurIo8bSU1 lP+vbuhh7Sho9AoUIahIdU/F3mB3LHfbG4c7B5Q= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Stefano Stabellini , Andrew Cooper , Jan Beulich Subject: [XEN PATCH v2] x86/intel: optional build of TSX support Date: Mon, 1 Jul 2024 11:25:06 +0300 Message-Id: <20240701082506.190941-1-Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Pobox-Relay-ID: 6E77753A-3783-11EF-BE1A-C38742FD603B-90055647!pb-smtp20.pobox.com Transactional Synchronization Extensions are supported on certain Intel's CPUs only, hence can be put under CONFIG_INTEL build option. The whole TSX support, even if supported by CPU, may need to be disabled via options, by microcode or through spec-ctrl, depending on a set of specific conditions. To make sure nothing gets accidentally runtime-broken all modifications of global TSX configuration variables is secured by #ifdef's, while variables themselves redefined to 0, so that ones can't mistakenly be written to. Signed-off-by: Sergiy Kibrik CC: Andrew Cooper CC: Jan Beulich Acked-by: Jan Beulich --- changes in v2: - updated command line doc - updated patch description - make tsx_init() stub one line --- docs/misc/xen-command-line.pandoc | 2 +- xen/arch/x86/Makefile | 2 +- xen/arch/x86/include/asm/processor.h | 6 ++++++ xen/arch/x86/spec_ctrl.c | 4 ++++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 1dea7431fa..2dc946a35d 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2584,7 +2584,7 @@ pages) must also be specified via the tbuf_size parameter. ### tsx = - Applicability: x86 + Applicability: x86 with CONFIG_INTEL active Default: false on parts vulnerable to TAA, true otherwise Controls for the use of Transactional Synchronization eXtensions. diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index d902fb7acc..286c003ec3 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -67,7 +67,7 @@ obj-y += srat.o obj-y += string.o obj-y += time.o obj-y += traps.o -obj-y += tsx.o +obj-$(CONFIG_INTEL) += tsx.o obj-y += usercopy.o obj-y += x86_emulate.o obj-$(CONFIG_TBOOT) += tboot.o diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h index c26ef9090c..66463f6a6d 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -503,9 +503,15 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint8_t *model, return fam; } +#ifdef CONFIG_INTEL extern int8_t opt_tsx; extern bool rtm_disabled; void tsx_init(void); +#else +#define opt_tsx 0 /* explicitly indicate TSX is off */ +#define rtm_disabled false /* RTM was not force-disabled */ +static inline void tsx_init(void) {} +#endif void update_mcu_opt_ctrl(void); void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val); diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 40f6ae0170..6b3631e375 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -116,8 +116,10 @@ static int __init cf_check parse_spec_ctrl(const char *s) if ( opt_pv_l1tf_domu < 0 ) opt_pv_l1tf_domu = 0; +#ifdef CONFIG_INTEL if ( opt_tsx == -1 ) opt_tsx = -3; +#endif disable_common: opt_rsb_pv = false; @@ -2264,6 +2266,7 @@ void __init init_speculation_mitigations(void) * plausibly value TSX higher than Hyperthreading...), disable TSX to * mitigate TAA. */ +#ifdef CONFIG_INTEL if ( opt_tsx == -1 && cpu_has_bug_taa && cpu_has_tsx_ctrl && ((hw_smt_enabled && opt_smt) || !boot_cpu_has(X86_FEATURE_SC_VERW_IDLE)) ) @@ -2271,6 +2274,7 @@ void __init init_speculation_mitigations(void) opt_tsx = 0; tsx_init(); } +#endif /* * On some SRBDS-affected hardware, it may be safe to relax srb-lock by