From patchwork Mon Jul 1 16:20:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13718367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9737C3065B for ; Mon, 1 Jul 2024 16:21:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=foX87Q35xBXng5Wl1QSeaFlNvKSPs7buApce6Aj2ce8=; b=luZb4TlDDaQa9HVgzCAJO6Jrfg y1eB8A8RHg4P6OZV+VUaVe1wMED7ZU1InJFVS9MRQu8goCXo5lINCDi7dsTkaj5STUwEunuvh33l1 pQxAdkevX1W2z25ILbVyH4iVHqZ2+DZj+JF8d77pCvYjG0qUFwxXTUS9w1t0b40yuw457lXiddxP6 ysclCvt8zQr74gQKFVkJ+Sa6PlBMN7dyhWAbJgIXYAKMAU2Coe0gCAf+/m1BpviZ274Qg+wE31Nh5 K8BVwbJj8URunstDkcQqWlYGjxR3m2YKbADUuKePD3FqFsd3fs6cDp3BTIyYDl71bESF//1XBX8zV K7fmIVQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOJm3-000000045Zh-1Fyv; Mon, 01 Jul 2024 16:21:03 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOJlk-000000045Pd-3O1a for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 16:20:46 +0000 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1fa78306796so17786995ad.3 for ; Mon, 01 Jul 2024 09:20:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719850844; x=1720455644; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=foX87Q35xBXng5Wl1QSeaFlNvKSPs7buApce6Aj2ce8=; b=R2LslnTiG4fZxGsNuTgB130edD9TZfVzPEHmoI7+di/nuUhZU6vNNAr/M2Rtmv/DJi ZcudV2lI6nt25BnHsIi8Mqg/RuZgwvWqJ0QWKtHZUudpeT1kr6tGOES5DC8q68tHTiT+ 7XrghuZAxo8uAqesIN3BRhf+VMeuEqYGlCMWYTLCVcYtrGZI3u4lCk18fTwYY8Y90YrK 2hik2N4VpL0ANjEMupZVm3IReEmXWG/XqhkdB9WwDH+zePGDznkRBlxB9z+kOeaoeQ6k Z9qBBIMQcw2DruVhlQGTu+qisyQgHg2mMIuvvTxl9vTcGCoVTA0zCHRrjLuWBwa3YoQK mu0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719850844; x=1720455644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=foX87Q35xBXng5Wl1QSeaFlNvKSPs7buApce6Aj2ce8=; b=siGXSrG0f2bABZDCxgfXWVUDu0khb2oyB8zaaJ69ilP3ttn359wwgwbsRigtFPp39l ay3eaSy0o+Fcb0bukiurAHEPA/A1AiQ/JJj5daEuiwsDtJ18tBD9zPXnMhCbZrRCc/UH 3Dzmv0Ngl1tVo11NY5x+jJbYED+GcPYo+//RO+1zOqJAJCnqOxxITgwNYGF7ftm4aZfu ZhvGh2dG/itaynQjjejxNLD6hBPYBJwoMaORSIC1Y5MhbTXr244V1ksnK0nzLXkKNSYO 5mZHTi7BBoYSdri1lOUFGgfelHKuy85hHLUimn6XcE2UYuxjhlRT0LnCTRj0kmS0XHU4 RcDQ== X-Forwarded-Encrypted: i=1; AJvYcCWg5UIiOVrG9dODg3RjG/D7uNwHoax2twtArAgI/Qlt9FhdDCfdScv2HpyGvP7eFVmDII9kPv2JM5mko5PC+R+IU3+lOwpWRrwTtdd9DnmGm3XZW7A= X-Gm-Message-State: AOJu0YxGUOxjLj7mY+D7/JUauXG0Fj7xFewroJquNvp3XEd/haBcRRs4 4ck+8fS/ldsAKqwbMlcfgaz8iMu/mC2tNnCcAspXSqQQic6sOBtP X-Google-Smtp-Source: AGHT+IGezuz9KcsCDkHHf6nqDerEGKPZp9rv7QW8gBS87OnSnt1vrKQewvteVEA7LabRrLMcMNIbBg== X-Received: by 2002:a17:902:ecce:b0:1f9:b16d:f97c with SMTP id d9443c01a7336-1fadbcf4391mr43164895ad.66.1719850843877; Mon, 01 Jul 2024 09:20:43 -0700 (PDT) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac1535cc8sm66487225ad.122.2024.07.01.09.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 09:20:43 -0700 (PDT) From: Rob Clark To: iommu@lists.linux.dev Cc: linux-arm-msm@vger.kernel.org, Stephen Boyd , Robin Murphy , Pranjal Shrivastava , Rob Clark , Thierry Reding , Krishna Reddy , Will Deacon , Joerg Roedel , Rob Clark , Jason Gunthorpe , Jerry Snitselaar , Krzysztof Kozlowski , Georgi Djakov , Dmitry Baryshkov , linux-tegra@vger.kernel.org (open list:TEGRA IOMMU DRIVERS), linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields Date: Mon, 1 Jul 2024 09:20:10 -0700 Message-ID: <20240701162025.375134-2-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240701162025.375134-1-robdclark@gmail.com> References: <20240701162025.375134-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_092044_877410_E972846D X-CRM114-Status: GOOD ( 19.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rob Clark For consistency, add the "CB" prefix to the bitfield defines for context registers. Signed-off-by: Rob Clark Reviewed-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 2 +- .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 18 +++---- drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +-- drivers/iommu/arm/arm-smmu/arm-smmu.h | 50 +++++++++---------- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 4 +- 5 files changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c index 957d988b6d83..4b2994b6126d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c @@ -200,7 +200,7 @@ static irqreturn_t nvidia_smmu_context_fault_bank(int irq, void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx); fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); - if (!(fsr & ARM_SMMU_FSR_FAULT)) + if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) return IRQ_NONE; fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c index 552199cbd9e2..e4ee78fb6a66 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -141,7 +141,7 @@ static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_doma writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG); fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if ((fsr & ARM_SMMU_FSR_FAULT) && (fsr & ARM_SMMU_FSR_SS)) { + if ((fsr & ARM_SMMU_CB_FSR_FAULT) && (fsr & ARM_SMMU_CB_FSR_SS)) { u32 sctlr_orig, sctlr; /* @@ -298,7 +298,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain, arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr); fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if (fsr & ARM_SMMU_FSR_FAULT) { + if (fsr & ARM_SMMU_CB_FSR_FAULT) { /* Clear pending interrupts */ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); @@ -306,7 +306,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain, * TBU halt takes care of resuming any stalled transcation. * Kept it here for completeness sake. */ - if (fsr & ARM_SMMU_FSR_SS) + if (fsr & ARM_SMMU_CB_FSR_SS) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE); } @@ -320,11 +320,11 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain, phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid); fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if (fsr & ARM_SMMU_FSR_FAULT) { + if (fsr & ARM_SMMU_CB_FSR_FAULT) { /* Clear pending interrupts */ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); - if (fsr & ARM_SMMU_FSR_SS) + if (fsr & ARM_SMMU_CB_FSR_SS) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE); } @@ -394,7 +394,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) DEFAULT_RATELIMIT_BURST); fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if (!(fsr & ARM_SMMU_FSR_FAULT)) + if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) return IRQ_NONE; fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); @@ -403,7 +403,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) if (list_empty(&tbu_list)) { ret = report_iommu_fault(&smmu_domain->domain, NULL, iova, - fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); if (ret == -ENOSYS) dev_err_ratelimited(smmu->dev, @@ -417,7 +417,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) phys_soft = ops->iova_to_phys(ops, iova); tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova, - fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); if (!tmp || tmp == -EBUSY) { dev_dbg(smmu->dev, "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n", @@ -481,7 +481,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); /* Retry or terminate any stalled transactions */ - if (fsr & ARM_SMMU_FSR_SS) + if (fsr & ARM_SMMU_CB_FSR_SS) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 87c81f75cf84..23cf91ac409b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -415,7 +415,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) int ret; fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if (!(fsr & ARM_SMMU_FSR_FAULT)) + if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) return IRQ_NONE; fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); @@ -423,7 +423,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); ret = report_iommu_fault(&smmu_domain->domain, NULL, iova, - fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); if (ret == -ENOSYS) dev_err_ratelimited(smmu->dev, @@ -1306,7 +1306,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; - if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_ATSR_ACTIVE), + if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_CB_ATSR_ACTIVE), 5, 50)) { spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); dev_err(dev, @@ -1642,7 +1642,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Make sure all context banks are disabled and clear CB_FSR */ for (i = 0; i < smmu->num_context_banks; ++i) { arm_smmu_write_context_bank(smmu, i); - arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); } /* Invalidate the TLB, just in case */ diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 4765c6945c34..b04a00126a12 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -196,34 +196,34 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_PAR_F BIT(0) #define ARM_SMMU_CB_FSR 0x58 -#define ARM_SMMU_FSR_MULTI BIT(31) -#define ARM_SMMU_FSR_SS BIT(30) -#define ARM_SMMU_FSR_UUT BIT(8) -#define ARM_SMMU_FSR_ASF BIT(7) -#define ARM_SMMU_FSR_TLBLKF BIT(6) -#define ARM_SMMU_FSR_TLBMCF BIT(5) -#define ARM_SMMU_FSR_EF BIT(4) -#define ARM_SMMU_FSR_PF BIT(3) -#define ARM_SMMU_FSR_AFF BIT(2) -#define ARM_SMMU_FSR_TF BIT(1) - -#define ARM_SMMU_FSR_IGN (ARM_SMMU_FSR_AFF | \ - ARM_SMMU_FSR_ASF | \ - ARM_SMMU_FSR_TLBMCF | \ - ARM_SMMU_FSR_TLBLKF) - -#define ARM_SMMU_FSR_FAULT (ARM_SMMU_FSR_MULTI | \ - ARM_SMMU_FSR_SS | \ - ARM_SMMU_FSR_UUT | \ - ARM_SMMU_FSR_EF | \ - ARM_SMMU_FSR_PF | \ - ARM_SMMU_FSR_TF | \ - ARM_SMMU_FSR_IGN) +#define ARM_SMMU_CB_FSR_MULTI BIT(31) +#define ARM_SMMU_CB_FSR_SS BIT(30) +#define ARM_SMMU_CB_FSR_UUT BIT(8) +#define ARM_SMMU_CB_FSR_ASF BIT(7) +#define ARM_SMMU_CB_FSR_TLBLKF BIT(6) +#define ARM_SMMU_CB_FSR_TLBMCF BIT(5) +#define ARM_SMMU_CB_FSR_EF BIT(4) +#define ARM_SMMU_CB_FSR_PF BIT(3) +#define ARM_SMMU_CB_FSR_AFF BIT(2) +#define ARM_SMMU_CB_FSR_TF BIT(1) + +#define ARM_SMMU_CB_FSR_IGN (ARM_SMMU_CB_FSR_AFF | \ + ARM_SMMU_CB_FSR_ASF | \ + ARM_SMMU_CB_FSR_TLBMCF | \ + ARM_SMMU_CB_FSR_TLBLKF) + +#define ARM_SMMU_CB_FSR_FAULT (ARM_SMMU_CB_FSR_MULTI | \ + ARM_SMMU_CB_FSR_SS | \ + ARM_SMMU_CB_FSR_UUT | \ + ARM_SMMU_CB_FSR_EF | \ + ARM_SMMU_CB_FSR_PF | \ + ARM_SMMU_CB_FSR_TF | \ + ARM_SMMU_CB_FSR_IGN) #define ARM_SMMU_CB_FAR 0x60 #define ARM_SMMU_CB_FSYNR0 0x68 -#define ARM_SMMU_FSYNR0_WNR BIT(4) +#define ARM_SMMU_CB_FSYNR0_WNR BIT(4) #define ARM_SMMU_CB_FSYNR1 0x6c @@ -237,7 +237,7 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_ATS1PR 0x800 #define ARM_SMMU_CB_ATSR 0x8f0 -#define ARM_SMMU_ATSR_ACTIVE BIT(0) +#define ARM_SMMU_CB_ATSR_ACTIVE BIT(0) #define ARM_SMMU_RESUME_TERMINATE BIT(0) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index e079bb7a993e..b98a7a598b89 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -194,7 +194,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev) fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR); - if (!(fsr & ARM_SMMU_FSR_FAULT)) + if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) return IRQ_NONE; fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0); @@ -274,7 +274,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, /* Clear context bank fault address fault status registers */ iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); - iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); /* TTBRs */ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, From patchwork Mon Jul 1 16:20:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13718368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 891A9C3065A for ; Mon, 1 Jul 2024 16:21:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=OWZgmKDZRrdhr1uUXK85/zqvq+/aZOrwP+oxnXRYvAE=; b=MPmwKIiX9hSzGTHnISA82z7IT8 apj833a+MX8Hv6UIbbaqKp6bQjlRvkfD3n5vQAwRGg+K95FOoQgVRwRUj44UijYv1adAyUI07vUuy 5OL/8yoy5jJ9kSBOxyp58qdrq7VTjnx2zjfQjyg4m5jMWIsPsF0OrcNTQuhFoDdcIzTIv8DNiMoai ljS9JIQhb3/mTquFjbQnEAh7rDjOfP2/eb7rFvtybnclYRlb/tUFpKQgJ+ixMtapMR+6r8Zw6Y62R u0MGppUx9wEYWUaULmKMRv+BVyI7vo0yzHMNzDKNQLZqHc8lhv/Yvnisw53pFgcNZ5egUxcOINCBu ji934Xdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOJmE-000000045eY-122J; Mon, 01 Jul 2024 16:21:14 +0000 Received: from mail-il1-x12f.google.com ([2607:f8b0:4864:20::12f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOJln-000000045Qx-1hkW for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 16:20:49 +0000 Received: by mail-il1-x12f.google.com with SMTP id e9e14a558f8ab-3762eadd807so11338985ab.1 for ; Mon, 01 Jul 2024 09:20:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719850846; x=1720455646; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OWZgmKDZRrdhr1uUXK85/zqvq+/aZOrwP+oxnXRYvAE=; b=MKqwzG6pM8tyVTpos6pCLUsdgXeXVxyOl8swDcJyxNTmqZO0eKESquhDlCpxEPjBtu AON753e8SywygSmB1phCN6ZG8k+mokEkuDZfLm1JvzfAQHax2dPEFlf81SPNj3XFdf/Z IT6VbM+zdXtRZ7WZuaULVHzZ3WEaHxci2OTCmk2MQMWrN2P56W38/aNa28FBBrASIKd7 lfvIYLDRKRt61tdYsngUqvCTbLHNuVM/a6Em2LDpLiACkTXVCc8vghOJAFfWMH9XgkNO 5uxaQnbrgRCDDvbFQs+BKPh144uL7Nt7yEbGIyab1+D4k6ydXdrxuM77GiEpOvIwCQox jSKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719850846; x=1720455646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OWZgmKDZRrdhr1uUXK85/zqvq+/aZOrwP+oxnXRYvAE=; b=ssLMbzO5fYIZMEasalJbKkMMpxhUnU3NWc4Kg8KV5LabSy02Bq2SXehW83cskdYP2K hd3Ooqx3TDT76gU7m7VJ6K3IWAjt1rAQJUkpl4EFwnpQjy0SRFRf2j+gvSxD91yhh1dV ZDDBxkKLR8FR0p21QVU29Q95LciHZGCSvoNHS/++9KwysVYYocYSYCvn2ljjdjPq7wvZ JbXMxMBFHLqsqPYcDwSkYw6obsTi3Z1x3RGcVZ4YO0J266NqBqKAwuIO8yfr89pP/lEd Ly1OdMPw1E9UH5TtDw2LU6hQ/E0XziVFpYOVegQGFsf2VUE83fhdUa7+VHd8K+TVC8va A1cA== X-Forwarded-Encrypted: i=1; AJvYcCUzpaLFd2BwQgqZgR0aFa8q5VUeR5bWDoSfBEWdp/BMltrJO/Y9ye1+4/p5WzP6nw/K0d9Towj1ogFWI/CXxvfw4Wkhg8DamFL7WrRx0v6Z7aqbJkE= X-Gm-Message-State: AOJu0YwfxFSVSFwEwUNAQM4rstDAEheLS8GmhYcuTrR4yRrOPJbixdp4 WprFpfpn0j5jpah3X26N0ZfjzK6XrBVyNf4ZT1BRDwqQTWxEoHtx X-Google-Smtp-Source: AGHT+IF4Q6jy5QIuCLxDiDWQRsnx6iHXwtvUgTE2lXBFYwEqB80Yt/8yPSYVyA6IBWuuR1iGqEUB/Q== X-Received: by 2002:a05:6e02:1645:b0:373:7f70:bb8f with SMTP id e9e14a558f8ab-37cd2bedbf5mr95954605ab.22.1719850846207; Mon, 01 Jul 2024 09:20:46 -0700 (PDT) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6c8ec501sm5246854a12.68.2024.07.01.09.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 09:20:45 -0700 (PDT) From: Rob Clark To: iommu@lists.linux.dev Cc: linux-arm-msm@vger.kernel.org, Stephen Boyd , Robin Murphy , Pranjal Shrivastava , Rob Clark , Rob Clark , Will Deacon , Joerg Roedel , linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults Date: Mon, 1 Jul 2024 09:20:11 -0700 Message-ID: <20240701162025.375134-3-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240701162025.375134-1-robdclark@gmail.com> References: <20240701162025.375134-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_092047_467113_11616120 X-CRM114-Status: GOOD ( 10.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rob Clark Handled faults can be "normal", don't spam dmesg about them. Signed-off-by: Rob Clark Reviewed-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c index e4ee78fb6a66..681fbdfc325d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -419,10 +419,6 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova, fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); if (!tmp || tmp == -EBUSY) { - dev_dbg(smmu->dev, - "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n", - iova, fsr, fsynr, idx); - dev_dbg(smmu->dev, "soft iova-to-phys=%pa\n", &phys_soft); ret = IRQ_HANDLED; resume = ARM_SMMU_RESUME_TERMINATE; } else { From patchwork Mon Jul 1 16:20:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13718369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A74BC2BD09 for ; Mon, 1 Jul 2024 16:21:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TcCQm16abjlGuhHVctKC5KbjGKSk1x2+sDYR2CB9B98=; b=noqeM+M/sbq25IG5i/D2+srU27 h51OZnWhKnMenqsTN8JpmHZKwC8XWNz7S1P1AUr3mytgv3VIpERDOFmedMJzSWHB+TSZBmsC2vZka 7MUvYrkT29luWAg6VR83CYW2nEiI4ow7/dnTxq5U77jO+2o8rCct+U29KDAhdL+dE8eI3gdkmvPLa 05mqQWISl9C7uY8gkeWUh+SQvgcUqUP9R56WaKzm4lfHjgBuN8mP1TGkcM8EnBPDUvU5L7JCX2zIr Z0Ibq12JpyRm7TaONRc4dDvZr/z53BqISet4Dfy5AYh0vH/Ro5fVndfCp8uKVuiBFvIKMxbsOXnea /omq0P6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOJmN-000000045k3-2tCY; Mon, 01 Jul 2024 16:21:23 +0000 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOJls-000000045TB-1uD3 for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 16:20:55 +0000 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-70698bcd19eso1961583b3a.0 for ; Mon, 01 Jul 2024 09:20:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719850851; x=1720455651; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TcCQm16abjlGuhHVctKC5KbjGKSk1x2+sDYR2CB9B98=; b=MJDwAs8+Zav20kzkqS7Ghp7kTjfJc6DUJBJAJm+LuopvTKt2dXXYleft23EWVjQ3a2 uce2zMAz/mh42ah5bC+LepvPXcpVPUQw4o7lsIKTU31SzNBtjPk6P1fNEmq43oDO+7WX xYcN9RanXNO/FlJOJiLyqqPZh309OR6Y+g2Uu2Xe6pxKOvTNaRL9Tsywl+h0RogEQSbn cXXVykQ7d+/E5cdVpVohbfd9m3nd1GVuXOO6ZEMwCXUwH47XbCmfeX0j9M8EnnVz5fi/ MRBC3ZU3ioU9itHWG9TwGh1I+iiL96GbEDOiAFFuVwofb9XM8p/bTydmDaeKQiYHsYE7 CfMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719850851; x=1720455651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TcCQm16abjlGuhHVctKC5KbjGKSk1x2+sDYR2CB9B98=; b=L0VPC3o64Sxww/qErFoUVf/3c6Re8VvzTfv8RvCYGV9v7SWcHLeDOSApuYszCvMocM dWNX/dARpY52NupXgjczhzPukomBMwPQ0602/W0Xv7Mt3i2KPxFmRyPMHxzM5FtoG4ca gOnQhWyw/kfnDQxh/a6eIpAXHk9DlDBKMnY+47r6bGlLfzz5Ig0NccoN4L7vQpEnRFxv FqC6+rTlF/OSHJmev4KhIH/0ulC8G2Ze9fZdZHu17De6T+AysyfBvRn16YFPmbKCfvW3 RsxW6z4t+q8o4rJyu1o1rBbly5oa7X9Sy6N9GsEn+IP+b6fTO+4igpXhGQAQYAx7K/dQ MUfA== X-Forwarded-Encrypted: i=1; AJvYcCXntUmiG9ZYC1mVGjdk07Q+a8BMUiHbrUxCAiDBuRzq6dDQ8GaJcn7n0tK9wavsvRm4Rxa5rl0IAB3i8k2wrU38I+8IN4manA/mAxMiShyfI+PzarM= X-Gm-Message-State: AOJu0Yxcinpix24GklgIsUjn3Y/RQ9keQWY+n9eu0QFlw/FU1KCsao/+ /9rfEBnVuZLvKl81mWYEkKN63do8G3AkPDe/DH21Q0w+Gve4dGvF X-Google-Smtp-Source: AGHT+IHrTptgHpbkf7m9fppXPFqapatA5w6Him+ZXaPS92rxGNkmx3F6YOre0k/mP2bMzO0C7aFkvQ== X-Received: by 2002:a05:6a20:3d81:b0:1be:f783:3d4f with SMTP id adf61e73a8af0-1bef783400bmr5430692637.43.1719850850678; Mon, 01 Jul 2024 09:20:50 -0700 (PDT) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac1538979sm66611085ad.159.2024.07.01.09.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 09:20:49 -0700 (PDT) From: Rob Clark To: iommu@lists.linux.dev Cc: linux-arm-msm@vger.kernel.org, Stephen Boyd , Robin Murphy , Pranjal Shrivastava , Rob Clark , Rob Clark , Will Deacon , Joerg Roedel , Jason Gunthorpe , Jerry Snitselaar , Rob Herring , Krzysztof Kozlowski , Georgi Djakov , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs Date: Mon, 1 Jul 2024 09:20:12 -0700 Message-ID: <20240701162025.375134-4-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240701162025.375134-1-robdclark@gmail.com> References: <20240701162025.375134-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_092052_551531_EE249052 X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rob Clark Parse out the bitfields for easier-to-read fault messages. Signed-off-by: Rob Clark Reviewed-by: Pranjal Shrivastava --- .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++--------- drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++---- drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++ 3 files changed, 92 insertions(+), 51 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c index 681fbdfc325d..ef93f825f11f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -383,64 +383,44 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) struct arm_smmu_domain *smmu_domain = dev; struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; struct arm_smmu_device *smmu = smmu_domain->smmu; - u32 fsr, fsynr, cbfrsynra, resume = 0; + struct arm_smmu_context_fault_info cfi; + u32 resume = 0; int idx = smmu_domain->cfg.cbndx; phys_addr_t phys_soft; - unsigned long iova; int ret, tmp; static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) - return IRQ_NONE; + arm_smmu_read_context_fault_info(smmu, idx, &cfi); - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) + return IRQ_NONE; if (list_empty(&tbu_list)) { - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova, - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); if (ret == -ENOSYS) - dev_err_ratelimited(smmu->dev, - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", - fsr, iova, fsynr, cbfrsynra, idx); + arm_smmu_print_context_fault_info(smmu, idx, &cfi); - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); return IRQ_HANDLED; } - phys_soft = ops->iova_to_phys(ops, iova); + phys_soft = ops->iova_to_phys(ops, cfi.iova); - tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova, - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + tmp = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); if (!tmp || tmp == -EBUSY) { ret = IRQ_HANDLED; resume = ARM_SMMU_RESUME_TERMINATE; } else { - phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, iova, fsr); + phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, cfi.iova, cfi.fsr); if (__ratelimit(&_rs)) { - dev_err(smmu->dev, - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", - fsr, iova, fsynr, cbfrsynra, idx); - dev_err(smmu->dev, - "FSR = %08x [%s%s%s%s%s%s%s%s%s], SID=0x%x\n", - fsr, - (fsr & 0x02) ? "TF " : "", - (fsr & 0x04) ? "AFF " : "", - (fsr & 0x08) ? "PF " : "", - (fsr & 0x10) ? "EF " : "", - (fsr & 0x20) ? "TLBMCF " : "", - (fsr & 0x40) ? "TLBLKF " : "", - (fsr & 0x80) ? "MHF " : "", - (fsr & 0x40000000) ? "SS " : "", - (fsr & 0x80000000) ? "MULTI " : "", - cbfrsynra); + arm_smmu_print_context_fault_info(smmu, idx, &cfi); dev_err(smmu->dev, "soft iova-to-phys=%pa\n", &phys_soft); @@ -474,10 +454,10 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) */ if (tmp != -EBUSY) { /* Clear the faulting FSR */ - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); /* Retry or terminate any stalled transactions */ - if (fsr & ARM_SMMU_CB_FSR_SS) + if (cfi.fsr & ARM_SMMU_CB_FSR_SS) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 23cf91ac409b..79ec911ae151 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = { .tlb_add_page = arm_smmu_tlb_add_page_s2_v1, }; + +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, + struct arm_smmu_context_fault_info *cfi) +{ + cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); + cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); + cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); + cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); +} + +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, + const struct arm_smmu_context_fault_info *cfi) +{ + dev_dbg(smmu->dev, + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", + cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx); + + dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n", + cfi->fsr, + (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "", + (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "", + (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr), + (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "", + (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "", + cfi->cbfrsynra); + + dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n", + cfi->fsynr, + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr), + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "", + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "", + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "", + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "", + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "", + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "", + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr)); +} + static irqreturn_t arm_smmu_context_fault(int irq, void *dev) { - u32 fsr, fsynr, cbfrsynra; - unsigned long iova; + struct arm_smmu_context_fault_info cfi; struct arm_smmu_domain *smmu_domain = dev; struct arm_smmu_device *smmu = smmu_domain->smmu; + static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, + DEFAULT_RATELIMIT_BURST); int idx = smmu_domain->cfg.cbndx; int ret; - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); - if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) - return IRQ_NONE; + arm_smmu_read_context_fault_info(smmu, idx, &cfi); - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) + return IRQ_NONE; - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova, - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); - if (ret == -ENOSYS) - dev_err_ratelimited(smmu->dev, - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", - fsr, iova, fsynr, cbfrsynra, idx); + if (ret == -ENOSYS && __ratelimit(&rs)) + arm_smmu_print_context_fault_info(smmu, idx, &cfi); - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); return IRQ_HANDLED; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index b04a00126a12..e2aeb511ae90 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -198,6 +198,7 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_FSR 0x58 #define ARM_SMMU_CB_FSR_MULTI BIT(31) #define ARM_SMMU_CB_FSR_SS BIT(30) +#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9) #define ARM_SMMU_CB_FSR_UUT BIT(8) #define ARM_SMMU_CB_FSR_ASF BIT(7) #define ARM_SMMU_CB_FSR_TLBLKF BIT(6) @@ -223,7 +224,14 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_FAR 0x60 #define ARM_SMMU_CB_FSYNR0 0x68 +#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0) #define ARM_SMMU_CB_FSYNR0_WNR BIT(4) +#define ARM_SMMU_CB_FSYNR0_PNU BIT(5) +#define ARM_SMMU_CB_FSYNR0_IND BIT(6) +#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8) +#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10) +#define ARM_SMMU_CB_FSYNR0_AFR BIT(11) +#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16) #define ARM_SMMU_CB_FSYNR1 0x6c @@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); +struct arm_smmu_context_fault_info { + unsigned long iova; + u32 fsr; + u32 fsynr; + u32 cbfrsynra; +}; + +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, + struct arm_smmu_context_fault_info *cfi); + +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, + const struct arm_smmu_context_fault_info *cfi); + #endif /* _ARM_SMMU_H */