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([178.197.219.137]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3675a1030dfsm12150875f8f.100.2024.07.01.23.35.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 23:35:18 -0700 (PDT) From: Krzysztof Kozlowski List-Id: To: Olof Johansson , Arnd Bergmann , arm@kernel.org, soc@kernel.org Cc: Krzysztof Kozlowski Subject: [GIT PULL 1/2] arm64: dts: samsung: DTS for v6.11 Date: Tue, 2 Jul 2024 08:35:08 +0200 Message-ID: <20240702063514.6215-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt64-6.11 for you to fetch changes up to 64c7ea42fcc2b972fc8d108642f4b8fabf0999c3: arm64: dts: exynos850: Enable TRNG (2024-07-01 14:27:09 +0200) ---------------------------------------------------------------- Samsung DTS ARM64 changes for v6.10 1. Google GS101: Minor cleanup and add fake regulators to USB phy, to satisfy dtbs_check. The PMIC providing these regulators is not yet implemented. 2. Exynos850: Add True Random Number Generator. ---------------------------------------------------------------- André Draszik (2): arm64: dts: exynos: gs101: reorder properties as per guidelines arm64: dts: exynos: gs101-oriole: add placeholder regulators for USB phy Sam Protsenko (1): arm64: dts: exynos850: Enable TRNG arch/arm64/boot/dts/exynos/exynos850.dtsi | 8 ++++++++ arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 9 ++++++++- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 22 +++++++++++----------- 3 files changed, 27 insertions(+), 12 deletions(-) From patchwork Tue Jul 2 06:35:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13719013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F08CBC3064D for ; Tue, 2 Jul 2024 06:35:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id D0B78C4AF0A; Tue, 2 Jul 2024 06:35:28 +0000 (UTC) Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id D6637C32781 for ; Tue, 2 Jul 2024 06:35:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org D6637C32781 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-36743abace4so3092513f8f.1 for ; Mon, 01 Jul 2024 23:35:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719902126; x=1720506926; darn=kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YuYZGZ40f/s8XcHh1CN5VPY9ouyMrtb4uHYgJzugWIk=; b=XbRsOvL85hoACpPHFocQBrdIPECGGMYk8FX/2AIsDozJ+x5772JfcfQQZYclyaMHNo qlOSS5vCyg4YuDeh2ofycL7e+5va8TY3E4KWxTLX5SaoBM51KhD7ECPddhDueIkkYRc8 xMBkbqpyyTYKLdDBXaeYJallH8/eNYaBx8A9oKitqOk3QqJTWH6lmWz1Z0IJeE5ySXcn Tn8Z8OofUiMCkThgJ2KR49OR7AFVZoBXFKIvZYj5nhGBnj36gYqH/ryFQwoxU7VGoT59 EtA0s75Ee6RKDswPTDTZmsNR6BNLQJAh79pAuv37ypKDPpVfcQ9rXIMw5+ZvGtUFmyke 4kgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719902126; x=1720506926; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YuYZGZ40f/s8XcHh1CN5VPY9ouyMrtb4uHYgJzugWIk=; b=U/E1DreSe8Dr2FS5FfdcMnR4ksZrJeaTXxqvI5k4XY0u0W26IACm0C6i5CDfxlGKb0 gr0rFrgfMBDEsSe+vikYWcnrjc2U8LWWNxKlM42CzxFNphwfOBz6g5ltR17CNIagjBW0 J1Vu49ZSlJMLC/nbxm69UqOm9m5NjBIA9nL8TcBJd2t0euhknFjD7iTyDTTVTZ4k47wq hP/h033dwfh39PFs9paBtm8Elu56oicfsrFDevLq6A3DP0sONrK/nMGPFmk/WC5qGNef 2TSHqb3zvNLad55WoyEF3Luo4EKjAvrZgQ3eJdIv9T3jSxv4mkqy+MDYiPJDGCc5xX9p uXLQ== X-Forwarded-Encrypted: i=1; AJvYcCVkiuGg1Fr3kLicYjlQrRAd0tA/lQGbv5rk/XCqFD1oC21rzlN1mK3NsoJMTOHHHD3q6f2osIXId3msBDAbDA== X-Gm-Message-State: AOJu0YyI4OXOZdNih44/eb+0ApICbXomaLiJW6IlD2LyRKwp8a7DnRJ+ 66BLHR2T0Kg2hObBCUZnLZSj265nC6RK5TLTlcVauVnNVWynZkBEcvmLBu+Qbc4= X-Google-Smtp-Source: AGHT+IFI7VpeBKngghf1BDh4qiD7nSZGmJvuVWoA0SVM8DHGI+moLOYhWPfN9qlnXfGnLd0yCMjbbA== X-Received: by 2002:a05:6000:1846:b0:365:aec0:e191 with SMTP id ffacd0b85a97d-36760a7c1demr12168539f8f.21.1719902126151; Mon, 01 Jul 2024 23:35:26 -0700 (PDT) Received: from krzk-bin.. ([178.197.219.137]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3675a1030dfsm12150875f8f.100.2024.07.01.23.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 23:35:25 -0700 (PDT) From: Krzysztof Kozlowski List-Id: To: Olof Johansson , Arnd Bergmann , arm@kernel.org, soc@kernel.org Cc: Krzysztof Kozlowski Subject: [GIT PULL 2/2 PATCH - drivers] soc: samsung: exynos-pmu: add support for PMU_ALIVE non atomic registers Date: Tue, 2 Jul 2024 08:35:09 +0200 Message-ID: <20240702063514.6215-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240702063514.6215-1-krzysztof.kozlowski@linaro.org> References: <20240702063514.6215-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 From: Peter Griffin Not all registers in PMU_ALIVE block support atomic set/clear operations. GS101_SYSIP_DAT0 and GS101_SYSTEM_CONFIGURATION registers are two regs where attempting atomic access fails. As documentation on exactly which registers support atomic operations is not forthcoming. We default to atomic access, unless the register is explicitly added to the tensor_is_atomic() function. Update the comment to reflect this as well. Reviewed-by: Will McVicker Tested-by: Will McVicker Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20240628223506.1237523-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-pmu.c | 22 ++++++++++++++++++--- include/linux/soc/samsung/exynos-regs-pmu.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index fd8b6ac06656..a0123070a816 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -129,14 +129,30 @@ static int tensor_set_bits_atomic(void *ctx, unsigned int offset, u32 val, return ret; } -static int tensor_sec_update_bits(void *ctx, unsigned int reg, - unsigned int mask, unsigned int val) +static bool tensor_is_atomic(unsigned int reg) { /* * Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF) - * as the target registers can be accessed by multiple masters. + * as the target registers can be accessed by multiple masters. SFRs + * that don't support atomic are added to the switch statement below. */ if (reg > PMUALIVE_MASK) + return false; + + switch (reg) { + case GS101_SYSIP_DAT0: + case GS101_SYSTEM_CONFIGURATION: + return false; + default: + return true; + } +} + +static int tensor_sec_update_bits(void *ctx, unsigned int reg, + unsigned int mask, unsigned int val) +{ + + if (!tensor_is_atomic(reg)) return tensor_sec_reg_rmw(ctx, reg, mask, val); return tensor_set_bits_atomic(ctx, reg, val, mask); diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index aa840ed043e1..f411c176536d 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -657,4 +657,8 @@ #define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268) #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) +/* For Tensor GS101 */ +#define GS101_SYSIP_DAT0 (0x810) +#define GS101_SYSTEM_CONFIGURATION (0x3A00) + #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */