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[128.178.122.21]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256af3f14csm204464925e9.6.2024.07.02.08.27.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 08:27:59 -0700 (PDT) From: Zheyu Ma To: Peter Maydell , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Paolo Bonzini Cc: Zheyu Ma , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2] hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate() Date: Tue, 2 Jul 2024 17:27:50 +0200 Message-Id: <20240702152750.3017426-1-zheyuma97@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=zheyuma97@gmail.com; helo=mail-lf1-x12a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In pl011_get_baudrate(), when we calculate the baudrate we can accidentally divide by zero. This happens because although (as the specification requires) we treat UARTIBRD = 0 as invalid, we aren't correctly limiting UARTIBRD and UARTFBRD values to the 16-bit and 6-bit ranges the hardware allows, and so some non-zero values of UARTIBRD can result in a zero divisor. Enforce the correct register field widths on guest writes and on inbound migration to avoid the division by zero. ASAN log: ==2973125==ERROR: AddressSanitizer: FPE on unknown address 0x55f72629b348 (pc 0x55f72629b348 bp 0x7fffa24d0e00 sp 0x7fffa24d0d60 T0) #0 0x55f72629b348 in pl011_get_baudrate hw/char/pl011.c:255:17 #1 0x55f726298d94 in pl011_trace_baudrate_change hw/char/pl011.c:260:33 #2 0x55f726296fc8 in pl011_write hw/char/pl011.c:378:9 Reproducer: cat << EOF | qemu-system-aarch64 -display \ none -machine accel=qtest, -m 512M -machine realview-pb-a8 -qtest stdio writeq 0x1000b024 0xf8000000 EOF Signed-off-by: Zheyu Ma --- Changes in v2: - Enforce the correct register field widths on writes to both UARTIBRD and UARTFBRD registers. - Mask UARTIBRD to 16 bits and UARTFBRD to 6 bits in the pl011_post_load function to prevent division by zero during inbound migration. --- hw/char/pl011.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 8753b84a84..ba5f7cfbda 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -374,11 +374,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->ilpr = value; break; case 9: /* UARTIBRD */ - s->ibrd = value; + s->ibrd = value & 0xffff; pl011_trace_baudrate_change(s); break; case 10: /* UARTFBRD */ - s->fbrd = value; + s->fbrd = value & 0x3f; pl011_trace_baudrate_change(s); break; case 11: /* UARTLCR_H */ @@ -531,6 +531,9 @@ static int pl011_post_load(void *opaque, int version_id) s->read_pos = 0; } + s->ibrd &= 0xffff; + s->fbrd &= 0x3f; + return 0; }