From patchwork Wed Jul 3 09:56:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720541 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74A21523A; Wed, 3 Jul 2024 02:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972754; cv=none; b=eqr+FeXedqotXeEerrpKvqT23dQ1Z54sG5/U6+m/ko47WMIs+3x+lXpitxHn/6tDX9PlplPCWlHRrz5wXuRIF9fwE9hfFmfTFf93RMZdf2aFnFp+7o5XK3zhVxE041DjfbYQKUANnckt1YIBUFkFVx/GCwDo/X1j7uBD/r8MLZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972754; c=relaxed/simple; bh=+M4vonICc0ZyeTSp/xqG/2je7Rme8lCHPlZ6Y/9HccU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d+Y386IjFyeJw1AwiDUnCt+66wrOJzEEGMAFMWBhy2mEaXqaEVbITQ+aD7XV5vyoWNCrou0Xx7nLc4mweTeTzf3WpTtL2YF6BvflO4gVS9C3nnomM7t2rCUsBhm+2y9dUWE3ON7Tp8nUeb6G0welLgNEwbpODiQskArbELN+bOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jIFIDyPh; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jIFIDyPh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972752; x=1751508752; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+M4vonICc0ZyeTSp/xqG/2je7Rme8lCHPlZ6Y/9HccU=; b=jIFIDyPhzEbHcuYYNEJl0T3ifIJ63j+cJEV/HgP3G5gtM61nkdcbsaRQ OvYEFNLi5HMSujDUYmRmdmPm9+gpvzei2xCeTujZ9DhaBTOGMdiz7AXw1 3sCz+TTKBiJ+SN0tLWqngesd35kwQ/YjyKMjEhgF4i04WequRlTFcfqpi 5ln9gLzraBQTEZU2fGmg8qqbiaGiynmBgJ1r1n8ya7MNISQbLxinUUiSn xmWBc1yx/O1fJhy14OHIdqhwMlSMzs1mwZpsRjKJWuMsFTHmwF7/FiM4X bzLEGo2amTRejYwHH3dtUZUc+K2xcMHY+/B/ggCoBbkUlU1H9tsVT5FjA A==; X-CSE-ConnectionGUID: 3XX55UmdS9C6eVxRSyBYrg== X-CSE-MsgGUID: X7xPt3hrRAukM/oi5wNYDQ== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17310938" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17310938" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:32 -0700 X-CSE-ConnectionGUID: D3TLjYn4Trit92MbBgXieA== X-CSE-MsgGUID: oYgzusVBQM65mVobeEPraQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148510" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:29 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 01/18] x86: pmu: Remove duplicate code in pmu_init() Date: Wed, 3 Jul 2024 09:56:55 +0000 Message-Id: <20240703095712.64202-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiong Zhang There are totally same code in pmu_init() helper, remove the duplicate code. Reviewed-by: Jim Mattson Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi --- lib/x86/pmu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c index 0f2afd65..d06e9455 100644 --- a/lib/x86/pmu.c +++ b/lib/x86/pmu.c @@ -16,11 +16,6 @@ void pmu_init(void) pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; } - if (pmu.version > 1) { - pmu.nr_fixed_counters = cpuid_10.d & 0x1f; - pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; - } - pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; From patchwork Wed Jul 3 09:56:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720543 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1804BE65; Wed, 3 Jul 2024 02:12:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972756; cv=none; b=tAqVJxP1KURuj6kQ+FnPo+iOFLwk5PJ1Ff2s5sHhcibFOk4DNRnx2geSeOspnUnd8KORe6AlXutth0cPRhrgKoLoxkuKUC9CMSB0Wm7zNgzOyHIimq3+ym32BvYXWDoO/+UMq+wIGtsEuMTFknZU89ZC/8ucfaQrNowylNtGPtw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972756; c=relaxed/simple; bh=UBSN3tAHv7Ks50wCX/Fi8DfPkqAzLtxONkTJalnh9Eo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DGri5EHt+WZA6WZTIerD0VJSL55ckSaqT8ckv0pla25i/R4y4l3R/HJlGBjMExgooTMG63QG3VYnVkd+AVSd5Nm/FDScVCwiMjqIBayYn6fcuku+Ka+GBcqA3fCsOcHK3MmSrZRkULthDBRqsCgSoNGZn/SV55ipl1uePOPQ9Sw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NxbsfYUN; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NxbsfYUN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972754; x=1751508754; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UBSN3tAHv7Ks50wCX/Fi8DfPkqAzLtxONkTJalnh9Eo=; b=NxbsfYUNobK/qETqFkQOmAtd518Enskv+UnB9ieg/Sd9LbB1lCGZya7g 0G/Q/rHzEf3lTl7wrye6pWg58f0V6RpfBVeT1TpkoxFPHHkxzSPBacnWc yx35e4ImKw9gwQ73bU4fNAKWnVx5uU2rlB2+xqYq9Gks+Zt4lqYfKV6U9 QdjHvdyfr+TP9pF0AHCiM8mUCHTQgXF9yId8KHgQjgx8I/N9zIg5yu399 /KQXPeWQx/x5CL4rG0qs517Iz0QQeDjtZHuS/upRvau1g9LpGVcqNydmA k2JLy9CrKLordyPLg4tqo3CaPRq4iOk4v5A50t3Ii7xVhZIWmtWBHtQm9 w==; X-CSE-ConnectionGUID: SKP3bhXMQT+c+PqUmsz6hg== X-CSE-MsgGUID: IoXSXtarTVCBkYM4NuAH8g== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17310947" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17310947" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:34 -0700 X-CSE-ConnectionGUID: yHfTQ/H9S8mDC5ZLKvpEmg== X-CSE-MsgGUID: I8UY/wLqQj6Oyb42x2KIxg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148521" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:32 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 02/18] x86: pmu: Remove blank line and redundant space Date: Wed, 3 Jul 2024 09:56:56 +0000 Message-Id: <20240703095712.64202-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 code style changes. Reviewed-by: Mingwei Zhang Signed-off-by: Dapeng Mi --- x86/pmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index ce9abbe1..865dbe67 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -205,8 +205,7 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { // printf("%d <= %ld <= %d\n", e->min, count, e->max); - return count >= e->min && count <= e->max; - + return count >= e->min && count <= e->max; } static bool verify_counter(pmu_counter_t *cnt) From patchwork Wed Jul 3 09:56:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720544 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C09717552; Wed, 3 Jul 2024 02:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972759; cv=none; b=K2q0koUBZ2+sQJaakDHz6wb+Sx+LLfcy7MspgI/tSdUhjoW31weiaTS5T+7q/eVrY2SGBDQQBUmTkxEyVN+oe0eRhZgI9Wa1u9Wlqkum30XPcoWpnrRoAa6ASzj7x3GuYqZ4mdw0ArGx0Q6z5wznTVzpNXoCIOXRQW60zxlG7Os= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972759; c=relaxed/simple; bh=KhG3sJ5luiiC8MFnE8cG6eZUNJPJ5V6DemW66c/WrE0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ni6GUuZDNUpfLfAG+quYGcTAq8QEkeqc7oexpiG3pde8BZCH4AGdxtjj307OWgulHsniGzwW5CBV4JB1RLrNSPlPxSLsGOkC9VDR7+ZyvIbnWNtjjJ32j2Pn1X/WCADJd3L/PkvuTnoHchitKdW1xobryIQuUKH6R+v98Jz8LZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LiXRxKNz; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LiXRxKNz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972757; x=1751508757; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KhG3sJ5luiiC8MFnE8cG6eZUNJPJ5V6DemW66c/WrE0=; b=LiXRxKNzlrVwKuv8e5CRG9wi7D30ONh34ajd5+Y4anqIsHXHC/Mw2iTB K1FT42ofNAbsmjyF2LnRbzgXLIUvya/+zMrrHsV2mMMcqMfmAQhfKepz4 cjU2DIchmQHoDZfrP2YDuWMPFyEKIIiQTwVaNc3FfnAgKH0DNdnkX2JrW E5wR8LACfrct15Pk4RAL0pDRlQgXYgZXDTF56tYXbK/bBjImpIxLpBa1m I5m7s3CjYuzX8JWWQBePaY9A6hs9707O0xldg2xYW/JhIrdDxKkU0uWFj o1m5NWrinzpviarQFNcevEXVxWOUBAadeulTURObKT3Rx8YVDCiS+2iKq w==; X-CSE-ConnectionGUID: 01Dq6B5qSzGP/Y7jHInvsA== X-CSE-MsgGUID: yXzm0mx5R8uTkIfhTpzCuQ== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17310959" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17310959" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:37 -0700 X-CSE-ConnectionGUID: CYW1qWbHR6+ERb9dcgelBQ== X-CSE-MsgGUID: GAK1yrreSKSxOSPKwIjinQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148535" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:34 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 03/18] x86: pmu: Refine fixed_events[] names Date: Wed, 3 Jul 2024 09:56:57 +0000 Message-Id: <20240703095712.64202-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In SDM the fixed counter is numbered from 0 but currently the fixed_events names are numbered from 1. It would cause confusion for users. So Change the fixed_events[] names to number from 0 as well and keep identical with SDM. Reviewed-by: Mingwei Zhang Signed-off-by: Dapeng Mi --- x86/pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 865dbe67..60db8bdf 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -45,9 +45,9 @@ struct pmu_event { {"branches", 0x00c2, 1*N, 1.1*N}, {"branch misses", 0x00c3, 0, 0.1*N}, }, fixed_events[] = { - {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, - {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, - {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} + {"fixed 0", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, + {"fixed 1", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, + {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} }; char *buf; From patchwork Wed Jul 3 09:56:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720545 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39E98182C3; Wed, 3 Jul 2024 02:12:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972761; cv=none; b=GBxIYJjuaaB+6990fN3vrjqQnjQl3GGy/Yq2q1FU70dGa42looxwxEw5X64d7GUPurSPBMO/sBNrgrb23heuDbJR1JDtqUu+FCBCxBl9uAk7zq/3riOKTdSdBrAe1xpRAfyh2GvKviJ3moNAYmq8fEHsDUIYxsXkwC+fTlkQZ5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972761; c=relaxed/simple; bh=TFH87E5BhpwdqBCfxEk/wJnJqhSK4EU8CSnk++BqOsA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jDwJiaohh466qbLf8mgfvyK9O6F7Zs10Cyqi0s6W7BNPDvSTwgEA/T42IWMY6heTSlIp8lW9BS4e6UaTvQI1jUdFlj5gdgvNViuNtJuS06SGAJcH94AEGP0n8oPhZCVJx02nFT4nZuLFcEYTEVFudKIoDfb3rUzWcmiQ3RmR5pI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Cdz2ZPhx; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cdz2ZPhx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972760; x=1751508760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TFH87E5BhpwdqBCfxEk/wJnJqhSK4EU8CSnk++BqOsA=; b=Cdz2ZPhxy/xulHUnrQoOv438+fX+qJ5DSQh36K/wige+VPxAxjj4Wpj5 u5UnC1EyK5uCtoXqnNuNWgWKr3oYbZLgux/3nBE8Bu2u5J0t2jXcD+SP8 ljjFGxLjxFcgaJuyr3aHwWv08/3YzRGpXtSak87IQvW7FxAQBkptRqEYh qZIwnmn3a0KiJBGi55RaNriVhOvUmqUG7zzHPqazq+OlD4yYMXkMl7o/z k46IyrBv3pEPnjCOOpWk0r2M8iHqtKoAzKyPoDFnZFrF6p93Xvx41awsk F1W4UqgkkCra5/t5R9ILJAdAiq0F8CIJd6HrrB8vKoZ5TcyCdEWmtpL/1 A==; X-CSE-ConnectionGUID: VZxpr5cHTQikydoDcHYHmw== X-CSE-MsgGUID: 775jBBpGSMqcVt20kNUwpQ== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17310970" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17310970" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:40 -0700 X-CSE-ConnectionGUID: DEAJOVxWRjmWyc5EXNRHLw== X-CSE-MsgGUID: 03wZetivQ/a7OoeE/URnhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148548" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:37 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 04/18] x86: pmu: Fix the issue that pmu_counter_t.config crosses cache line Date: Wed, 3 Jul 2024 09:56:58 +0000 Message-Id: <20240703095712.64202-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When running pmu test on SPR, the following #GP fault is reported. Unhandled exception 13 #GP at ip 000000000040771f error_code=0000 rflags=00010046 cs=00000008 rax=00000000004031ad rcx=0000000000000186 rdx=0000000000000000 rbx=00000000005142f0 rbp=0000000000514260 rsi=0000000000000020 rdi=0000000000000340 r8=0000000000513a65 r9=00000000000003f8 r10=000000000000000d r11=00000000ffffffff r12=000000000043003c r13=0000000000514450 r14=000000000000000b r15=0000000000000001 cr0=0000000080010011 cr2=0000000000000000 cr3=0000000001007000 cr4=0000000000000020 cr8=0000000000000000 STACK: @40771f 40040e 400976 400aef 40148d 401da9 4001ad FAIL pmu It looks EVENTSEL0 MSR (0x186) is written a invalid value (0x4031ad) and cause a #GP. Further investigation shows the #GP is caused by below code in __start_event(). rmsr(MSR_GP_EVENT_SELECTx(event_to_global_idx(evt)), evt->config | EVNTSEL_EN); The evt->config is correctly initialized but seems corrupted before writing to MSR. The original pmu_counter_t layout looks as below. typedef struct { uint32_t ctr; uint64_t config; uint64_t count; int idx; } pmu_counter_t; Obviously the config filed crosses two cache lines. When the two cache lines are not updated simultaneously, the config value is corrupted. Adjust pmu_counter_t fields order and ensure config field is cache-line aligned. Signeduoff-by: Dapeng Mi --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 60db8bdf..a0268db8 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -21,9 +21,9 @@ typedef struct { uint32_t ctr; + uint32_t idx; uint64_t config; uint64_t count; - int idx; } pmu_counter_t; struct pmu_event { From patchwork Wed Jul 3 09:56:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720546 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39ADF1CAA9; Wed, 3 Jul 2024 02:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972764; cv=none; b=fiXO94iszDmy2/imN8Xw2ZnddeqUAybxvdfGeyEk1GyQHnsiKGJOtZMtTTgx9HllG2JHW1B8rUow+hPzqzggCek7q9TuqJYjpuc185O5nLU3uoz2ohVoyMAg2qg1NbdMYE+l18RgxUio82cYB7wcFjYlX9VOa8hK3BV2hU/v3PA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972764; c=relaxed/simple; bh=c/FKtCmCvkZd0M4TkpSHqVExn/0016+qbGWLpWK/BiA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iB7pwfifnmNlt14HmJbVR66bL7X5NeSUEIAM/Cz1JkxdRGsxHPR/+G9R9ePg9Dpk14dfjrcyFawupsz/Qk9RLwZZTlRS1x0bGWzaazupl/IBEfrGTyuHRE7grSj+vP8bYA1IEvu5zchfPWC4MX8TkWPzMiJYLhx1BOk5tqsTP10= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Bdhztw1+; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Bdhztw1+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972763; x=1751508763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c/FKtCmCvkZd0M4TkpSHqVExn/0016+qbGWLpWK/BiA=; b=Bdhztw1+sjb63A5OC28Nqz/w+cu++imNp9JtVFQuGLKcFiJtjQI9E1OF H13k0urRoETZyWvD+ggE2RcDwEQFfcCdG17Lr0z/HDGY3TFTfZwN5FvpJ vut6AhqGumfwxMx6SAAdjLc7k+N/b/HGL/v+BQBVIOxm//c+tlJ7YEYts Jnb87C1peSvfku0ZYK1e74F7nKpZ62FbiknrjM2GzpX5bDvKZ/xAnb8An +BaWcEARGd3v54nmBVPmy4XcWsnLmJK/1TC0zb0IOZbGNZ4Q62Mff7e5g Mi2Pm5md+cDFH9UUEW1pTWyRAHPiYXf9/cKaTKQMNGUsbV05gzDs3pX8C w==; X-CSE-ConnectionGUID: NZn4XQYBSJGKo+dZtUrZsA== X-CSE-MsgGUID: w3rQZzaBTuOyHbkMOWaUZw== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17310983" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17310983" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:43 -0700 X-CSE-ConnectionGUID: OT7RmQJQT+KMwQiIVrEg6w== X-CSE-MsgGUID: 7CRYMr5PTiuB0S2/Ys8y8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148567" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:40 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 05/18] x86: pmu: Enlarge cnt[] length to 48 in check_counters_many() Date: Wed, 3 Jul 2024 09:56:59 +0000 Message-Id: <20240703095712.64202-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Considering there are already 8 GP counters and 4 fixed counters on latest Intel processors, like Sapphire Rapids. The original cnt[] array length 10 is definitely not enough to cover all supported PMU counters on these new processors even through currently KVM only supports 3 fixed counters at most. This would cause out of bound memory access and may trigger false alarm on PMU counter validation It's probably more and more GP and fixed counters are introduced in the future and then directly extends the cnt[] array length to 48 once and for all. Base on the layout of IA32_PERF_GLOBAL_CTRL and IA32_PERF_GLOBAL_STATUS, 48 looks enough in near feature. Reviewed-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index a0268db8..b4de2680 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -255,7 +255,7 @@ static void check_fixed_counters(void) static void check_counters_many(void) { - pmu_counter_t cnt[10]; + pmu_counter_t cnt[48]; int i, n; for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) { From patchwork Wed Jul 3 09:57:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720547 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C175122315; Wed, 3 Jul 2024 02:12:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972767; cv=none; b=RKBny2ZBdweZwGbq457oOvfII91nJolUortFQslxqLgTqZmA+dl+D47H0W5RW5ZnXgurymWsOjtrlRZ3mp0jgJK5lYu0VsZkP/gE4eMdChYB0xog2hcoO0HWgSPj5Zux05FTw26cJL9O0ihK1EGEfI1hjz/x9PbmP9U9Hf+r0sA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972767; c=relaxed/simple; bh=J8M0I4LP/AgsGW+cohnqQuEL47InULKRmzAJ+kd1JvY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JviXOVAyQ/mN90sdDX87S7TXa57RlmLJNcPPGiDiUug9vjHlb3t9PsMwN3FFbX9k+Ba4SzAKNJ0sXPC65ZQVtdj+ILQrxcvdPISYbXeGaUnfy3cUJHRt5x+e2qti/ON5EvZsClqcGhjZz29Pohq1khJw0s1iz1tZds+cMoMlBc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L5pJodwu; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L5pJodwu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972766; x=1751508766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J8M0I4LP/AgsGW+cohnqQuEL47InULKRmzAJ+kd1JvY=; b=L5pJodwukgMcpTASDKHLZvJpm+UxRqMLXmuepoZNfd0EmmOJu88QbzNG iuhbbsDjDRYWK5L2JmafaoT/XnrsHqEK7Y0O9JUgbbqKeeeOptSDtOkmx 46Z1GE7aoNOtBO/Zk8tiqrSZEZ2/5TFDteE8hu8+mE1ec3xr3fno4rvQO neYfZnLKOF2gPaQTVVJrAFRJOiBAkUg4aBCIBA3e2ON1eSLtgP6I2UhvV y/GshLjPOso0lh483/uRr/BYpddmGwQt6msRwmgzgY+ze8MWsoh2HtKIE RpHxWIe6YIaLOam9sbrZvt9nN+yUrQfoYjAmIIrxKYcobJpyPXKm3/X7Z A==; X-CSE-ConnectionGUID: 8179dXqFR8CmjZYB0M3nlA== X-CSE-MsgGUID: JjW995yLSKSriVFn6v+z8A== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17310993" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17310993" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:45 -0700 X-CSE-ConnectionGUID: yvoNCg0JQvKFUst1oKMJ+g== X-CSE-MsgGUID: CaGycblnS9CWHkiZ+dvlFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148578" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:43 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 06/18] x86: pmu: Add asserts to warn inconsistent fixed events and counters Date: Wed, 3 Jul 2024 09:57:00 +0000 Message-Id: <20240703095712.64202-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Current PMU code deosn't check whether PMU fixed counter number is larger than pre-defined fixed events. If so, it would cause memory access out of range. So add assert to warn this invalid case. Reviewed-by: Mingwei Zhang Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index b4de2680..3e0bf3a2 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -113,8 +113,12 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) for (i = 0; i < gp_events_size; i++) if (gp_events[i].unit_sel == (cnt->config & 0xffff)) return &gp_events[i]; - } else - return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; + } else { + unsigned int idx = cnt->ctr - MSR_CORE_PERF_FIXED_CTR0; + + assert(idx < ARRAY_SIZE(fixed_events)); + return &fixed_events[idx]; + } return (void*)0; } @@ -740,6 +744,8 @@ int main(int ac, char **av) printf("Fixed counters: %d\n", pmu.nr_fixed_counters); printf("Fixed counter width: %d\n", pmu.fixed_counter_width); + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); + apic_write(APIC_LVTPC, PMI_VECTOR); check_counters(); From patchwork Wed Jul 3 09:57:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720548 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 928AA28370; Wed, 3 Jul 2024 02:12:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972770; cv=none; b=Otek2RQ/KYSYEj+ljbcFuJmg7tfu0uic2SErPK+olpg8iU4ZgGMRqJEFq13qmV07amhiuGST+CjJBCgEIK7osz4T05JhMF/fbhtuMF74d5Y495+Z/GRlHekD23JbyduOfUmx3mNYnwAhYuGv4I/vI/LBiILZ2lt/sOsbqXwpow0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972770; c=relaxed/simple; bh=NOKncSb0XiiYQO6c+6ANmKchgy105hDTLQorIKO0dWY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZozGjgDa4ukhVlGaXQq78aUY9LVHF4CuSUNShDZ4iThkWtLOZ81/taGz+HN2UxRI2ld+nKvgikeUPxB9xCw12rML252Ebu5nJK0exZabNd3/AqzXrKUCDnuA6/f0kbtR6dlnVfndQnI1mOYvdl0m5CCbaDU6YNdq/nKz/4EGpv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cCROZzbT; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cCROZzbT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972768; x=1751508768; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NOKncSb0XiiYQO6c+6ANmKchgy105hDTLQorIKO0dWY=; b=cCROZzbT6C+7WvwBnpqSSxuU7ckURwTJpHAMXXJH3vOkEFaaiCp/ektB qMOk6RXMjdkNRyfm0AtJj3NDbqnD5wRVIzzTD9Gx0J3w8ySP2eznG6c91 cs7DkaQcPbbEgXXqJA6BHRfLEiK9Fbp0TPLYqM0WfLdtV8lzMtnn4guCq bB9gvjGVw90uxib63dkS2iT081qEAasaX/f1zoTYSazxnE0F9qxaswewA bmn+e9eDC83IVHR8qYnHnBGA3qPY+0LsfxAzNyJapZPS0Vr9veDMQKYi6 LUgFoPGLerhy520uBMTk1u0kTWEox0NsL30tUqFj/+Eu46RowB+jyV9jn A==; X-CSE-ConnectionGUID: rYOWfXKyS2m4q9tEcWiMow== X-CSE-MsgGUID: IKifbUKtRdCUQc8W1xnvYw== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17311009" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17311009" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:48 -0700 X-CSE-ConnectionGUID: hdp2MQQdTSiQXUV4CzPQjA== X-CSE-MsgGUID: Wkx7HKwMQkW8nfIR6ygDLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148587" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:46 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 07/18] x86: pmu: Fix cycles event validation failure Date: Wed, 3 Jul 2024 09:57:01 +0000 Message-Id: <20240703095712.64202-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When running pmu test on SPR, sometimes the following failure is reported. PMU version: 2 GP counters: 8 GP counter width: 48 Mask length: 8 Fixed counters: 3 Fixed counter width: 48 1000000 <= 55109398 <= 50000000 FAIL: Intel: core cycles-0 1000000 <= 18279571 <= 50000000 PASS: Intel: core cycles-1 1000000 <= 12238092 <= 50000000 PASS: Intel: core cycles-2 1000000 <= 7981727 <= 50000000 PASS: Intel: core cycles-3 1000000 <= 6984711 <= 50000000 PASS: Intel: core cycles-4 1000000 <= 6773673 <= 50000000 PASS: Intel: core cycles-5 1000000 <= 6697842 <= 50000000 PASS: Intel: core cycles-6 1000000 <= 6747947 <= 50000000 PASS: Intel: core cycles-7 The count of the "core cycles" on first counter would exceed the upper boundary and leads to a failure, and then the "core cycles" count would drop gradually and reach a stable state. That looks reasonable. The "core cycles" event is defined as the 1st event in xxx_gp_events[] array and it is always verified at first. when the program loop() is executed at the first time it needs to warm up the pipeline and cache, such as it has to wait for cache is filled. All these warm-up work leads to a quite large core cycles count which may exceeds the verification range. To avoid the false positive of cycles event caused by warm-up, explicitly introduce a warm-up state before really starting verification. Signed-off-by: Dapeng Mi --- x86/pmu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 3e0bf3a2..1e028579 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -593,11 +593,27 @@ static void check_tsx_cycles(void) report_prefix_pop(); } +static void warm_up(void) +{ + int i = 8; + + /* + * Since cycles event is always run as the first event, there would be + * a warm-up state to warm up the cache, it leads to the measured cycles + * value may exceed the pre-defined cycles upper boundary and cause + * false positive. To avoid this, introduce an warm-up state before + * the real verification. + */ + while (i--) + loop(); +} + static void check_counters(void) { if (is_fep_available()) check_emulated_instr(); + warm_up(); check_gp_counters(); check_fixed_counters(); check_rdpmc(); From patchwork Wed Jul 3 09:57:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720549 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6078F8F49; Wed, 3 Jul 2024 02:12:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972772; cv=none; b=pACiiorrhXMVEBKvIwm3H4R1+98c9bMZRkoNswoa1mUELIhiovWlO+bmBPn2Ha9VF7a2dyZ0yCKwRir1/3DQ9zcP8BPu5bqfKXGqxlOqEshfPjyoyCYv3Nsoq1IajYod+8qqBVckPNvpYLb3/bEsFlrqWVbeGCQMiI4b8cTaOJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972772; c=relaxed/simple; bh=9J4gTUwUn2cWSw1SNih0bGr/MeYBF/9jYecIo0DiWaY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WwF+nCKczeX+zkzCbLr3JY5aeDvtwth3rpQq2gCZuxapGry3JY4Sfu8R52yugxFQZu9dzG8GrEb8d9VErtzVwi1hQNIPdug7+DDQvnq03jvhO9ju5e3kRUWv/w0COaSEOltX2Gtd+CC2mevJundPo/hYa765WsWWuRSYo36n/AY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=F7U8Y1E4; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="F7U8Y1E4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972771; x=1751508771; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9J4gTUwUn2cWSw1SNih0bGr/MeYBF/9jYecIo0DiWaY=; b=F7U8Y1E4HwC9XUr5PUETD0VsNR9tVFRz87OYzSEuUKQA1qnYXR+Jecnt TfIxiuh6tWfUkDqfjPd1VLPa/khWC3X1xubHbJjTgaeOglQxWh2/d8liF Tjqis1sTIMNGJBg5fLzz9f+Ud4UijnGKgzdYpd/XMyvHL3Fwj+kJZ6TlM jRT7dieJVuUZsNLdqd5g8NDNR29hgN7z2RFMD/4tQf54jdWpf/EPaH51J 8xBgQvFdzPfoMilvLouM6Ym4GP9f0h2jN9Jk3zOlmf97oWtxdDbqGWzeq +3H7kkQ1kpptKU+kqEKXSYAVipCUp3czuSnbRpT194Y6iNXe9R647psk+ g==; X-CSE-ConnectionGUID: ZWvP1r+jTjC3oMwimzFz3w== X-CSE-MsgGUID: jRW6TcOtR2qqF/8yvCJHqA== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17311022" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17311022" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:12:51 -0700 X-CSE-ConnectionGUID: jfwGEheERveVJfdaAz3uwA== X-CSE-MsgGUID: 4M45Krs0S8uOe9oKdNXYrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148597" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:48 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 08/18] x86: pmu: Use macro to replace hard-coded branches event index Date: Wed, 3 Jul 2024 09:57:02 +0000 Message-Id: <20240703095712.64202-9-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently the branches event index is a hard-coded number. User could add new events and cause the branches event index changes in the future, but don't notice the hard-coded event index and forget to update the event index synchronously, then the issue comes. Thus, replace the hard-coded index to a macro. Signed-off-by: Dapeng Mi --- x86/pmu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 1e028579..d2138567 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -50,6 +50,22 @@ struct pmu_event { {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} }; +/* + * Events index in intel_gp_events[], ensure consistent with + * intel_gp_events[]. + */ +enum { + INTEL_BRANCHES_IDX = 5, +}; + +/* + * Events index in amd_gp_events[], ensure consistent with + * amd_gp_events[]. + */ +enum { + AMD_BRANCHES_IDX = 2, +}; + char *buf; static struct pmu_event *gp_events; @@ -483,7 +499,8 @@ static void check_emulated_instr(void) { uint64_t status, instr_start, brnch_start; uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1; - unsigned int branch_idx = pmu.is_intel ? 5 : 2; + unsigned int branch_idx = pmu.is_intel ? + INTEL_BRANCHES_IDX : AMD_BRANCHES_IDX; pmu_counter_t brnch_cnt = { .ctr = MSR_GP_COUNTERx(0), /* branch instructions */ From patchwork Wed Jul 3 09:57:03 2024 Content-Type: text/plain; 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Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index d2138567..b7de3b58 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -55,6 +55,7 @@ struct pmu_event { * intel_gp_events[]. */ enum { + INTEL_REF_CYCLES_IDX = 2, INTEL_BRANCHES_IDX = 5, }; @@ -699,7 +700,8 @@ static void set_ref_cycle_expectations(void) { pmu_counter_t cnt = { .ctr = MSR_IA32_PERFCTR0, - .config = EVNTSEL_OS | EVNTSEL_USR | intel_gp_events[2].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | + intel_gp_events[INTEL_REF_CYCLES_IDX].unit_sel, }; uint64_t tsc_delta; uint64_t t0, t1, t2, t3; @@ -735,8 +737,10 @@ static void set_ref_cycle_expectations(void) if (!tsc_delta) return; - intel_gp_events[2].min = (intel_gp_events[2].min * cnt.count) / tsc_delta; - intel_gp_events[2].max = (intel_gp_events[2].max * cnt.count) / tsc_delta; + intel_gp_events[INTEL_REF_CYCLES_IDX].min = + (intel_gp_events[INTEL_REF_CYCLES_IDX].min * cnt.count) / tsc_delta; + intel_gp_events[INTEL_REF_CYCLES_IDX].max = + (intel_gp_events[INTEL_REF_CYCLES_IDX].max * cnt.count) / tsc_delta; } static void check_invalid_rdpmc_gp(void) From patchwork Wed Jul 3 09:57:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720551 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D83E23C684; Wed, 3 Jul 2024 02:12:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972779; cv=none; b=NAH0dCfCEdLSUEoscYbKw9gY8I1+nhI+3TmNjJYmVa5PXksstYUdooDy6PLoFEoDeFB26N/LoCmShN5PJ9D0/pYSPFu6CRcF9myB8+1PYpzIoEu3yINXGuXZUJepqlx1WLHiY0qO80qURHQPPuLgJLtOQ+FP1oIZnOgbXWTABNQ= ARC-Message-Signature: i=1; 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d="scan'208";a="46148645" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:55 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 10/18] x86: pmu: Use macro to replace hard-coded instructions event index Date: Wed, 3 Jul 2024 09:57:04 +0000 Message-Id: <20240703095712.64202-11-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace hard-coded instruction event index with macro to avoid possible mismatch issue if new event is added in the future and cause instructions event index changed, but forget to update the hard-coded event index. Signed-off-by: Dapeng Mi --- x86/pmu.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index b7de3b58..31b49a74 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -55,6 +55,7 @@ struct pmu_event { * intel_gp_events[]. */ enum { + INTEL_INSTRUCTIONS_IDX = 1, INTEL_REF_CYCLES_IDX = 2, INTEL_BRANCHES_IDX = 5, }; @@ -64,6 +65,7 @@ enum { * amd_gp_events[]. */ enum { + AMD_INSTRUCTIONS_IDX = 1, AMD_BRANCHES_IDX = 2, }; @@ -319,11 +321,16 @@ static uint64_t measure_for_overflow(pmu_counter_t *cnt) static void check_counter_overflow(void) { - uint64_t overflow_preset; int i; + uint64_t overflow_preset; + int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; + pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | + gp_events[instruction_idx].unit_sel /* instructions */, }; overflow_preset = measure_for_overflow(&cnt); @@ -379,13 +386,18 @@ static void check_counter_overflow(void) static void check_gp_counter_cmask(void) { + int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; + pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | + gp_events[instruction_idx].unit_sel /* instructions */, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); measure_one(&cnt); - report(cnt.count < gp_events[1].min, "cmask"); + report(cnt.count < gp_events[instruction_idx].min, "cmask"); } static void do_rdpmc_fast(void *ptr) @@ -460,9 +472,14 @@ static void check_running_counter_wrmsr(void) { uint64_t status; uint64_t count; + unsigned int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; + pmu_counter_t evt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | + gp_events[instruction_idx].unit_sel, }; report_prefix_push("running counter wrmsr"); @@ -471,7 +488,7 @@ static void check_running_counter_wrmsr(void) loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); - report(evt.count < gp_events[1].min, "cntr"); + report(evt.count < gp_events[instruction_idx].min, "cntr"); /* clear status before overflow test */ if (this_cpu_has_perf_global_status()) @@ -502,6 +519,9 @@ static void check_emulated_instr(void) uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1; unsigned int branch_idx = pmu.is_intel ? INTEL_BRANCHES_IDX : AMD_BRANCHES_IDX; + unsigned int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; pmu_counter_t brnch_cnt = { .ctr = MSR_GP_COUNTERx(0), /* branch instructions */ @@ -510,7 +530,7 @@ static void check_emulated_instr(void) pmu_counter_t instr_cnt = { .ctr = MSR_GP_COUNTERx(1), /* instructions */ - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[instruction_idx].unit_sel, }; report_prefix_push("emulated instruction"); From patchwork Wed Jul 3 09:57:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720552 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCA7045945; Wed, 3 Jul 2024 02:13:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972783; cv=none; b=o9ckoxnUkeJ51yHYZ/MkUTouEJqnHwj2d0gkDX8ZPqFvTE4ZvT42v9dcEpXMQ3iH01OOyYXIHuDh8HBRMWKTpW91Oeq83B9n6ygcZsaebvCgSBXWO8H4ZM7X5ddiTkHcZf1C9sdLRWDpr143EfdlclRFaM7eUtSpPGNMSa6ixGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972783; c=relaxed/simple; bh=Zl1kZq1pxJSML3CbfbN+iyCEBOKjlxxYS2XjXy//qFo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mn0PUUmETkY2/41pZanXHvhKxhgluAn6IyDKulKSBeTa4flaxyDm2J2vy1mgFJA6t0fAxs03iuz9ngpdZnkI/qNxi+DWLtAcoq7NEyQ6W3GtclBAebbBeVhUf1HFA5Y9DvOOPvrbBYd6T3cD14snU/Gjvi8kKVg/CORncCxAQnc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OGLV37+T; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OGLV37+T" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972782; x=1751508782; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zl1kZq1pxJSML3CbfbN+iyCEBOKjlxxYS2XjXy//qFo=; b=OGLV37+TIbCuIFAtylwl5kRb4OxP+RN3P35tjF7vR7AI9Yx3Hc8y/TtB zd21bafRW/izAUFgzKigKJZ3RlXlju3O8e3u84S9JoZ3P03OPiHsN8aol yfCY9TXHJYZ5iy9U750IU4/7QjNIR2RfXYt2iOe3j/NYUeYENg0rUZ9M1 E33YwqruWb6lXMVRe+hirQxFafdfWEdsJ5Dbx9BkTz6xMTkJO6YOOwfLf kv3NV+RAqL984jwOgeXZ0/fQwnwIaJAQ/aZDl4WHQBmtaetZ7BS6Xaahv quceVf0hY4cddrAjY1IWULssR549xdBr05HImE79Xjv+l2XO1hK3Bie74 A==; X-CSE-ConnectionGUID: VJQKb2rtQTqHWkdLM0aUBg== X-CSE-MsgGUID: WS1cdR2GSWeogCmX8kp+5w== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17311077" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17311077" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:13:01 -0700 X-CSE-ConnectionGUID: K6hM714ZTYGI8vVaMt71uQ== X-CSE-MsgGUID: TRcay0+3Qge8775M72nq3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148669" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:12:58 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 11/18] x86: pmu: Enable and disable PMCs in loop() asm blob Date: Wed, 3 Jul 2024 09:57:05 +0000 Message-Id: <20240703095712.64202-12-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently enabling PMCs, executing loop() and disabling PMCs are divided 3 separated functions. So there could be other instructions executed between enabling PMCS and running loop() or running loop() and disabling PMCs, e.g. if there are multiple counters enabled in measure_many() function, the instructions which enabling the 2nd and more counters would be counted in by the 1st counter. So current implementation can only verify the correctness of count by an rough range rather than a precise count even for instructions and branches events. Strictly speaking, this verification is meaningless as the test could still pass even though KVM vPMU has something wrong and reports an incorrect instructions or branches count which is in the rough range. Thus, move the PMCs enabling and disabling into the loop() asm blob and ensure only the loop asm instructions would be counted, then the instructions or branches events can be verified with an precise count instead of an rough range. Signed-off-by: Dapeng Mi --- x86/pmu.c | 80 ++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 65 insertions(+), 15 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 31b49a74..d005e376 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,6 +19,15 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 +#define LOOP_ASM(_wrmsr) \ + _wrmsr "\n\t" \ + "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ + "1: mov (%1), %2; add $64, %1;\n\t" \ + "nop; nop; nop; nop; nop; nop; nop;\n\t" \ + "loop 1b;\n\t" \ + "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ + _wrmsr "\n\t" + typedef struct { uint32_t ctr; uint32_t idx; @@ -74,13 +83,43 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; -static inline void loop(void) + +static inline void __loop(void) +{ + unsigned long tmp, tmp2, tmp3; + + asm volatile(LOOP_ASM("nop") + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) + : "0"(N), "1"(buf)); +} + +/* + * Enable and disable counters in a whole asm blob to ensure + * no other instructions are counted in the window between + * counters enabling and really LOOP_ASM code executing. + * Thus counters can verify instructions and branches events + * against precise counts instead of a rough valid count range. + */ +static inline void __precise_loop(u64 cntrs) { unsigned long tmp, tmp2, tmp3; + unsigned int global_ctl = pmu.msr_global_ctl; + u32 eax = cntrs & (BIT_ULL(32) - 1); + u32 edx = cntrs >> 32; - asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); + asm volatile(LOOP_ASM("wrmsr") + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) + : "a"(eax), "d"(edx), "c"(global_ctl), + "0"(N), "1"(buf) + : "edi"); +} +static inline void loop(u64 cntrs) +{ + if (!this_cpu_has_perf_global_ctrl()) + __loop(); + else + __precise_loop(cntrs); } volatile uint64_t irq_received; @@ -180,18 +219,17 @@ static void __start_event(pmu_counter_t *evt, uint64_t count) ctrl = (ctrl & ~(0xf << shift)) | (usrospmi << shift); wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); } - global_enable(evt); apic_write(APIC_LVTPC, PMI_VECTOR); } static void start_event(pmu_counter_t *evt) { __start_event(evt, 0); + global_enable(evt); } -static void stop_event(pmu_counter_t *evt) +static void __stop_event(pmu_counter_t *evt) { - global_disable(evt); if (is_gp(evt)) { wrmsr(MSR_GP_EVENT_SELECTx(event_to_global_idx(evt)), evt->config & ~EVNTSEL_EN); @@ -203,14 +241,24 @@ static void stop_event(pmu_counter_t *evt) evt->count = rdmsr(evt->ctr); } +static void stop_event(pmu_counter_t *evt) +{ + global_disable(evt); + __stop_event(evt); +} + static noinline void measure_many(pmu_counter_t *evt, int count) { int i; + u64 cntrs = 0; + + for (i = 0; i < count; i++) { + __start_event(&evt[i], 0); + cntrs |= BIT_ULL(event_to_global_idx(&evt[i])); + } + loop(cntrs); for (i = 0; i < count; i++) - start_event(&evt[i]); - loop(); - for (i = 0; i < count; i++) - stop_event(&evt[i]); + __stop_event(&evt[i]); } static void measure_one(pmu_counter_t *evt) @@ -220,9 +268,11 @@ static void measure_one(pmu_counter_t *evt) static noinline void __measure(pmu_counter_t *evt, uint64_t count) { + u64 cntrs = BIT_ULL(event_to_global_idx(evt)); + __start_event(evt, count); - loop(); - stop_event(evt); + loop(cntrs); + __stop_event(evt); } static bool verify_event(uint64_t count, struct pmu_event *e) @@ -485,7 +535,7 @@ static void check_running_counter_wrmsr(void) report_prefix_push("running counter wrmsr"); start_event(&evt); - loop(); + __loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); report(evt.count < gp_events[instruction_idx].min, "cntr"); @@ -502,7 +552,7 @@ static void check_running_counter_wrmsr(void) wrmsr(MSR_GP_COUNTERx(0), count); - loop(); + __loop(); stop_event(&evt); if (this_cpu_has_perf_global_status()) { @@ -643,7 +693,7 @@ static void warm_up(void) * the real verification. */ while (i--) - loop(); + loop(0); } static void check_counters(void) From patchwork Wed Jul 3 09:57:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720553 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BB6A481B3; Wed, 3 Jul 2024 02:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; 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d="scan'208";a="17311089" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:13:04 -0700 X-CSE-ConnectionGUID: QMzN9DxzTGKXENbG6qNapg== X-CSE-MsgGUID: SS1jDho5Q6qIaiubxy2MBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148695" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:13:01 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 12/18] x86: pmu: Improve instruction and branches events verification Date: Wed, 3 Jul 2024 09:57:06 +0000 Message-Id: <20240703095712.64202-13-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are moved in __precise_count_loop(). Thus, instructions and branches events can be verified against a precise count instead of a rough range. Signed-off-by: Dapeng Mi --- x86/pmu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index d005e376..ffb7b4a4 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,6 +19,11 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 + +/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ +#define EXTRA_INSTRNS (3 + 3) +#define LOOP_INSTRNS (N * 10 + EXTRA_INSTRNS) +#define LOOP_BRANCHES (N) #define LOOP_ASM(_wrmsr) \ _wrmsr "\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ @@ -122,6 +127,24 @@ static inline void loop(u64 cntrs) __precise_loop(cntrs); } +static void adjust_events_range(struct pmu_event *gp_events, + int instruction_idx, int branch_idx) +{ + /* + * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are + * moved in __precise_loop(). Thus, instructions and branches events + * can be verified against a precise count instead of a rough range. + */ + if (this_cpu_has_perf_global_ctrl()) { + /* instructions event */ + gp_events[instruction_idx].min = LOOP_INSTRNS; + gp_events[instruction_idx].max = LOOP_INSTRNS; + /* branches event */ + gp_events[branch_idx].min = LOOP_BRANCHES; + gp_events[branch_idx].max = LOOP_BRANCHES; + } +} + volatile uint64_t irq_received; static void cnt_overflow(isr_regs_t *regs) @@ -823,6 +846,9 @@ static void check_invalid_rdpmc_gp(void) int main(int ac, char **av) { + int instruction_idx; + int branch_idx; + setup_vm(); handle_irq(PMI_VECTOR, cnt_overflow); buf = malloc(N*64); @@ -836,13 +862,18 @@ int main(int ac, char **av) } gp_events = (struct pmu_event *)intel_gp_events; gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); + instruction_idx = INTEL_INSTRUCTIONS_IDX; + branch_idx = INTEL_BRANCHES_IDX; report_prefix_push("Intel"); set_ref_cycle_expectations(); } else { gp_events_size = sizeof(amd_gp_events)/sizeof(amd_gp_events[0]); gp_events = (struct pmu_event *)amd_gp_events; + instruction_idx = AMD_INSTRUCTIONS_IDX; + branch_idx = AMD_BRANCHES_IDX; report_prefix_push("AMD"); } + adjust_events_range(gp_events, instruction_idx, branch_idx); printf("PMU version: %d\n", pmu.version); printf("GP counters: %d\n", pmu.nr_gp_counters); From patchwork Wed Jul 3 09:57:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720554 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7055F4AEE7; Wed, 3 Jul 2024 02:13:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972789; cv=none; b=IBBKas+lbjS6o/fu8MpKqM0JaI2yRSg3RJnOTd5RoMXcTDEERpkBgZARXj1luDxspxYNPcEjFqIoP+aes0JTCn7WwBloNwRakFzGS5+Z3dOy/wgZi2fFOaghQN6IBeV4ud0iEf3DNk1YiihrbfU6549jNY+awuW/dcfwN4iCBQw= ARC-Message-Signature: i=1; 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d="scan'208";a="46148748" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:13:04 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 13/18] x86: pmu: Improve LLC misses event verification Date: Wed, 3 Jul 2024 09:57:07 +0000 Message-Id: <20240703095712.64202-14-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When running pmu test on SPR, sometimes the following failure is reported. 1 <= 0 <= 1000000 FAIL: Intel: llc misses-4 Currently The LLC misses occurring only depends on probability. It's possible that there is no LLC misses happened in the whole loop(), especially along with processors have larger and larger cache size just like what we observed on SPR. Thus, add clflush instruction into the loop() asm blob and ensure once LLC miss is triggered at least. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index ffb7b4a4..799d8d5c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -20,19 +20,30 @@ #define EXPECTED_BRNCH 5 -/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ -#define EXTRA_INSTRNS (3 + 3) +/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ +#define EXTRA_INSTRNS (3 + 3 + 2) #define LOOP_INSTRNS (N * 10 + EXTRA_INSTRNS) #define LOOP_BRANCHES (N) -#define LOOP_ASM(_wrmsr) \ +#define LOOP_ASM(_wrmsr, _clflush) \ _wrmsr "\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ + _clflush "\n\t" \ + "mfence;\n\t" \ "1: mov (%1), %2; add $64, %1;\n\t" \ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ _wrmsr "\n\t" +#define _loop_asm(_wrmsr, _clflush) \ +do { \ + asm volatile(LOOP_ASM(_wrmsr, _clflush) \ + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ + : "a"(eax), "d"(edx), "c"(global_ctl), \ + "0"(N), "1"(buf) \ + : "edi"); \ +} while (0) + typedef struct { uint32_t ctr; uint32_t idx; @@ -88,14 +99,17 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; - static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; + u32 global_ctl = 0; + u32 eax = 0; + u32 edx = 0; - asm volatile(LOOP_ASM("nop") - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) - : "0"(N), "1"(buf)); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("nop", "clflush (%1)"); + else + _loop_asm("nop", "nop"); } /* @@ -108,15 +122,14 @@ static inline void __loop(void) static inline void __precise_loop(u64 cntrs) { unsigned long tmp, tmp2, tmp3; - unsigned int global_ctl = pmu.msr_global_ctl; + u32 global_ctl = pmu.msr_global_ctl; u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - asm volatile(LOOP_ASM("wrmsr") - : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) - : "a"(eax), "d"(edx), "c"(global_ctl), - "0"(N), "1"(buf) - : "edi"); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("wrmsr", "clflush (%1)"); + else + _loop_asm("wrmsr", "nop"); } static inline void loop(u64 cntrs) From patchwork Wed Jul 3 09:57:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720555 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D6814DA14; Wed, 3 Jul 2024 02:13:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972792; cv=none; b=HxWxuGjRG/HSZJbzJc73zcx9nSJ9YzeovJ9/dm1ds5q+v9YUHM89Tys0P/UIz8ubX1erT5V4flLdKUDWBYRAOjKJjXZ8gVNbmK7pqYg7w75DCOzyIvC5su2VvHdH0ukQYRKFRf2WGBe1T0+IuTWKGE77F9fqXCqYzG66sqADAvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972792; c=relaxed/simple; bh=R/66LWCs88TWOQNVJu516TgpiQiS0Mu+jzzPoSjZGxI=; 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02 Jul 2024 19:13:08 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 14/18] x86: pmu: Adjust lower boundary of llc-misses event to 0 for legacy CPUs Date: Wed, 3 Jul 2024 09:57:08 +0000 Message-Id: <20240703095712.64202-15-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For these legacy Intel CPUs without clflush/clflushopt support, there is on way to force to trigger a LLC miss and the measured llc misses is possible to be 0. Thus adjust the lower boundary of llc-misses event to 0 to avoid possible false positive. Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 799d8d5c..c9c5fc19 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -82,6 +82,7 @@ struct pmu_event { enum { INTEL_INSTRUCTIONS_IDX = 1, INTEL_REF_CYCLES_IDX = 2, + INTEL_LLC_MISSES_IDX = 4, INTEL_BRANCHES_IDX = 5, }; @@ -877,6 +878,15 @@ int main(int ac, char **av) gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); instruction_idx = INTEL_INSTRUCTIONS_IDX; branch_idx = INTEL_BRANCHES_IDX; + + /* + * For legacy Intel CPUS without clflush/clflushopt support, + * there is no way to force to trigger a LLC miss, thus set + * the minimum value to 0 to avoid false positives. + */ + if (!this_cpu_has(X86_FEATURE_CLFLUSH)) + gp_events[INTEL_LLC_MISSES_IDX].min = 0; + report_prefix_push("Intel"); set_ref_cycle_expectations(); } else { From patchwork Wed Jul 3 09:57:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720556 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A92861FFB; Wed, 3 Jul 2024 02:13:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972795; cv=none; b=Ma8GGrLIlMCv12EeoqDv7zonZcrTJKQ9ZaJmu8aSL2G30V1IHB63c0KjTT1Sl+pI3rksMmjnSGbiOAnqbEC+5cl6P3+PC221tT0TcO6WxAtYbSoY8vI4eIiemrGbNvfYbytkdwHWMyl8rb1nx0fGUs9Y4QYhnP2qa3wXqdHcmGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972795; c=relaxed/simple; bh=iQdi4gGhSljc/r7rV+lLy/f6YfOXx8nDMF2O3B0DeX0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OOxHMP0SuySIb0iuJwsTmeY7med6nUYPFAPnz5mLs8XqdXLc9yify5HGWTc+8jbxLX//b5eMqVkjVjqM+oLAm4hBjUpYn/V3E8l0rBYaQPP3k/tg1gVW5hkp2NHR2K8KEwW+sbxFiir7V6mFEh9YtPpJiO6ZaFxwYaakNXPpwQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ixl0mE4x; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ixl0mE4x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719972794; x=1751508794; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iQdi4gGhSljc/r7rV+lLy/f6YfOXx8nDMF2O3B0DeX0=; b=Ixl0mE4xCKJlHZRIqQAdpL/aqOni+iEWDXTEoOtOtue3CoDNAnKtIbrT bnVMDlY3dXjIMbBM6Wl+uVl+LATmGyZkvZPblmhVrrjr98OKnksyjr3LY cnsVKkNvE2RM4wZHd6UItspr8kXAq6+X4vugHmyc+3QNvelo8zZ7G2pfG cQ1RVtU9BIOJLvgWHq0KtEMIRv0b+ev0GYCeFaUvxF2U5KAlyS63dkAMp XnhtRT+o+6jXykeJ2dYp3rVgQnEWkMZ+n7+R+/pXSrSJ5IDsKzK1Iur1P 1VX82r9+ohnXzXB7IPFbUdzNfNy2I/Fam59q8PHxcOmV4IIsD+1RWTV7q Q==; X-CSE-ConnectionGUID: DjaMnhNuQhqxo5DrPyau2w== X-CSE-MsgGUID: 5MRuqrfXQs+ND2VVdudyZA== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17311126" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17311126" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:13:14 -0700 X-CSE-ConnectionGUID: D+LLzHFfSum+rAB87xPR3Q== X-CSE-MsgGUID: B2hzyWKwSUqHiYttPWrFWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148803" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:13:11 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 15/18] x86: pmu: Add IBPB indirect jump asm blob Date: Wed, 3 Jul 2024 09:57:09 +0000 Message-Id: <20240703095712.64202-16-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently the lower boundary of branch misses event is set to 0. Strictly speaking 0 shouldn't be a valid count since it can't tell us if branch misses event counter works correctly or even disabled. Whereas it's also possible and reasonable that branch misses event count is 0 especailly for such simple loop() program with advanced branch predictor. To eliminate such ambiguity and make branch misses event verification more acccurately, an extra IBPB indirect jump asm blob is appended and IBPB command is leveraged to clear the branch target buffer and force to cause a branch miss for the indirect jump. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 71 +++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 56 insertions(+), 15 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index c9c5fc19..498b18d0 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,25 +19,52 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 - -/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ -#define EXTRA_INSTRNS (3 + 3 + 2) +#define IBPB_JMP_INSTRNS 9 +#define IBPB_JMP_BRANCHES 2 + +#if defined(__i386__) || defined(_M_IX86) /* i386 */ +#define IBPB_JMP_ASM(_wrmsr) \ + "mov $1, %%eax; xor %%edx, %%edx;\n\t" \ + "mov $73, %%ecx;\n\t" \ + _wrmsr "\n\t" \ + "call 1f\n\t" \ + "1: pop %%eax\n\t" \ + "add $(2f-1b), %%eax\n\t" \ + "jmp *%%eax;\n\t" \ + "nop;\n\t" \ + "2: nop;\n\t" +#else /* x86_64 */ +#define IBPB_JMP_ASM(_wrmsr) \ + "mov $1, %%eax; xor %%edx, %%edx;\n\t" \ + "mov $73, %%ecx;\n\t" \ + _wrmsr "\n\t" \ + "call 1f\n\t" \ + "1: pop %%rax\n\t" \ + "add $(2f-1b), %%rax\n\t" \ + "jmp *%%rax;\n\t" \ + "nop;\n\t" \ + "2: nop;\n\t" +#endif + +/* GLOBAL_CTRL enable + disable + clflush/mfence + IBPB_JMP */ +#define EXTRA_INSTRNS (3 + 3 + 2 + IBPB_JMP_INSTRNS) #define LOOP_INSTRNS (N * 10 + EXTRA_INSTRNS) -#define LOOP_BRANCHES (N) -#define LOOP_ASM(_wrmsr, _clflush) \ - _wrmsr "\n\t" \ +#define LOOP_BRANCHES (N + IBPB_JMP_BRANCHES) +#define LOOP_ASM(_wrmsr1, _clflush, _wrmsr2) \ + _wrmsr1 "\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ _clflush "\n\t" \ "mfence;\n\t" \ "1: mov (%1), %2; add $64, %1;\n\t" \ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" \ + IBPB_JMP_ASM(_wrmsr2) \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ - _wrmsr "\n\t" + _wrmsr1 "\n\t" -#define _loop_asm(_wrmsr, _clflush) \ +#define _loop_asm(_wrmsr1, _clflush, _wrmsr2) \ do { \ - asm volatile(LOOP_ASM(_wrmsr, _clflush) \ + asm volatile(LOOP_ASM(_wrmsr1, _clflush, _wrmsr2) \ : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ : "a"(eax), "d"(edx), "c"(global_ctl), \ "0"(N), "1"(buf) \ @@ -100,6 +127,12 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; +static int has_ibpb(void) +{ + return this_cpu_has(X86_FEATURE_SPEC_CTRL) || + this_cpu_has(X86_FEATURE_AMD_IBPB); +} + static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; @@ -107,10 +140,14 @@ static inline void __loop(void) u32 eax = 0; u32 edx = 0; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _loop_asm("nop", "clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _loop_asm("nop", "clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("nop", "clflush (%1)", "nop"); + else if (has_ibpb()) + _loop_asm("nop", "nop", "wrmsr"); else - _loop_asm("nop", "nop"); + _loop_asm("nop", "nop", "nop"); } /* @@ -127,10 +164,14 @@ static inline void __precise_loop(u64 cntrs) u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _loop_asm("wrmsr", "clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _loop_asm("wrmsr", "clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("wrmsr", "clflush (%1)", "nop"); + else if (has_ibpb()) + _loop_asm("wrmsr", "nop", "wrmsr"); else - _loop_asm("wrmsr", "nop"); + _loop_asm("wrmsr", "nop", "nop"); } static inline void loop(u64 cntrs) From patchwork Wed Jul 3 09:57:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720557 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50C8F7F7FB; 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X-CSE-ConnectionGUID: zDEI6B2cSoOQxz7SPt+HNg== X-CSE-MsgGUID: ddMRgbTsTg6cEfJbPCoSIg== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="17311131" X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="17311131" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:13:17 -0700 X-CSE-ConnectionGUID: yzNWfzGyTt2Ie6cgaGg6kg== X-CSE-MsgGUID: r3uUIS/MSyqiftxw4TSiqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148833" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:13:14 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 16/18] x86: pmu: Adjust lower boundary of branch-misses event Date: Wed, 3 Jul 2024 09:57:10 +0000 Message-Id: <20240703095712.64202-17-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since the IBPB command is added to force to trigger a branch miss at least, the lower boundary of branch misses event is increased to 1 by default. For these CPUs without IBPB support, adjust dynamically the lower boundary to 0 to avoid false positive. Signed-off-by: Dapeng Mi --- x86/pmu.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 498b18d0..4026deab 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -90,12 +90,12 @@ struct pmu_event { {"llc references", 0x4f2e, 1, 2*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, - {"branch misses", 0x00c5, 0, 0.1*N}, + {"branch misses", 0x00c5, 1, 0.1*N}, }, amd_gp_events[] = { {"core cycles", 0x0076, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, {"branches", 0x00c2, 1*N, 1.1*N}, - {"branch misses", 0x00c3, 0, 0.1*N}, + {"branch misses", 0x00c3, 1, 0.1*N}, }, fixed_events[] = { {"fixed 0", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, {"fixed 1", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, @@ -111,6 +111,7 @@ enum { INTEL_REF_CYCLES_IDX = 2, INTEL_LLC_MISSES_IDX = 4, INTEL_BRANCHES_IDX = 5, + INTEL_BRANCH_MISS_IDX = 6, }; /* @@ -120,6 +121,7 @@ enum { enum { AMD_INSTRUCTIONS_IDX = 1, AMD_BRANCHES_IDX = 2, + AMD_BRANCH_MISS_IDX = 3, }; char *buf; @@ -183,7 +185,8 @@ static inline void loop(u64 cntrs) } static void adjust_events_range(struct pmu_event *gp_events, - int instruction_idx, int branch_idx) + int instruction_idx, int branch_idx, + int branch_miss_idx) { /* * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are @@ -198,6 +201,17 @@ static void adjust_events_range(struct pmu_event *gp_events, gp_events[branch_idx].min = LOOP_BRANCHES; gp_events[branch_idx].max = LOOP_BRANCHES; } + + /* + * For CPUs without IBPB support, no way to force to trigger a + * branch miss and the measured branch misses is possible to be + * 0. Thus overwrite the lower boundary of branch misses event + * to 0 to avoid false positive. + */ + if (!has_ibpb()) { + /* branch misses event */ + gp_events[branch_miss_idx].min = 0; + } } volatile uint64_t irq_received; @@ -903,6 +917,7 @@ int main(int ac, char **av) { int instruction_idx; int branch_idx; + int branch_miss_idx; setup_vm(); handle_irq(PMI_VECTOR, cnt_overflow); @@ -919,6 +934,7 @@ int main(int ac, char **av) gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); instruction_idx = INTEL_INSTRUCTIONS_IDX; branch_idx = INTEL_BRANCHES_IDX; + branch_miss_idx = INTEL_BRANCH_MISS_IDX; /* * For legacy Intel CPUS without clflush/clflushopt support, @@ -935,9 +951,10 @@ int main(int ac, char **av) gp_events = (struct pmu_event *)amd_gp_events; instruction_idx = AMD_INSTRUCTIONS_IDX; branch_idx = AMD_BRANCHES_IDX; + branch_miss_idx = AMD_BRANCH_MISS_IDX; report_prefix_push("AMD"); } - adjust_events_range(gp_events, instruction_idx, branch_idx); + adjust_events_range(gp_events, instruction_idx, branch_idx, branch_miss_idx); printf("PMU version: %d\n", pmu.version); printf("GP counters: %d\n", pmu.nr_gp_counters); From patchwork Wed Jul 3 09:57:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720559 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB9710A1E; Wed, 3 Jul 2024 02:13:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972801; cv=none; b=pT19eSy+gNRO02rujNuff4YFXrJEVtCWukDPk3Kp6WOyCxDcyZD2T6u12egYHl1URZdgvWBayodnnNzN4z/WbWrFvW1nehLU/mzjOn6RiTz5bezdOzAtkojf42VSRiE6K3lQMqCUS+yqQaOGViLJgITc1IE8ZXBdvAxSQgPr1LA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719972801; 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d="scan'208";a="46148860" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:13:17 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 17/18] x86: pmu: Optimize emulated instruction validation Date: Wed, 3 Jul 2024 09:57:11 +0000 Message-Id: <20240703095712.64202-18-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For support CPUs supporting PERF_GLOBAL_CTRL MSR, the validation for emulated instruction can be improved to check against precise counts for instructions and branches events instead of a rough range. Move enabling and disabling PERF_GLOBAL_CTRL MSR into kvm_fep_asm blob, thus instructions and branches events can be verified against precise counts. Signed-off-by: Dapeng Mi --- x86/pmu.c | 108 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 65 insertions(+), 43 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 4026deab..332d274c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -14,11 +14,6 @@ #define N 1000000 -// These values match the number of instructions and branches in the -// assembly block in check_emulated_instr(). -#define EXPECTED_INSTR 17 -#define EXPECTED_BRNCH 5 - #define IBPB_JMP_INSTRNS 9 #define IBPB_JMP_BRANCHES 2 @@ -71,6 +66,40 @@ do { \ : "edi"); \ } while (0) +/* the number of instructions and branches of the kvm_fep_asm() blob */ +#define KVM_FEP_INSTR 22 +#define KVM_FEP_BRNCH 5 + +/* + * KVM_FEP is a magic prefix that forces emulation so + * 'KVM_FEP "jne label\n"' just counts as a single instruction. + */ +#define kvm_fep_asm(_wrmsr) \ +do { \ + asm volatile( \ + _wrmsr "\n\t" \ + "mov %%ecx, %%edi;\n\t" \ + "mov $0x0, %%eax;\n\t" \ + "cmp $0x0, %%eax;\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "1: mov %%edi, %%ecx; \n\t" \ + "xor %%eax, %%eax; \n\t" \ + "xor %%edx, %%edx;\n\t" \ + _wrmsr "\n\t" \ + : \ + : "a"(eax), "d"(edx), "c"(ecx) \ + : "ebx", "edi"); \ +} while (0) + typedef struct { uint32_t ctr; uint32_t idx; @@ -657,6 +686,7 @@ static void check_running_counter_wrmsr(void) static void check_emulated_instr(void) { + u32 eax, edx, ecx; uint64_t status, instr_start, brnch_start; uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1; unsigned int branch_idx = pmu.is_intel ? @@ -664,6 +694,7 @@ static void check_emulated_instr(void) unsigned int instruction_idx = pmu.is_intel ? INTEL_INSTRUCTIONS_IDX : AMD_INSTRUCTIONS_IDX; + pmu_counter_t brnch_cnt = { .ctr = MSR_GP_COUNTERx(0), /* branch instructions */ @@ -679,55 +710,46 @@ static void check_emulated_instr(void) if (this_cpu_has_perf_global_status()) pmu_clear_global_status(); - start_event(&brnch_cnt); - start_event(&instr_cnt); + __start_event(&brnch_cnt, 0); + __start_event(&instr_cnt, 0); - brnch_start = -EXPECTED_BRNCH; - instr_start = -EXPECTED_INSTR; + brnch_start = -KVM_FEP_BRNCH; + instr_start = -KVM_FEP_INSTR; wrmsr(MSR_GP_COUNTERx(0), brnch_start & gp_counter_width); wrmsr(MSR_GP_COUNTERx(1), instr_start & gp_counter_width); - // KVM_FEP is a magic prefix that forces emulation so - // 'KVM_FEP "jne label\n"' just counts as a single instruction. - asm volatile( - "mov $0x0, %%eax\n" - "cmp $0x0, %%eax\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "label:\n" - : - : - : "eax", "ebx", "ecx", "edx"); - if (this_cpu_has_perf_global_ctrl()) - wrmsr(pmu.msr_global_ctl, 0); + if (this_cpu_has_perf_global_ctrl()) { + eax = BIT(0) | BIT(1); + ecx = pmu.msr_global_ctl; + edx = 0; + kvm_fep_asm("wrmsr"); + } else { + eax = ecx = edx = 0; + kvm_fep_asm("nop"); + } - stop_event(&brnch_cnt); - stop_event(&instr_cnt); + __stop_event(&brnch_cnt); + __stop_event(&instr_cnt); // Check that the end count - start count is at least the expected // number of instructions and branches. - report(instr_cnt.count - instr_start >= EXPECTED_INSTR, - "instruction count"); - report(brnch_cnt.count - brnch_start >= EXPECTED_BRNCH, - "branch count"); + if (this_cpu_has_perf_global_ctrl()) { + report(instr_cnt.count - instr_start == KVM_FEP_INSTR, + "instruction count"); + report(brnch_cnt.count - brnch_start == KVM_FEP_BRNCH, + "branch count"); + } else { + report(instr_cnt.count - instr_start >= KVM_FEP_INSTR, + "instruction count"); + report(brnch_cnt.count - brnch_start >= KVM_FEP_BRNCH, + "branch count"); + } + if (this_cpu_has_perf_global_status()) { // Additionally check that those counters overflowed properly. status = rdmsr(pmu.msr_global_status); - report(status & 1, "branch counter overflow"); - report(status & 2, "instruction counter overflow"); + report(status & BIT_ULL(0), "branch counter overflow"); + report(status & BIT_ULL(1), "instruction counter overflow"); } report_prefix_pop(); From patchwork Wed Jul 3 09:57:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 13720560 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4378F131732; Wed, 3 Jul 2024 02:13:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="17311148" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 19:13:23 -0700 X-CSE-ConnectionGUID: /w4k3O+bSwu20NIZV9QPiA== X-CSE-MsgGUID: EqIfOJT6TcSDto4BJYD4Bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,180,1716274800"; d="scan'208";a="46148892" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa010.fm.intel.com with ESMTP; 02 Jul 2024 19:13:20 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [Patch v5 18/18] x86: pmu: Print measured event count if test fails Date: Wed, 3 Jul 2024 09:57:12 +0000 Message-Id: <20240703095712.64202-19-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Print the measured event count if the test case fails. This helps users quickly know why the test case fails. Signed-off-by: Dapeng Mi --- x86/pmu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 332d274c..0658a1c1 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -398,8 +398,12 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { - // printf("%d <= %ld <= %d\n", e->min, count, e->max); - return count >= e->min && count <= e->max; + bool pass = count >= e->min && count <= e->max; + + if (!pass) + printf("FAIL: %d <= %"PRId64" <= %d\n", e->min, count, e->max); + + return pass; } static bool verify_counter(pmu_counter_t *cnt)