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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?qPN7erwsJhycNyG2xpg3dAHI1k71?= =?utf-8?q?KsXbFefH5YPX5LZXyp/5/LkC/lyH2PovDLBsVS2h3uRzZsBBWrqOxIMwDLmTwYCyT?= =?utf-8?q?URpyW3zYbVy85hAGDv7gxlCusPQrcqDqSTqCUfwyDd3uJI6K/NNrWWW7LlGAUGs88?= =?utf-8?q?998jnFkUYdLdOSqbk/JcVzGKtXclfcQWxT7MHQsQw7m+58WHznc1MnUvy4ukSQAZw?= =?utf-8?q?iV+SKjjZfbklfTVpmaUmhZPKE/wVJfVt7zhWF/FNzmDp2qzq1bPYOliyWx1pSmf1i?= =?utf-8?q?hx0tDsEy8oDm+oAEHMJFZKiksvjHqdmUh7QyOwctEMTjH+PGft0JrJEESVUyWDenL?= =?utf-8?q?HeJZI9poafq44D4ViNkLZ4g6/hUl6s54VMjjxMH7x78R5WChiYm4fgLRYElTw8kKT?= =?utf-8?q?t7IAeu6TVs8HSe2ysiD7Q549nIggZ3tqhtNj4cgbrSwaDQWw65EBFvAP1MN7cJUfB?= =?utf-8?q?ryyqmaD9eYfp8+nPNwqKjNyD1Xl1WSWUPWIWCCo0uaE/oPlxmT2E6FTqRBCiItSPi?= =?utf-8?q?cS+NACIRX1bSdr26W+Jt1jWWH9XNvbXnH+I/7E5GC2ZcFtJZ3ThIU1smrVjRAAxBV?= =?utf-8?q?L/Y65ZcgnIhmr9wzIGrO9wINki0HBDXrgzlhoboKlIOS4SyYrM09L1WDDppXSB8mU?= =?utf-8?q?i16aEj8tatPD9CLAUkpKEr+O8kQNYboT6aR14s7rIP8OQGkrnNovkV+rTSK5YhAjB?= =?utf-8?q?zYeG1gt5hQsk0xmRQ982hMVsWURLK6DgyVOeDliB7vnbYhcH++/J4N0KlzaSnBFGO?= =?utf-8?q?hP0kni304cbrCPjcQyZCu7yLIAP9TP/2fsWUDy0Lv8oqvyav+WpBDZheQZ/ytwZYV?= =?utf-8?q?1Q33tQi7te7tUFdfPirc/0G94vHlLB/y1HW+5FJWCEvHvpkyUZNor7il5a2/icaP4?= =?utf-8?q?Pxk7Wy9fzRCqA+v6Avm3jC7nIzh+TNVQbMftbZphbxMP68A+LEWDJMGTf6NzF7SO4?= =?utf-8?q?Rc3gYFrlo/B+2jgiLoxEeg+nAbWL5AsdtpbDywLNhdmcidTGDmRLCBKjwmoeaFZG1?= =?utf-8?q?R5Uszt7Rp/srS4Dm6dS4MrSZXDeaPG1tULPQwNHPiHUC5EOUYY60LKksE7ltg2SpV?= =?utf-8?q?AX61xl3jPKb6+FSH7AM5ZeEW73pMAv1U7ECcK0Az8Uvfk3y9Ns/gYgJvryVpIQzl8?= =?utf-8?q?hkMLcrGELOrYMg0JZ8kido2AqSqnrd16qXNQgEHvPCBX9PpUJlgZq5QD0s7WOM9TX?= =?utf-8?q?yGxAnG22fnFkG3AL40IeuC9081IsWalA7Zj3Vkh+FmbrQvSx8nVu681Zod1baHcHR?= =?utf-8?q?Rhd8nlQMP8Kb8isDF7ye+eu303SQfu8q/07KzwrGWHqkr+CGRM4L2436DYbNckVMT?= =?utf-8?q?tRWM+9mXx5gwOhM5UPyT7Q9WPJJdYs94PJZbHgGMXCpUrLHw+NTq43z2fkD+ihmA8?= =?utf-8?q?2c+CDHIM04TGw98PcaSiJtuxlUVc4WPQNAatBDjfwMGkR/fm3l+kSFCB3R2Qz+pLL?= =?utf-8?q?WmoSaTihWqLXTlgVQuIGTqeHNcG2YqtJgMuDn1bkS83Z47e1gMljVBulDlsAopFK4?= =?utf-8?q?lYx3ysywNkvW?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 07db3fd7-7af8-490f-7fa0-08dc9bb4e012 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2024 23:07:13.6424 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: n3QSCR4yUyJ1O8TtENx16l+/E6NvS4s6hWeF8WEWCy1tYOAGWxhowduGQNow3Ttpq/6P6OLiqabQXri3LunZxQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR04MB7242 From: Ran Wang Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW default cache type configuration to fix DWC3 init failure when applying property dma-coherent. The cache type configuration is actually native feature of DWC3, not additional desgin (or glue layer) coming from SoC, so add compatible string 'fsl,ls-dwc3'. Signed-off-by: Ran Wang Reviewed-by: Jun Li Signed-off-by: Frank Li --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 1cd0ca90127d9..02cb986d0fd32 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -32,6 +32,7 @@ properties: compatible: contains: oneOf: + - const: fsl,ls-dwc3 - const: snps,dwc3 - const: synopsys,dwc3 deprecated: true From patchwork Wed Jul 3 23:06:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13723053 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2085.outbound.protection.outlook.com [40.107.20.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4726194C8C for ; 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For each transfer type, controller has a 4-bit register field to enable different cache type. Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments: ---------------------------------------------------------------- MBUS_TYPE| bit[3] |bit[2] |bit[1] |bit[0] ---------------------------------------------------------------- AHB |Cacheable |Bufferable |Privilegge |Data AXI3 |Write Allocate|Read Allocate|Cacheable |Bufferable AXI4 |Allocate Other|Allocate |Modifiable |Bufferable AXI4 |Other Allocate|Allocate |Modifiable |Bufferable Native |Same as AXI |Same as AXI |Same as AXI|Same as AXI ---------------------------------------------------------------- Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain signals, which have the same meaning: Bufferable = Posted Cacheable = Modifiable = Snoop (negation of No Snoop) In most cases, driver work well with default value. But USB device detect failure sometime on Layerscape platforms if bit[1] not set and enable dma-coherent. Set bit[1] "Snoop" for Data Read, Desc Read, Data Write and Desc write if compatible string contain fsl,ls-dwc3. Signed-off-by: Ran Wang Reviewed-by: Jun Li Signed-off-by: Frank Li --- drivers/usb/dwc3/core.c | 12 ++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index cb82557678ddd..2b474de83b783 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1061,6 +1061,18 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + if (of_device_is_compatible(dev->of_node, "fsl,ls-dwc3")) { + + cfg &= ~(DWC3_GSBUSCFG0_DATARD | DWC3_GSBUSCFG0_DESCRD | + DWC3_GSBUSCFG0_DATAWR | DWC3_GSBUSCFG0_DESCWR); + cfg |= FIELD_PREP(DWC3_GSBUSCFG0_DATARD, 2) | + FIELD_PREP(DWC3_GSBUSCFG0_DESCRD, 2) | + FIELD_PREP(DWC3_GSBUSCFG0_DATAWR, 2) | + FIELD_PREP(DWC3_GSBUSCFG0_DESCWR, 2); + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); + } + /* * Handle property "snps,incr-burst-type-adjustment". * Get the number of value from this property: diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 3781c736c1a17..99edfabd89673 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -184,6 +184,10 @@ /* Bit fields */ /* Global SoC Bus Configuration INCRx Register 0 */ +#define DWC3_GSBUSCFG0_DATARD GENMASK(31, 28) +#define DWC3_GSBUSCFG0_DESCRD GENMASK(27, 24) +#define DWC3_GSBUSCFG0_DATAWR GENMASK(23, 20) +#define DWC3_GSBUSCFG0_DESCWR GENMASK(19, 16) #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */