From patchwork Fri Jul 5 13:42:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Bonnefille X-Patchwork-Id: 13725159 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22556154458; Fri, 5 Jul 2024 13:42:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720186956; cv=none; b=SY85Y8kej/KPvqLDrUZWHUIHII2yn5V608EwKHVW95yj2SaGp3B1rHrYNHBZr+ckYxOW4v1GBMt2TJgSYWOgJcysq3V7ie6S6/G51+P/4t2Dq04V9hrEgvmcJ2f+lHOg6nCCVgLmZnRUed690nB0EsogEK8W13Sre58rnBUnYAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720186956; c=relaxed/simple; bh=eV1nr9EcWp01rio9fuJXhva/jBt+bqRu5Lz/dqYDjNE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SJhMDHPmiFEotSGlC8MxYzigWYhgXjDxRI/sK5zBw4tUewy2F7ZsT5QuCj44asGznsaI6sSJZztiF8IxKe3fnfEiC+4F18YFZ37B+Yvx+d8DojTV7sqpBwiq+catq6P5TcT1q+mGa3k7MMtBcardnkfXP1GZVPWfHl3V4TcWDBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cYemTJtw; arc=none smtp.client-ip=217.70.183.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cYemTJtw" Received: by mail.gandi.net (Postfix) with ESMTPSA id A367B240006; Fri, 5 Jul 2024 13:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1720186952; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ODottIJUZD5cbwACBdwt28E6WF2p4dCijXNFos9RZ6s=; b=cYemTJtwaBgKyuYuDe1/QjDtG1Xo55/jjihYG4oMnzU7p8Mwhxtne1hv/DjMfm5ZLSBTje 88rEkrCGXP8BSL+LUW+LNWD8QQOW2nRDVeTBgjUcLAAL5W3Uf9qYg+YjVVjSH0lq4MEiUp dGOTKE6RXafz+nffLqgaEBcn/K6COSCANd8QYfO2G4oJQZLmbNHt+Z+j4I/aW1LVH12nCo A/imJDvpA+FHYRL6tg0AEtHFnbjByAm08Lzc9nJv8uUd31AALMAjT+2A1lRm5IeKlzgGzs HHUKMzlWnfTzYBenKKloR3a0gFYH4M4/BSOMMz0AeOpICaUwn8/p39HyNOOGwA== From: Thomas Bonnefille Date: Fri, 05 Jul 2024 15:42:23 +0200 Subject: [PATCH v2 1/3] dt-bindings: iio: adc: sophgo,cv18xx-saradc.yaml: Add Sophgo SARADC binding documentation Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240705-sg2002-adc-v2-1-83428c20a9b2@bootlin.com> References: <20240705-sg2002-adc-v2-0-83428c20a9b2@bootlin.com> In-Reply-To: <20240705-sg2002-adc-v2-0-83428c20a9b2@bootlin.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Thomas Petazzoni , =?utf-8?q?Miqu=C3=A8l_R?= =?utf-8?q?aynal?= , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Thomas Bonnefille X-Mailer: b4 0.14.0 X-GND-Sasl: thomas.bonnefille@bootlin.com The Sophgo SARADC is a Successive Approximation ADC that can be found in the Sophgo SoC. Signed-off-by: Thomas Bonnefille --- .../bindings/iio/adc/sophgo,cv18xx-saradc.yaml | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/sophgo,cv18xx-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/sophgo,cv18xx-saradc.yaml new file mode 100644 index 000000000000..31bd8ac6dfa5 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/sophgo,cv18xx-saradc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/sophgo,cv18xx-saradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: + Sophgo CV18XX SoC series 3 channels Successive Approximation Analog to + Digital Converters + +maintainers: + - Thomas Bonnefille + +description: + Datasheet at https://github.com/sophgo/sophgo-doc/releases + +properties: + compatible: + oneOf: + - items: + - enum: + - sophgo,cv1800b-saradc + - const: sophgo,cv18xx-saradc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: + SARADC will use the presence of this clock to determine if the controller + needs to be explicitly clocked by it (Active domain) or if it is part of + the No-Die Domain, along with the RTC, which does not require explicit + clocking. + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + /* ADC in the Active domain */ + adc@30f0000 { + compatible = "sophgo,cv1800b-saradc", "sophgo,cv18xx-saradc"; + clocks = <&clk CLK_SARADC>; + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x030F0000 0x1000>; + }; + - | + #include + #include + /* ADC in the No-Die domain */ + adc@502c000 { + compatible = "sophgo,cv1800b-saradc", "sophgo,cv18xx-saradc"; + reg = <0x0502C000 0x1000>; + }; From patchwork Fri Jul 5 13:42:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Bonnefille X-Patchwork-Id: 13725160 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6AA814C5BD; Fri, 5 Jul 2024 13:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720186957; cv=none; b=Ks3n+AU8HSZRacBSckcmOEWdRnVyo14W2jVYYwbZSlsxsj7Y75ylNatMEPU2InVAbG472PWvt9nxzNPSee/mplaOGU8Dubs+yhTNn79brsVlO0Q4E4ff9AHlCfmf5JwQHWNraIc3v51NDhQ3lUyxmhCmaNWevktiJJlMtMXZNAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720186957; c=relaxed/simple; bh=iCfISyqO4lqGabTJUDndtNk6xzssnQ7JRz8VHzNH4lA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BLuboDCzgNae6V9aw7Q2Cmvs94NbutwyYzZ0ItzyI0VpWNPZ8uVl24wUL62SzhBxIp0FXZBHIgJCnueuTmCbvxMNiAWU/w8IMnK7OHq0wo9J41MU3I5bp73p7hO+RBFE3i5yRGrpK7gNKUShNWm/NqVBGwgYdg8AmyI/gYzxNF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=kTU5hJXK; arc=none smtp.client-ip=217.70.183.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="kTU5hJXK" Received: by mail.gandi.net (Postfix) with ESMTPSA id 6EE56240004; Fri, 5 Jul 2024 13:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1720186953; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8opSpDQ51mRmczar3YcnEwHG514tMoc1SR4IVLVTgKQ=; b=kTU5hJXKrnTlWrdPeuDhJYclr1rk5hNRQ+GLH5uKT5JHGf9bBUMk+0UtG8iuzNQmRziLWr of1xvswBArd3vEE++kzmYosL0Wa2TJSxVw2ZJVxYr/I+jerzVCvYHrSKqPt5lJoJhrJ5gF kLq/62DVCAgRli+D17uyZI9KPLqlsSRm2Cy4zIXN53bPgtC1GbTtpkLyyuc9mYWt2CVw/s qEy+eS6IJe6iJ+8XfWWeQ5Lgq7FAGOhmOVlwp4wqBc4EXSCpCwb//CAo4uP1RO/4FDxw1t w45j1FZPeDzykCzFZHy69OGOhTLtPYqPAIMlV6Qq3sSdyVubnMedRxGPOlgj5w== From: Thomas Bonnefille Date: Fri, 05 Jul 2024 15:42:24 +0200 Subject: [PATCH v2 2/3] iio: adc: sophgo-saradc: Add driver for Sophgo SARADC Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240705-sg2002-adc-v2-2-83428c20a9b2@bootlin.com> References: <20240705-sg2002-adc-v2-0-83428c20a9b2@bootlin.com> In-Reply-To: <20240705-sg2002-adc-v2-0-83428c20a9b2@bootlin.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Thomas Petazzoni , =?utf-8?q?Miqu=C3=A8l_R?= =?utf-8?q?aynal?= , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Thomas Bonnefille X-Mailer: b4 0.14.0 X-GND-Sasl: thomas.bonnefille@bootlin.com This adds a driver for the common Sophgo SARADC. Signed-off-by: Thomas Bonnefille --- drivers/iio/adc/Kconfig | 10 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/sophgo-cv18xx-adc.c | 195 ++++++++++++++++++++++++++++++++++++ 3 files changed, 206 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 8db68b80b391..e48d8f7f2873 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1122,6 +1122,16 @@ config SC27XX_ADC This driver can also be built as a module. If so, the module will be called sc27xx_adc. +config SOPHGO_CV18XX_ADC + tristate "Sophgo CV18XX series SARADC" + depends on ARCH_SOPHGO || COMPILE_TEST + help + Say yes here to build support for the SARADC integrated inside + the Sophgo CV18XX series SoCs. + + This driver can also be built as a module. If so, the module + will be called sophgo_adc. + config SPEAR_ADC tristate "ST SPEAr ADC" depends on PLAT_SPEAR || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index edb32ce2af02..3967d3953349 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o obj-$(CONFIG_RICHTEK_RTQ6056) += rtq6056.o obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o +obj-$(CONFIG_SOPHGO_CV18XX_ADC) += sophgo-cv18xx-adc.o obj-$(CONFIG_SPEAR_ADC) += spear_adc.o obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o obj-$(CONFIG_SUN20I_GPADC) += sun20i-gpadc-iio.o diff --git a/drivers/iio/adc/sophgo-cv18xx-adc.c b/drivers/iio/adc/sophgo-cv18xx-adc.c new file mode 100644 index 000000000000..dd1188b1923e --- /dev/null +++ b/drivers/iio/adc/sophgo-cv18xx-adc.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Sophgo CV18XX series SARADC Driver + * + * Copyright (C) Bootlin 2024 + * Author: Thomas Bonnefille + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CV18XX_ADC_CTRL_REG 0x04 +#define CV18XX_ADC_EN BIT(0) +#define CV18XX_ADC_SEL(x) BIT((x)+4) +#define CV18XX_ADC_STATUS_REG 0x08 +#define CV18XX_ADC_BUSY BIT(0) +#define CV18XX_ADC_CYC_SET_REG 0x0C +#define CV18XX_ADC_DEF_CYC_SETTINGS 0xF1F0F +#define CV18XX_ADC_CH_RESULT_REG(x) (0x10+4*(x)) +#define CV18XX_ADC_CH_RESULT 0xfff +#define CV18XX_ADC_CH_VALID BIT(15) +#define CV18XX_ADC_INTR_EN_REG 0x20 +#define CV18XX_ADC_INTR_CLR_REG 0x24 +#define CV18XX_ADC_INTR_STA_REG 0x28 + +#define CV18XX_ADC_CHANNEL(index) \ + { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = index, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = index, \ + } + +struct cv18xx_adc { + struct completion completion; + void __iomem *regs; + struct mutex lock; /* ADC Control and Result register */ + int irq; +}; + +static const struct iio_chan_spec sophgo_channels[] = { + CV18XX_ADC_CHANNEL(1), + CV18XX_ADC_CHANNEL(2), + CV18XX_ADC_CHANNEL(3), +}; + +static void cv18xx_adc_start_measurement(struct cv18xx_adc *saradc, + int channel) +{ + writel(0, saradc->regs + CV18XX_ADC_CTRL_REG); + writel(CV18XX_ADC_SEL(channel) | CV18XX_ADC_EN, + saradc->regs + CV18XX_ADC_CTRL_REG); +} + +static int cv18xx_adc_wait(struct cv18xx_adc *saradc) +{ + if (saradc->irq < 0) { + u32 reg; + + return readl_poll_timeout(saradc->regs + CV18XX_ADC_STATUS_REG, + reg, !(reg & CV18XX_ADC_BUSY), + 500, 1000000); + } + return wait_for_completion_timeout(&saradc->completion, + msecs_to_jiffies(1000)) > 0 + ? 0 : -ETIMEDOUT; +} + +static int cv18xx_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_RAW: + struct cv18xx_adc *saradc = iio_priv(indio_dev); + u32 sample; + int ret; + + scoped_guard(mutex, &saradc->lock) { + cv18xx_adc_start_measurement(saradc, chan->scan_index); + ret = cv18xx_adc_wait(saradc); + if (ret < 0) + return ret; + + sample = readl(saradc->regs + CV18XX_ADC_CH_RESULT_REG(chan->scan_index)); + } + if (!(sample & CV18XX_ADC_CH_VALID)) + return -ENODATA; + + *val = sample & CV18XX_ADC_CH_RESULT; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val = 3300; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static irqreturn_t cv18xx_adc_interrupt_handler(int irq, void *private) +{ + struct cv18xx_adc *saradc = private; + + if (!(readl(saradc->regs + CV18XX_ADC_INTR_STA_REG) & BIT(0))) + return IRQ_NONE; + + writel(1, saradc->regs + CV18XX_ADC_INTR_CLR_REG); + complete(&saradc->completion); + return IRQ_HANDLED; +} + +static const struct iio_info cv18xx_adc_info = { + .read_raw = &cv18xx_adc_read_raw, +}; + +static int cv18xx_adc_probe(struct platform_device *pdev) +{ + struct cv18xx_adc *saradc; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*saradc)); + if (!indio_dev) + return -ENOMEM; + + saradc = iio_priv(indio_dev); + indio_dev->name = "sophgo-cv18xx-adc"; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &cv18xx_adc_info; + indio_dev->num_channels = ARRAY_SIZE(sophgo_channels); + indio_dev->channels = sophgo_channels; + + + if (IS_ERR(devm_clk_get_optional_enabled(&pdev->dev, NULL))) + dev_dbg(&pdev->dev, "Can't get clock from device tree, using No-Die domain"); + + saradc->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(saradc->regs)) { + ret = PTR_ERR(saradc->regs); + return ret; + } + + saradc->irq = platform_get_irq_optional(pdev, 0); + if (saradc->irq >= 0) { + init_completion(&saradc->completion); + ret = devm_request_irq(&pdev->dev, saradc->irq, + cv18xx_adc_interrupt_handler, 0, + dev_name(&pdev->dev), saradc); + if (ret) + return ret; + + writel(1, saradc->regs + CV18XX_ADC_INTR_EN_REG); + + } + + + mutex_init(&saradc->lock); + platform_set_drvdata(pdev, indio_dev); + writel(CV18XX_ADC_DEF_CYC_SETTINGS, saradc->regs + CV18XX_ADC_CYC_SET_REG); + ret = devm_iio_device_register(&pdev->dev, indio_dev); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id cv18xx_adc_match[] = { + { .compatible = "sophgo,cv18xx-saradc", }, + { } +}; +MODULE_DEVICE_TABLE(of, cv18xx_adc_match); + +static struct platform_driver cv18xx_adc_driver = { + .driver = { + .name = "sophgo-saradc", + .of_match_table = cv18xx_adc_match, + }, + .probe = cv18xx_adc_probe, +}; +module_platform_driver(cv18xx_adc_driver); + +MODULE_AUTHOR("Thomas Bonnefille "); +MODULE_DESCRIPTION("Sophgo SARADC driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Jul 5 13:42:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Bonnefille X-Patchwork-Id: 13725161 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809EB154C04; Fri, 5 Jul 2024 13:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720186957; cv=none; b=X6jM0K6DGdV9l0w3M7RD/VXmdA0ttGcrCWjzc+Uzzcfx6iXbWyLTk/mFdCKtIgvQ1HnpGosKgIWTS+uUPYYoFafwQeDYzkUzaJpqn5b80I3DbO+DEJrzLjf4Zx1c5nYlvbHsVIgsYbcvmJGzNeysFCHVUHM/E/Z+L/9yuKRkTH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720186957; c=relaxed/simple; bh=z9WsL0zU3oyUVTQFrcZ7jW08510FqQYoLiYtGQsJ/lw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eH7z9eDkdeaiyzD0o0qvU7x55XBJmI2xAhjH1nx9P0XrWnGrs7cvTPVVbSOCRs2tT465m+ZdCSSydTqj5YYB6vlFi42YPWiduEjT6nkpVAYNiZfGLxOK1M6o4SkSNYf1W4SeCcsabVql+fbZSFSR7YuedBwSZb36NyEBOrH30dM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=muw90pSE; arc=none smtp.client-ip=217.70.183.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="muw90pSE" Received: by mail.gandi.net (Postfix) with ESMTPSA id 3DCD6240007; Fri, 5 Jul 2024 13:42:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1720186953; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9hUs3AjldaPNd5g+4FRGeGWP8GUZ22OX94EKEBMYwyY=; b=muw90pSEWZSWnblkVz/gg/x8PI/GcoRx6QeUa/OD5umHK0FNeEL0hZsq3qKV3oA0Rmzh8v k8vNhdJbrymeh508A89nKxUbytN0E0nwibE+ualXZtedYSXStP0jfxciDF0c5bXIWzGshu 4QqjbN3Y9g4A26wAvlMtDmYR25ZcbMVlH+j4PnfacPT7PIbgcY6Nyym+CoiB5dPJ7MGGFT z89HnEW6zDWT7//lyyMSwptODE0w/aUz1g6ZLunSaKux0z6cRpxx/EGIyRsXLBMn7ypzhr 4fkqUz0YDUClNzT5pry/435Ke4DYl6pXIbKNm81W/Ez/yDLqXY+iN8IOtcsYTA== From: Thomas Bonnefille Date: Fri, 05 Jul 2024 15:42:25 +0200 Subject: [PATCH v2 3/3] riscv: dts: sophgo: Add SARADC configuration Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240705-sg2002-adc-v2-3-83428c20a9b2@bootlin.com> References: <20240705-sg2002-adc-v2-0-83428c20a9b2@bootlin.com> In-Reply-To: <20240705-sg2002-adc-v2-0-83428c20a9b2@bootlin.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Thomas Petazzoni , =?utf-8?q?Miqu=C3=A8l_R?= =?utf-8?q?aynal?= , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Thomas Bonnefille X-Mailer: b4 0.14.0 X-GND-Sasl: thomas.bonnefille@bootlin.com Adds SARADC nodes for the common Successive Approximation Analog to Digital Converter used in Sophgo CV18xx series SoC. This patch adds two nodes for the two controllers the board, one in the Active domain and the other in the No-Die domain. Signed-off-by: Thomas Bonnefille --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 8 ++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index ec9530972ae2..73abbb6e5363 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -25,3 +25,11 @@ &clint { &clk { compatible = "sophgo,cv1800-clk"; }; + +&saradc_active { + compatible = "sophgo,cv1800b-saradc", "sophgo,cv18xx-saradc"; +}; + +&saradc_nodie { + compatible = "sophgo,cv1800b-saradc", "sophgo,cv18xx-saradc"; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 891932ae470f..752e14fa3d0c 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -133,6 +133,14 @@ portd: gpio-controller@0 { }; }; + saradc_active: adc@30f0000 { + compatible = "sophgo,cv18xx-saradc"; + clocks = <&clk CLK_SARADC>; + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x030F0000 0x1000>; + status = "disabled"; + }; + i2c0: i2c@4000000 { compatible = "snps,designware-i2c"; reg = <0x04000000 0x10000>; @@ -297,6 +305,12 @@ sdhci0: mmc@4310000 { status = "disabled"; }; + saradc_nodie: adc@502c000 { + compatible = "sophgo,cv18xx-saradc"; + reg = <0x0502C000 0x1000>; + status = "disabled"; + }; + plic: interrupt-controller@70000000 { reg = <0x70000000 0x4000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;