From patchwork Sat Mar 2 05:20:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836475 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BAA817E0 for ; Sat, 2 Mar 2019 05:21:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4942C2D759 for ; Sat, 2 Mar 2019 05:21:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CB032D789; Sat, 2 Mar 2019 05:21:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4B352D759 for ; Sat, 2 Mar 2019 05:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726319AbfCBFUb (ORCPT ); Sat, 2 Mar 2019 00:20:31 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9806 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbfCBFUb (ORCPT ); Sat, 2 Mar 2019 00:20:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:39 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Mar 2019 21:20:30 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:30 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 2 Mar 2019 05:20:30 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:29 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 01/11] mmc: tegra: fix ddr signaling for non-ddr modes Date: Fri, 1 Mar 2019 21:20:15 -0800 Message-ID: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504039; bh=Qe2T48QJX1FMDt69wX/5uHHEUnqPGEOo62jpymdGE50=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=lxtcKuD+qW5/YBbhFQsOJCjhgJ5hQLM3klmDJR0v1JK69DAZQMJmJhBn0LtZ7X/3k 14wtgBydG+RPtAtxPRmdBZmW2LNEAyMjuxR7/ruiSsTvjdtKi0oTT5hGZSaoEWFo/r jMYmqj//fEEPYDELTq74RHi94V78nkG2vgypOGRprA1rNqmZ4N+Ya5Q7u4Qqi5bsag HnRsKtnJA3agieKtksQcwpJ3pm5MLab/ElebnAa+xVeIIy7H/T9TqI72cgGQmiOBkD GYiUmK+SmdnZ+cC1xfMvAknFuRqA2/oZcDpmAHma/oJVn9jb1ue6w8EruetyMVq3Io EupwgF+PDJkxQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ddr_signaling is set to true for DDR50 and DDR52 modes but is not set back to false for other modes. This programs incorrect host clock when mode change happens from DDR52/DDR50 to other SDR or HS modes like incase of mmc_retune where it switches from HS400 to HS DDR and then from HS DDR to HS mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Signed-off-by: Sowjanya Komatineni Tested-by: Jon Hunter Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 32e62904c0d3..46086dd43bfb 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, bool set_dqs_trim = false; bool do_hs400_dll_cal = false; + tegra_host->ddr_signaling = false; switch (timing) { case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104: From patchwork Sat Mar 2 05:20:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836473 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0B57922 for ; Sat, 2 Mar 2019 05:21:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEABB2D759 for ; Sat, 2 Mar 2019 05:21:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D30082D789; Sat, 2 Mar 2019 05:21:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 766972D759 for ; Sat, 2 Mar 2019 05:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727492AbfCBFUf (ORCPT ); Sat, 2 Mar 2019 00:20:35 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9814 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbfCBFUe (ORCPT ); Sat, 2 Mar 2019 00:20:34 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:42 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:33 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:33 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 2 Mar 2019 05:20:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:32 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 02/11] mmc: sdhci: allow host to specify maximum tuning loops Date: Fri, 1 Mar 2019 21:20:16 -0800 Message-ID: <1551504025-3541-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504042; bh=+Pp6rIrvJvggoBUpoCHnktYSalCLLDgvrPjVwKSaiBk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HPguesaPq90KRCy+QMj+2tu2Y1fxuymcaJDRwh5WtNmkx5klQdhAx3+kwKeKL/ObB m+E7n/nFf1LvtdFHT6v7X82fsQDYjvpiB6/nNO+jhEl/45uCs/2nFngi5fZmzMTDTl TqlPTjlAee6x6H2GuzB43gNnxbyFv5YgJLxLku/F6OGlGRPL6wOzGQGFkfiU+IydE7 7s6sa3fWwu2F4kOMRVeHMOU5JcPI18/ZhJvwHKlRrU+UXaeefVHi9UPlYBMed+SBvG QfcNp5EgNaQKfe1HU+QmX+eoxtx2zCteJ+ypKXdr4G7w8g6g3/zw0hxTB2ehb7fJ6t BIUiMkIz4KX8w== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As per the Host Controller Standard Specification Version 4.20, limitation of tuning iteration count is removed as PLL locking time can be longer than UHS-1 tuning due to larger PVT fluctuation and it will result in increase of tuning iteration to complete the tuning. This patch creates a hook get_max_tuning_loop_count to allow hosts to specify maximum tuning iterations and updates execute_tuning to use the specified maximum tuning iteration count. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci.c | 7 +++++-- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index a8141ff9be03..e9e919218006 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2366,12 +2366,15 @@ EXPORT_SYMBOL_GPL(sdhci_send_tuning); static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; + int tuning_loop_count = MAX_TUNING_LOOP; + if (host->ops->get_max_tuning_loop_count) + tuning_loop_count = host->ops->get_max_tuning_loop_count(host); /* * Issue opcode repeatedly till Execute Tuning is set to 0 or the number - * of loops reaches 40 times. + * of loops reaches tuning loop count. */ - for (i = 0; i < MAX_TUNING_LOOP; i++) { + for (i = 0; i < tuning_loop_count; i++) { u16 ctrl; sdhci_send_tuning(host, opcode); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 01002cba1359..c80e0d6f9b10 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -638,6 +638,7 @@ struct sdhci_ops { unsigned int (*get_ro)(struct sdhci_host *host); void (*reset)(struct sdhci_host *host, u8 mask); int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + int (*get_max_tuning_loop_count)(struct sdhci_host *host); void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); void (*hw_reset)(struct sdhci_host *host); void (*adma_workaround)(struct sdhci_host *host, u32 intmask); From patchwork Sat Mar 2 05:20:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836471 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC2B1922 for ; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA4692D759 for ; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE5A12D789; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7AE792D759 for ; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727816AbfCBFUi (ORCPT ); Sat, 2 Mar 2019 00:20:38 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17551 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbfCBFUi (ORCPT ); Sat, 2 Mar 2019 00:20:38 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:31 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:37 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Mar 2019 21:20:37 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:36 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 2 Mar 2019 05:20:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:36 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 03/11] mmc: sdhci: add support for post tuning process Date: Fri, 1 Mar 2019 21:20:17 -0800 Message-ID: <1551504025-3541-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504031; bh=I88WLCNl1yV3gNupXuAzY6+a4EyFKT0wLnMQMi5w4B8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZDsNj7nmu9ANc4VbFPMN+eoIsn4zxTmSZiM+g84l2c9WIBjxtsSZkdHVbYskpfopB +jtEVVWkEWAL4lCEKFChZeTpk3Z9irSG0TBIWbMifRlaajs3emJzrw+PlP/ypBjp84 ZULqUYZCAKId0lCY1Oi3q6TiHl6kYdtO9rp3u0XDtWUQHa/6RSVD6mXgTzgINIDB09 auSf5UDs2LzZPGH0Km8qINdSXmxY3NrGF75u28C8KhVkoKsgnsO6nAj1uy9c+6FNcu Y33lFFZH0ynO31EyM70+9m1pxCEZ45eSrwh4Web4wCqLfhECWF0SrnYeSY4V02m8Xy lMNjEHOpyvdww== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for post tuning process needed for some hosts to perform after successful completion of HW tuning. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci.c | 6 +++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index e9e919218006..976d4d1e2400 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2392,8 +2392,12 @@ static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { - if (ctrl & SDHCI_CTRL_TUNED_CLK) + if (ctrl & SDHCI_CTRL_TUNED_CLK) { + if (host->ops->post_tuning) + host->ops->post_tuning(host); return 0; /* Success! */ + } + break; } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c80e0d6f9b10..236d67778645 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -639,6 +639,7 @@ struct sdhci_ops { void (*reset)(struct sdhci_host *host, u8 mask); int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); int (*get_max_tuning_loop_count)(struct sdhci_host *host); + void (*post_tuning)(struct sdhci_host *host); void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); void (*hw_reset)(struct sdhci_host *host); void (*adma_workaround)(struct sdhci_host *host, u32 intmask); From patchwork Sat Mar 2 05:20:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836469 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4891B17E0 for ; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 332272D759 for ; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24BA92D789; Sat, 2 Mar 2019 05:21:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 332472D759 for ; Sat, 2 Mar 2019 05:21:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727926AbfCBFUm (ORCPT ); Sat, 2 Mar 2019 00:20:42 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17563 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbfCBFUl (ORCPT ); Sat, 2 Mar 2019 00:20:41 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:34 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:40 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:40 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 2 Mar 2019 05:20:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:39 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 04/11] mmc: tegra: update hw tuning process Date: Fri, 1 Mar 2019 21:20:18 -0800 Message-ID: <1551504025-3541-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504034; bh=aZ12lNQfcbEPhzZP29P+vOIeiC5xLRyo38KdT0jhQ/Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cFw5MhVPwi/QA8YtAFBT/mC1xQv0PI3fNSzdBgQoi5JELvir5Zb4/N1MbW3a/46R4 BiYnkCR5a4p4B2QNx4A1DFGyeeWV3CFlm++qS4Lj72VSzXltQ/3ao3aOQA51bNcoHk KySkNpuZ04t46sBEsfU/1uQyPHd6afyqnoWS02I9F8AKhzmc6VBHw/6yssSoExYWHR WHNnLVmNE4Y1XgQlt9g2slxjhMPQf9LtfCDb3q0sH6i3dwrEsgaB80Dy8FtJpm90J7 StOaKKhjqsvdei1wW/8M7ecBK+Wt+F41u+qmPC8VOqVKlQSOJ6oi+n6ggBNt+jzaXJ TWmREitwDQJlA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch includes below HW tuning related fixes. - configures tuning parameters as per Tegra TRM - WAR fix for manual tap change - HW auto-tuning post process As per Tegra TRM, SDR50 mode tuning execution takes upto maximum of 256 tuning iterations and SDR104/HS200/HS400 modes tuning execution takes upto maximum of 128 tuning iterations. This patch programs tuning control register with maximum tuning iterations needed based on the timing along with the start tap, multiplier, and step size used by the HW tuning. Tegra210 has a known issue of glitch on trimmer output when the tap value is changed with the trimmer input clock running and the WAR is to disable card clock before sending tuning command and after sending tuning command wait for 1usec and issue SW reset followed by enabling card clock. This WAR is applicable when changing tap value manually as well. Tegra SDHCI driver has this implemented correctly for manual tap change but missing SW reset before enabling card clock during sending tuning command. Issuing SW reset during tuning command as a part of WAR and is applicable in cases where tuning is performed with single step size for more iterations. This patch includes this fix. HW auto-tuning finds the best largest passing window and sets the tap at the middle of the window. With some devices like sandisk eMMC driving fast edges and due to high tap to tap delay in the Tegra chipset, auto-tuning does not detect falling tap between the valid windows resulting in a parital window or a merged window and the best tap is set at the signal transition which is actually the worst tap location. Recommended SW solution is to detect if the best passing window picked by the HW tuning is a partial or a merged window based on min and max tap delays found from chip characterization across PVT and perform tuning correction to pick the best tap. This patch has this implemention of post tuning and uses tuned tap delay. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 218 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 217 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 46086dd43bfb..2086e0eced88 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -66,6 +66,23 @@ #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 +#define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 +#define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 +#define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 +#define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 +#define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 +#define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 +#define TRIES_40 0 +#define TRIES_128 2 +#define TRIES_256 4 +#define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 + +#define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 +#define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 +#define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC +#define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF +#define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 +#define TUNING_WORD_BIT_SIZE 32 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 #define SDHCI_AUTO_CAL_START BIT(31) @@ -97,6 +114,8 @@ struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; u32 nvquirks; + u8 min_tap_delay; + u8 max_tap_delay; }; /* Magic pull up and pull down pad calibration offsets */ @@ -136,6 +155,8 @@ struct sdhci_tegra { u32 default_trim; u32 dqs_trim; bool enable_hwcq; + unsigned long curr_clk_rate; + u8 tuned_tap_delay; }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -241,6 +262,7 @@ static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) if (is_tuning_cmd) { udelay(1); + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); tegra_sdhci_configure_card_clk(host, clk_enabled); } } @@ -722,6 +744,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) */ host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; clk_set_rate(pltfm_host->clk, host_clk); + tegra_host->curr_clk_rate = host_clk; if (tegra_host->ddr_signaling) host->max_clk = host_clk; else @@ -770,6 +793,162 @@ static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) "HS400 delay line calibration timed out\n"); } +static int tegra_sdhci_get_max_tuning_loop(struct sdhci_host *host) +{ + u32 val; + + val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); + val &= SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK; + val = val >> SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT; + if (val == TRIES_128) + return 128; + else if (val == TRIES_256) + return 256; + else + return 40; +} + +static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 num_iter, + u8 thd_up, u8 thd_low, u8 fixed_tap) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + u32 val, tun_status; + u8 word, bit, edge1, tap, window; + bool tap_result; + bool start_fail = false; + bool start_pass = false; + bool end_pass = false; + bool first_fail = false; + bool first_pass = false; + u8 start_pass_tap = 0; + u8 end_pass_tap = 0; + u8 first_fail_tap = 0; + u8 first_pass_tap = 0; + u8 total_tuning_words = num_iter / TUNING_WORD_BIT_SIZE; + + /* + * Read auto-tuned results and extract good valid passing window by + * filtering out un-wanted bubble/partial/merged windows. + */ + for (word = 0; word < total_tuning_words; word++) { + val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); + val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; + val |= word; + sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); + tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); + bit = 0; + while (bit < TUNING_WORD_BIT_SIZE) { + tap = word * TUNING_WORD_BIT_SIZE + bit; + tap_result = tun_status & (1 << bit); + if (!tap_result && !start_fail) { + start_fail = true; + if (!first_fail) { + first_fail_tap = tap; + first_fail = true; + } + + } else if (tap_result && start_fail && !start_pass) { + start_pass_tap = tap; + start_pass = true; + if (!first_pass) { + first_pass_tap = tap; + first_pass = true; + } + + } else if (!tap_result && start_fail && start_pass && + !end_pass) { + end_pass_tap = tap - 1; + end_pass = true; + } else if (tap_result && start_pass && start_fail && + end_pass) { + window = end_pass_tap - start_pass_tap; + /* discard merged window and bubble window */ + if (window >= thd_up || window < thd_low) { + start_pass_tap = tap; + end_pass = false; + } else { + /* set tap at middle of valid window */ + tap = start_pass_tap + window / 2; + tegra_host->tuned_tap_delay = tap; + return; + } + } + + bit++; + } + } + + if (!first_fail) { + WARN_ON("no edge detected, continue with hw tuned delay.\n"); + } else if (first_pass) { + /* set tap location at fixed tap relative to the first edge */ + edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; + if (edge1 - 1 > fixed_tap) + tegra_host->tuned_tap_delay = edge1 - fixed_tap; + else + tegra_host->tuned_tap_delay = edge1 + fixed_tap; + } +} + +static void tegra_sdhci_post_tuning(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; + u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; + u8 fixed_tap, start_tap, end_tap, window_width; + u8 thdupper, thdlower; + u8 num_iter; + u32 clk_rate_mhz, period_ps, bestcase, worstcase; + + /* retain HW tuned tap to use incase if no correction is needed */ + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); + tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> + SDHCI_CLOCK_CTRL_TAP_SHIFT; + if (soc_data->min_tap_delay && soc_data->max_tap_delay) { + min_tap_dly = soc_data->min_tap_delay; + max_tap_dly = soc_data->max_tap_delay; + clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; + period_ps = USEC_PER_SEC / clk_rate_mhz; + bestcase = period_ps / min_tap_dly; + worstcase = period_ps / max_tap_dly; + /* + * Upper and Lower bound thresholds used to detect merged and + * bubble windows + */ + thdupper = (2 * worstcase + bestcase) / 2; + thdlower = worstcase / 4; + /* + * fixed tap is used when HW tuning result contains single edge + * and tap is set at fixed tap delay relative to the first edge + */ + avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); + fixed_tap = avg_tap_dly / 2; + + val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); + start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; + end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & + SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; + window_width = end_tap - start_tap; + num_iter = tegra_sdhci_get_max_tuning_loop(host); + /* + * partial window includes edges of the tuning range. + * merged window includes more taps so window width is higher + * than upper threshold. + */ + if (start_tap == 0 || (end_tap == (num_iter - 1)) || + (end_tap == num_iter - 2) || window_width >= thdupper) { + pr_debug("%s: Apply tuning correction\n", + mmc_hostname(host->mmc)); + tegra_sdhci_tap_correction(host, num_iter, thdupper, + thdlower, fixed_tap); + } + } + + tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); +} + static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { @@ -778,17 +957,22 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, bool set_default_tap = false; bool set_dqs_trim = false; bool do_hs400_dll_cal = false; + u8 iter = TRIES_256; + u32 val; tegra_host->ddr_signaling = false; switch (timing) { case MMC_TIMING_UHS_SDR50: + break; case MMC_TIMING_UHS_SDR104: case MMC_TIMING_MMC_HS200: /* Don't set default tap on tunable modes. */ + iter = TRIES_128; break; case MMC_TIMING_MMC_HS400: set_dqs_trim = true; do_hs400_dll_cal = true; + iter = TRIES_128; break; case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: @@ -800,11 +984,23 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, break; } + val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); + val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | + SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | + SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); + val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | + 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | + 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); + sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); + sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); + sdhci_set_uhs_signaling(host, timing); tegra_sdhci_pad_autocalib(host); - if (set_default_tap) + if (tegra_host->tuned_tap_delay && !set_default_tap) + tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); + else tegra_sdhci_set_tap(host, tegra_host->default_tap); if (set_dqs_trim) @@ -1090,6 +1286,8 @@ static const struct sdhci_ops tegra210_sdhci_ops = { .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, .voltage_switch = tegra_sdhci_voltage_switch, .get_max_clock = tegra_sdhci_get_max_clock, + .get_max_tuning_loop_count = tegra_sdhci_get_max_tuning_loop, + .post_tuning = tegra_sdhci_post_tuning, }; static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { @@ -1110,6 +1308,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra210 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104, + .min_tap_delay = 106, + .max_tap_delay = 185, }; static const struct sdhci_ops tegra186_sdhci_ops = { @@ -1121,6 +1321,8 @@ static const struct sdhci_ops tegra186_sdhci_ops = { .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, .voltage_switch = tegra_sdhci_voltage_switch, .get_max_clock = tegra_sdhci_get_max_clock, + .get_max_tuning_loop_count = tegra_sdhci_get_max_tuning_loop, + .post_tuning = tegra_sdhci_post_tuning, .irq = sdhci_tegra_cqhci_irq, }; @@ -1150,9 +1352,23 @@ static const struct sdhci_tegra_soc_data soc_data_tegra186 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104, + .min_tap_delay = 84, + .max_tap_delay = 136, +}; + +static const struct sdhci_tegra_soc_data soc_data_tegra194 = { + .pdata = &sdhci_tegra186_pdata, + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104, + .min_tap_delay = 96, + .max_tap_delay = 139, }; static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, From patchwork Sat Mar 2 05:20:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836467 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0CE4F17E0 for ; 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Sat, 2 Mar 2019 00:20:44 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:42 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:43 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Mar 2019 21:20:43 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 2 Mar 2019 05:20:43 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:42 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 05/11] dt-bindings: mmc: tegra: document Tegra194 compatible string Date: Fri, 1 Mar 2019 21:20:19 -0800 Message-ID: <1551504025-3541-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504042; bh=LvXE/tIRMDd6Jvph5xVoFpxz86mo5Xzi+B7NL7GSoWE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Yhucr6Sa2LgK8pOmrKImqFiJ9P76s0iUTRQ3NoPwvi5P6RP/GwkSQKH3WsXDQ+DhU 4VVraMeQQBkmaKUz/kTKyhxGqnDd4bqdk/rZ09sgCzqrPFrYDzNPPpkbjkWp0CaAT6 6TMYNZlg5lsGWPGzunsBpr0HuEPR+oDyhPF6+fBjT7k9mgfV64Yojj2Rql6PZ2Jswv ylTiRMsgVTNiESUm2Y6aRzXilbTU17biyJqqEz2Lv8W46Z+22DfffILtUHYC9h9IEO Etjqu0ViP8Q4itJIC+rkr7f8+7P0IdiVNGaegKuFCd0Ib0GjFx1DZUiosk93m46TC2 DO4noBxCUNOTw== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHCI controller of Tegra194 is similar to SDHCI controller in Tegra186. This patch documents Tegra194 sdhci compatible string. Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 2cecdc71d94c..2cf3affa1be7 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -14,6 +14,7 @@ Required properties: - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 - "nvidia,tegra210-sdhci": for Tegra210 - "nvidia,tegra186-sdhci": for Tegra186 + - "nvidia,tegra194-sdhci": for Tegra194 - clocks : Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets : Must contain an entry for each entry in reset-names. From patchwork Sat Mar 2 05:20:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836465 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB051922 for ; Sat, 2 Mar 2019 05:21:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A87B92D759 for ; Sat, 2 Mar 2019 05:21:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9D09D2D789; Sat, 2 Mar 2019 05:21:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52A482D759 for ; Sat, 2 Mar 2019 05:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728017AbfCBFUr (ORCPT ); Sat, 2 Mar 2019 00:20:47 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9830 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727985AbfCBFUr (ORCPT ); Sat, 2 Mar 2019 00:20:47 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:55 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:46 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Mar 2019 21:20:46 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:46 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:45 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:45 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:45 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , "Sowjanya Komatineni" Subject: [PATCH V1 06/11] arm64: tegra: fix default tap and trim values Date: Fri, 1 Mar 2019 21:20:20 -0800 Message-ID: <1551504025-3541-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504055; bh=qUjFbWXCUApzKfPArZ5J7ifVPmb5w+NFtEc2jWgZ0SQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=fJ9a2qgQsFaJIFeBeUXPQtpEPNrH258npT+ocWclkQITQJ4YkiHtCUG/L/crPbRXR NYNrQVaUXe32tQfIcsQLOmNR2qU7aJsLeMbo5IjtRQoGmcun0ZHim+YclFajk1ARaa Z+uUpfIN3/e0ENY99Cf+vfyBAXfErQa9TSuQuH5g4Gmsbeoq9Pkr+4MLw4AnnLsZwd upN5beLV/eYAmqVuYqdeJthTrVoQdu2KO3Aoa8xdLHmBK/Q1bJqV93NvUyc0P7I7IE RzY+ZIAZ9ah2WHAlVw2y65TfFqu0SKXujLmx8IQdBqKQ5bHnqiS9iSwMGjtzle+9gt E/Th7RiCejdRg== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Default tap and trim values are incorrect for Tegra186 SDMMC4. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 97aeb946ed5e..472f55fe9488 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -317,8 +317,8 @@ nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0x9>; + nvidia,default-tap = <0x9>; + nvidia,default-trim = <0x5>; nvidia,dqs-trim = <63>; mmc-hs400-1_8v; status = "disabled"; From patchwork Sat Mar 2 05:20:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836461 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4F9F7922 for ; Sat, 2 Mar 2019 05:21:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3DC812D759 for ; Sat, 2 Mar 2019 05:21:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 325DF2D789; Sat, 2 Mar 2019 05:21:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CEE9F2D759 for ; Sat, 2 Mar 2019 05:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728100AbfCBFUz (ORCPT ); Sat, 2 Mar 2019 00:20:55 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17585 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728060AbfCBFUt (ORCPT ); Sat, 2 Mar 2019 00:20:49 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:43 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:49 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Mar 2019 21:20:49 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:48 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 2 Mar 2019 05:20:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:48 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 07/11] mmc: cqhci: add quirk for setting DCMD CMD_TIMING Date: Fri, 1 Mar 2019 21:20:21 -0800 Message-ID: <1551504025-3541-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504043; bh=smkvq17VQm70eK2SbYDgI2Z1aLuFj6uiizFN4E5yrd0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=P0q1FNJuIMd61AvhJV2AFdje3MPyZgy8vbyU6ZixYZ+Lw86XHouLJH9pYAujBIB7D TBNqzM4ZoA13LYhEuE0aOdR4AYTsyHEfposIMw3y3H7RRJrjnuiOBbCr7GHi+TWr66 r6m//27yOeMH/B7id+5FWhKosRD5DRu7SN7H2Ja+3/ICBmQgHDB2kwjqAQgKbusaqv L9LVb6HapDH+EpnX8J5V/ThMFF/0gkDtSlpt7muJ+yiELm7fcI44ZCg2FrcC4S9RpT Itc0UCoKUNOeMWn1uqgFREPlOAADp24JRJifrPFjtVkTQjEJxGvosZSmBKWT0pXTMp u4m5hchxmP4ZA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a quirk for setting CMD_TIMING to 1 in descriptor for DCMD with R1B response type to allow the command to be sent to device during data activity or busy time. Tegra186 CQHCI host has bug where it selects DATA_PRESENT_SELECT to 1 by CQHCI controller for DCMDs with R1B response type and since DCMD does not trigger any data transfer, DCMD task complete happens leaving the DATA FSM of host controller in wait state for data. This effects the data transfer task issued after R1B DCMD task and no interrupt is generated for the data transfer task. SW WAR for this issue is to set CMD_TIMING bit to 1 in DCMD task descriptor and as DCMD task descriptor preparation is done by cqhci driver, this patch adds cqequirk to handle this. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/cqhci.c | 5 ++++- drivers/mmc/host/cqhci.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c index a8af682a9182..b34c07125f32 100644 --- a/drivers/mmc/host/cqhci.c +++ b/drivers/mmc/host/cqhci.c @@ -521,7 +521,10 @@ static void cqhci_prep_dcmd_desc(struct mmc_host *mmc, } else { if (mrq->cmd->flags & MMC_RSP_R1B) { resp_type = 0x3; - timing = 0x0; + if (cq_host->quirks & CQHCI_QUIRK_CMD_TIMING_R1B_DCMD) + timing = 0x1; + else + timing = 0x0; } else { resp_type = 0x2; timing = 0x1; diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index 9e68286a07b4..f96d8565cc07 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -170,6 +170,7 @@ struct cqhci_host { u32 quirks; #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1 +#define CQHCI_QUIRK_CMD_TIMING_R1B_DCMD 0x2 bool enabled; bool halted; From patchwork Sat Mar 2 05:20:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17F42922 for ; Sat, 2 Mar 2019 05:21:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 071A82D759 for ; Sat, 2 Mar 2019 05:21:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EFCE62D789; Sat, 2 Mar 2019 05:21:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B6622D759 for ; Sat, 2 Mar 2019 05:21:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728087AbfCBFUy (ORCPT ); Sat, 2 Mar 2019 00:20:54 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15121 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727985AbfCBFUx (ORCPT ); Sat, 2 Mar 2019 00:20:53 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:51 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:52 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:52 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:51 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 08/11] mmc: tegra: add Tegra186 WAR for CQE Date: Fri, 1 Mar 2019 21:20:22 -0800 Message-ID: <1551504025-3541-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504051; bh=1B+N7uE+HVqMozipQL4sMXKkt7WcnsWeT4TSmtt5PYo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=VZTRqa9sAIkv/NVS8AO5Ymz3T2BA+H6Z0Xc+Z7oQRHovXrOr3cE3LWAOvu0sckU/q Cg9CZd4K3Byo4o5OT3E2oMIYOx57fScP+sP+rqQQjgWEIQxxFbH2mTjQYVsKIHf3pP IS9VgXdNwfDBDt4SHhmOdYemgbnqxCTm5KY+Ia4YiyGB6/qogLBMkK4b+Jj8nLE34h 4vSUzMoedLOQGxlhI1GLx+OE0L15ImqV7xOUctn45GSYM0QoqJLYVmzLgwP7DKeqGR gobFcTsgi8oQxa49N9k+51gcMCqSn6X08dW959cCx/itYchCVofaCYTsp0gPoIGFd5 pfT6ltka32Wkw== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra186 design has a known bug where CQE does not generated task complete interrupt for data transfer tasks issued after DCMD task with R1b response type and results in timeout. SW WAR is to set CMD_TIMING to 1 in task descriptor for DCMDs with R1b response type. This bug and SW WAR is applicable only for Tegra186 and not for Tegra194. This patch adds this WAR to Tegra186. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2086e0eced88..2b63626dc2fa 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -116,6 +116,7 @@ struct sdhci_tegra_soc_data { u32 nvquirks; u8 min_tap_delay; u8 max_tap_delay; + u32 cqequirks; }; /* Magic pull up and pull down pad calibration offsets */ @@ -1354,6 +1355,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra186 = { NVQUIRK_ENABLE_SDR104, .min_tap_delay = 84, .max_tap_delay = 136, + .cqequirks = CQHCI_QUIRK_CMD_TIMING_R1B_DCMD, }; static const struct sdhci_tegra_soc_data soc_data_tegra194 = { @@ -1383,6 +1385,7 @@ static int sdhci_tegra_add_host(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; struct cqhci_host *cq_host; bool dma64; int ret; @@ -1407,6 +1410,7 @@ static int sdhci_tegra_add_host(struct sdhci_host *host) cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; cq_host->ops = &sdhci_tegra_cqhci_ops; + cq_host->quirks = soc_data->cqequirks; dma64 = host->flags & SDHCI_USE_64_BIT_DMA; if (dma64) From patchwork Sat Mar 2 05:20:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836459 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C5AA17E0 for ; Sat, 2 Mar 2019 05:21:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A83F2D759 for ; Sat, 2 Mar 2019 05:21:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E9902D789; Sat, 2 Mar 2019 05:21:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEAEA2D759 for ; Sat, 2 Mar 2019 05:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727428AbfCBFVN (ORCPT ); Sat, 2 Mar 2019 00:21:13 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9841 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728120AbfCBFU4 (ORCPT ); Sat, 2 Mar 2019 00:20:56 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:21:04 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:55 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:55 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:55 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:54 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 09/11] mmc: cqhci: add CQHCI_SSC1 register CBC field mask Date: Fri, 1 Mar 2019 21:20:23 -0800 Message-ID: <1551504025-3541-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504064; bh=wkx3HuTJxIWb28BfsCb9mlzWzWFwJ4pnX4Z3RHL7NaQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cnAZ9UVaGYuv0VtH4efT6tOehUYcwsVVjfb87WvWQC2whKsdqoswASKC0jqGeWCXU vCznwDwAp3D0KfwDocygT+FZdRECpGC3OTyontolHFV1ZqlgpDQc4snKjRjT+T27j2 kvtwZqFuinZn1pvCc6TaHWohTQpKqXRsr5rT03HBRIZePApImfpM8Mwb/8gvc95bvX VE4Rjwu/hifyw3T/aUn4giBQN4D1TfXyGX8G4tX+FYVP2zUKR7pHSU9fvb23LmainE pHWO6b31A0fzHAVXiXi79S8ZUKM/J+S4/1VZbYEy9n88oLczbdwY5moanzH7j/gnwL DU/rWcQPlVBfA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds define for CBC field mask of the register CQHCI_SSC1. Signed-off-by: Sowjanya Komatineni Acked-by: Adrian Hunter --- drivers/mmc/host/cqhci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index f96d8565cc07..f1dc48c7436f 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -88,6 +88,7 @@ /* send status config 1 */ #define CQHCI_SSC1 0x40 +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) /* send status config 2 */ #define CQHCI_SSC2 0x44 From patchwork Sat Mar 2 05:20:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836457 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6015922 for ; Sat, 2 Mar 2019 05:21:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C2A2E2D759 for ; Sat, 2 Mar 2019 05:21:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B67FB2D789; Sat, 2 Mar 2019 05:21:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 427522D759 for ; Sat, 2 Mar 2019 05:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728170AbfCBFVA (ORCPT ); Sat, 2 Mar 2019 00:21:00 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15131 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728157AbfCBFU7 (ORCPT ); Sat, 2 Mar 2019 00:20:59 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:57 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:58 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:58 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:57 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:57 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:57 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 10/11] mmc: tegra: fix CQE resume sequence Date: Fri, 1 Mar 2019 21:20:24 -0800 Message-ID: <1551504025-3541-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504057; bh=DV4Yb0Gbx+cmnhT168bdb37TlCyRQtmweHXGjuQjnMI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=TUhlvNKEGdNOAR2JRRv4vyQ3wdxsvRPyLsKSIKqq+PTQbXqdy6+Ov/i4QKBn3aKnN pt4iiIimRCbPCz38qEYqUls6CyAhXKyQdkiexgQV6MGkOBBNvufWnJ9wYIHmq9OmNz 6Q4tuqcNg9cyPDPWG8t7udHNUMAyZxccSJ0ePjBJHXJQaUcqsXjq8Rl2Msl1zd3/7F 8HLEGCMAjX9dsnDhyi2/EuZt6iAi4m8FXZ8rsCimi1kTjiLkDPsbwN1UMNhL83WMmA 86eu8iOCSWy35XpaZ653sNxulAs2TDGnREBg0ztoT3Mi5tIPj53rdeaK7wvF+0mcjD OGM4Vs+sisMWA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra CQHCI/SDHCI design prevents write access to SDHCI block size register when CQE is enabled and unhalted. CQHCI driver enabled CQE prior to invoking sdhci_cqe_enable which violates this Tegra specific host requirement. This patch fixes this by configuring sdhci block registers prior to CQE unhalt. Signed-off-by: Sowjanya Komatineni Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 71 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 62 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2b63626dc2fa..7063cfcdc590 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1126,23 +1126,75 @@ static void tegra_sdhci_voltage_switch(struct sdhci_host *host) tegra_host->pad_calib_required = true; } +static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) +{ + struct mmc_host *mmc = cq_host->mmc; + u8 ctrl; + ktime_t timeout; + bool timed_out; + + /* + * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to + * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need + * to be re-configured. + * Tegra CQHCI/SDHCI prevents write access to block size register when + * CQE is unhalted. So handling CQE resume sequence here to configure + * SDHCI block registers prior to exiting CQE halt state. + */ + if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && + cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { + sdhci_cqe_enable(mmc); + writel(val, cq_host->mmio + reg); + timeout = ktime_add_us(ktime_get(), 50); + while (1) { + timed_out = ktime_compare(ktime_get(), timeout) > 0; + ctrl = cqhci_readl(cq_host, CQHCI_CTL); + if (!(ctrl & CQHCI_HALT) || timed_out) + break; + } + /* + * CQE usually resumes very quick, but incase if Tegra CQE + * doesn't resume retry unhalt. + */ + if (timed_out) + writel(val, cq_host->mmio + reg); + } else { + writel(val, cq_host->mmio + reg); + } +} + static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) { struct cqhci_host *cq_host = mmc->cqe_private; - u32 cqcfg = 0; + u32 val; /* - * Tegra SDMMC Controller design prevents write access to BLOCK_COUNT - * registers when CQE is enabled. + * Tegra CQHCI/SDMMC design prevents write access to sdhci block size + * register when CQE is enabled and unhalted. + * CQHCI driver enables CQE prior to activation, so disable CQE before + * programming block size in sdhci controller and enable it back. */ - cqcfg = cqhci_readl(cq_host, CQHCI_CFG); - if (cqcfg & CQHCI_ENABLE) - cqhci_writel(cq_host, (cqcfg & ~CQHCI_ENABLE), CQHCI_CFG); + if (!cq_host->activated) { + val = cqhci_readl(cq_host, CQHCI_CFG); + if (val & CQHCI_ENABLE) + cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), + CQHCI_CFG); + sdhci_cqe_enable(mmc); + if (val & CQHCI_ENABLE) + cqhci_writel(cq_host, val, CQHCI_CFG); + } - sdhci_cqe_enable(mmc); + /* + * CMD CRC errors are seen sometimes with some eMMC devices when status + * command is sent during transfer of last data block which is the + * default case as send status command block counter (CBC) is 1. + * So changing send status command block counter (CBC) to 0 to allow + * send status command only when the data lines are idle. + */ + val = cqhci_readl(cq_host, CQHCI_SSC1); + val &= ~CQHCI_SSC1_CBC_MASK; + cqhci_writel(cq_host, val, CQHCI_SSC1); - if (cqcfg & CQHCI_ENABLE) - cqhci_writel(cq_host, cqcfg, CQHCI_CFG); } static void sdhci_tegra_dumpregs(struct mmc_host *mmc) @@ -1167,6 +1219,7 @@ static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { .enable = sdhci_tegra_cqe_enable, .disable = sdhci_cqe_disable, .dumpregs = sdhci_tegra_dumpregs, + .write_l = tegra_cqhci_writel, }; static const struct sdhci_ops tegra_sdhci_ops = { From patchwork Sat Mar 2 05:20:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C8138922 for ; Sat, 2 Mar 2019 05:21:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A9C432D759 for ; Sat, 2 Mar 2019 05:21:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C1ED2D789; Sat, 2 Mar 2019 05:21:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09E572D759 for ; Sat, 2 Mar 2019 05:21:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728216AbfCBFVD (ORCPT ); Sat, 2 Mar 2019 00:21:03 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9852 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728205AbfCBFVC (ORCPT ); Sat, 2 Mar 2019 00:21:02 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:21:11 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:21:01 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:21:01 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:21:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:21:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:21:00 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 11/11] arm64: tegra: enable command queue for tegra186 sdmmc4 Date: Fri, 1 Mar 2019 21:20:25 -0800 Message-ID: <1551504025-3541-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504071; bh=CYolxqoLCYY9GqQxqJVXC12HnxUs/oA/8PqPnDjGK/E=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=b6xQa4PKmW5qlsQ+T/+sCCfAeTt0h6xJT8CUsFGdI3XjXJJlCwowrLZphs7OvESOD mEZBZmFeYO+CosM5gug99eMJIucfnr5tUWtfkP97sJ0GKzG7OTZij2qz3alKw9aUj/ 1TAunQhQtQkEU/W9jfQFDYy8KJxRdUoiFhfntPtRFmnkkpCD7I74VVt8+bar3S/8rD tmuFyACgRHGXAX+6XBaLvgFA9HNBeCQBYPuWe6WMayriicw33h9qPU/Zyu0c0W/HZ5 TB+j9aaoZtaKxkUYEiFx3GstcRF+3w7/fQz7ac2IpjAovc7wO5K24esmj36Kg7TRN8 /KyapydbpiYkg== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enables command queue support for Tegra186 SDMMC4. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 472f55fe9488..6e2b6ce99df2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -321,6 +321,7 @@ nvidia,default-trim = <0x5>; nvidia,dqs-trim = <63>; mmc-hs400-1_8v; + supports-cqe; status = "disabled"; };