From patchwork Tue Jul 9 09:55:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tiezhu Yang X-Patchwork-Id: 13727570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76A64C2BD09 for ; Tue, 9 Jul 2024 09:55:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=R66JQX115Ohcb5kTe0GyBRhhsOYk04izeoe/Y+2p8Z8=; b=M2gtQ1Q7MjzTgR6aQQ46hjbIxD yHKyDGy2mTfWvJ68kC6ufiAl9SzVtvGfFuViTysP38/8lKK+wG+YHsgNqfdXIsSMDS0aUSRw4151I 6+Y1jdVAeyjp3d5mj7Y17VNQAkGYxHU//6SOL/1Wq/qOkDkYm490I+Gu16hpFZVp9HN5ZDjazSamr M58Fy2EPwImS+3ebn/4gQgXMVE03qfXhBvUKbGd7CDB/6XBvCO4aQE9/ySSACY+5rbOW1sOG2Iz7l 8GfokFd3xqb81AOzZugcyi9/oYOYGmbnSuNIkKBmTCcPt+OzwZ1HWfWnenVYdPL1WUfkjW2g/8/yU KVYwKx7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sR7ZW-00000006hNK-3Oo7; Tue, 09 Jul 2024 09:55:42 +0000 Received: from mail.loongson.cn ([114.242.206.163]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sR7Z2-00000006hDH-0NEG for linux-arm-kernel@lists.infradead.org; Tue, 09 Jul 2024 09:55:15 +0000 Received: from loongson.cn (unknown [113.200.148.30]) by gateway (Coremail) with SMTP id _____8Dxfev8CI1mVGACAA--.7182S3; Tue, 09 Jul 2024 17:55:08 +0800 (CST) Received: from linux.localdomain (unknown [113.200.148.30]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxqsb6CI1mgt1AAA--.17645S3; Tue, 09 Jul 2024 17:55:08 +0800 (CST) From: Tiezhu Yang To: Will Deacon , Mark Rutland , Russell King , Catalin Marinas , Oleg Nesterov , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] perf: Add perf_event_attr::bp_priv Date: Tue, 9 Jul 2024 17:55:04 +0800 Message-ID: <20240709095506.9691-2-yangtiezhu@loongson.cn> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240709095506.9691-1-yangtiezhu@loongson.cn> References: <20240709095506.9691-1-yangtiezhu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cxqsb6CI1mgt1AAA--.17645S3 X-CM-SenderInfo: p1dqw3xlh2x3gn0dqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoW7uFWkAF1rXr47Cr1DXF1DJwc_yoW8Ww4Upr Zxurn8K3ykJa4F9w13G3yDZw1UJws7W39Fga43Kw4Yyr43Z393uw1kWFyav3Z8Zw1UAayF qwnIgFyDta4UXagCm3ZEXasCq-sJn29KB7ZKAUJUUUU7529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUB2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVWxJr0_GcWln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12 xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q 6rW5McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64 vIr41lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1l4IxYO2xFxVAFwI0_Jrv_JF1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8Gjc xK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0 cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8V AvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E 14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUxhiSDUUUU X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_025512_504167_7D0E0EEA X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When developing hardware watchpoint on LoongArch, we want to set the same privilege passed by the ptrace user data, but there is no bridge to save this value like bp_addr, bp_type and bp_len. This is a common issue for the archs which have privilege level of breakpoint. Add a member "bp_priv" which lives in a union on config3 at the end of the uapi struct perf_event_attr to make a bridge between ptrace and hardware breakpoint. This is preparation for later patch on some archs such as ARM, ARM64 and LoongArch which have privilege level of breakpoint. Signed-off-by: Tiezhu Yang --- include/uapi/linux/perf_event.h | 5 ++++- kernel/events/hw_breakpoint.c | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 3a64499b0f5d..abe8da7a1f60 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -521,7 +521,10 @@ struct perf_event_attr { */ __u64 sig_data; - __u64 config3; /* extension of config2 */ + union { + __u8 bp_priv; /* privilege level of breakpoint */ + __u64 config3; /* extension of config2 */ + }; }; /* diff --git a/kernel/events/hw_breakpoint.c b/kernel/events/hw_breakpoint.c index 6c2cb4e4f48d..3ad16b226e4f 100644 --- a/kernel/events/hw_breakpoint.c +++ b/kernel/events/hw_breakpoint.c @@ -754,6 +754,7 @@ static void hw_breakpoint_copy_attr(struct perf_event_attr *to, to->bp_addr = from->bp_addr; to->bp_type = from->bp_type; to->bp_len = from->bp_len; + to->bp_priv = from->bp_priv; to->disabled = from->disabled; } From patchwork Tue Jul 9 09:55:05 2024 Content-Type: text/plain; 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The value of ctrl->privilege saved in decode_ctrl_reg() can be used in arch_build_bp_info(), there is no need to check bp virtual address to assign value for hw->ctrl.privilege, just make use of "bp_priv" in the struct perf_event_attr to save the privilege of access control via ptrace for hardware breakpoint. Signed-off-by: Tiezhu Yang --- arch/arm/kernel/hw_breakpoint.c | 4 +--- arch/arm/kernel/ptrace.c | 2 ++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index a12efd0f43e8..7720d39473d9 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -568,9 +568,7 @@ static int arch_build_bp_info(struct perf_event *bp, hw->address = attr->bp_addr; /* Privilege */ - hw->ctrl.privilege = ARM_BREAKPOINT_USER; - if (arch_check_bp_in_kernelspace(hw)) - hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV; + hw->ctrl.privilege = attr->bp_priv; /* Enabled? */ hw->ctrl.enabled = !attr->disabled; diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index c421a899fc84..0d6d6b2a57a0 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -422,6 +422,7 @@ static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type) attr.bp_addr = 0; attr.bp_len = HW_BREAKPOINT_LEN_4; attr.bp_type = type; + attr.bp_priv = ARM_BREAKPOINT_USER; attr.disabled = 1; return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, @@ -530,6 +531,7 @@ static int ptrace_sethbpregs(struct task_struct *tsk, long num, attr.bp_len = gen_len; attr.bp_type = gen_type; + attr.bp_priv = ctrl.privilege; attr.disabled = !ctrl.enabled; } From patchwork Tue Jul 9 09:55:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tiezhu Yang X-Patchwork-Id: 13727569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69241C2BD09 for ; Tue, 9 Jul 2024 09:55:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Tue, 09 Jul 2024 09:55:14 +0000 Received: from loongson.cn (unknown [113.200.148.30]) by gateway (Coremail) with SMTP id _____8DxzfD9CI1mYmACAA--.7493S3; Tue, 09 Jul 2024 17:55:09 +0800 (CST) Received: from linux.localdomain (unknown [113.200.148.30]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxqsb6CI1mgt1AAA--.17645S5; Tue, 09 Jul 2024 17:55:09 +0800 (CST) From: Tiezhu Yang To: Will Deacon , Mark Rutland , Russell King , Catalin Marinas , Oleg Nesterov , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] arm64: hw_breakpoint: Save privilege of access control via ptrace Date: Tue, 9 Jul 2024 17:55:06 +0800 Message-ID: <20240709095506.9691-4-yangtiezhu@loongson.cn> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240709095506.9691-1-yangtiezhu@loongson.cn> References: <20240709095506.9691-1-yangtiezhu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cxqsb6CI1mgt1AAA--.17645S5 X-CM-SenderInfo: p1dqw3xlh2x3gn0dqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoW7CF18JryDGr4kur18ZrWrJFc_yoW8tw4Dpr ZxAw1qqw4UGa1UGayaqws3Zan8GwsFgryUXryDG3ySkr15Zr1fWrykGrnxurZ3JrW0q3y0 v3yDXr15Wa17X3XCm3ZEXasCq-sJn29KB7ZKAUJUUUU7529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUB2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVWxJr0_GcWln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12 xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q 6rW5McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64 vIr41lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1l4IxYO2xFxVAFwI0_Jrv_JF1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8Gjc xK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0 cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8V AvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E 14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUxhiSDUUUU X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_025512_494370_C60EE745 X-CRM114-Status: GOOD ( 15.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In the current code, decode_ctrl_reg() saves the privilege of access control passed by the ptrace user data, but it is not used anymore, arch_build_bp_info() checks whether bp virtual address is in kernel space to construct hw->ctrl.privilege, it seems not reasonable. The value of ctrl->privilege saved in decode_ctrl_reg() can be used in arch_build_bp_info(), there is no need to check bp virtual address to assign value for hw->ctrl.privilege, just make use of "bp_priv" in the struct perf_event_attr to save the privilege of access control via ptrace for hardware breakpoint. Signed-off-by: Tiezhu Yang --- arch/arm64/kernel/hw_breakpoint.c | 11 ++--------- arch/arm64/kernel/ptrace.c | 2 ++ 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index 722ac45f9f7b..06e34bcdcf92 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -486,15 +486,8 @@ static int arch_build_bp_info(struct perf_event *bp, /* Address */ hw->address = attr->bp_addr; - /* - * Privilege - * Note that we disallow combined EL0/EL1 breakpoints because - * that would complicate the stepping code. - */ - if (arch_check_bp_in_kernelspace(hw)) - hw->ctrl.privilege = AARCH64_BREAKPOINT_EL1; - else - hw->ctrl.privilege = AARCH64_BREAKPOINT_EL0; + /* Privilege */ + hw->ctrl.privilege = attr->bp_priv; /* Enabled? */ hw->ctrl.enabled = !attr->disabled; diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 0d022599eb61..3b37c4a2e0d4 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -309,6 +309,7 @@ static struct perf_event *ptrace_hbp_create(unsigned int note_type, attr.bp_addr = 0; attr.bp_len = HW_BREAKPOINT_LEN_4; attr.bp_type = type; + attr.bp_priv = AARCH64_BREAKPOINT_EL0; attr.disabled = 1; bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); @@ -352,6 +353,7 @@ static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, attr->bp_len = len; attr->bp_type = type; attr->bp_addr += offset; + attr->bp_priv = ctrl.privilege; return 0; }