From patchwork Tue Jul 9 10:45:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13727655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7AC3C2BD09 for ; Tue, 9 Jul 2024 10:45:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD6B110E4F4; Tue, 9 Jul 2024 10:45:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="cWXNcb92"; dkim-atps=neutral Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by gabe.freedesktop.org (Postfix) with ESMTPS id 02D4C10E4ED for ; Tue, 9 Jul 2024 10:45:35 +0000 (UTC) Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a77c7d3e8bcso492623566b.1 for ; Tue, 09 Jul 2024 03:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720521934; x=1721126734; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IGu0LuUjGKiWzipHAvenbBISpRzy/JWKn/Q0VCWcD/s=; b=cWXNcb92L2my04ewz9fIP/Vb5nm4zvnF/SAfONINcThdNunpJtDl1Ka3v5zjzx0Ax8 FaD0c/bnoQILdp+0tEMjONK9SmbzTZVA67V89cBN5eT1CI0fFZfDjSYzDfCDQY1jEvQ7 PVAMu6FFL/+C1HSUYUvHD+rDPzkcs7WM7yPvV40KIiHdaEAGGmeCk+P6Yz4X/3/5gmiY qgrCFLoRUoi+nXxrHakkQ/FNr01jhNp4dtM+6DT53WMUNJ4nQhUC6Q3eDpSUe1Q9hB3s Ry3CPfCGecOuPHNl70+/B9rRkeOnNT8Nt5Nlz+AHwJsT7FVoQdB4fELuzbaGPHjD4gJN 6GDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720521934; x=1721126734; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IGu0LuUjGKiWzipHAvenbBISpRzy/JWKn/Q0VCWcD/s=; b=YI5lR+1Hqw/d4WZB8uYZXrF+rPVNOp1aG6+qiuMwPQpgsEIzcDaSvoKvHSKWPqnTcJ 1kpTC5wUtp+qtGkwnWt7S3IHtzBzT3a9kmXBiNgntyJawbV0GYvPBo6ShjOff8e9CN1e J+gieyPF8ETaji5WpnOVwg7O9ys+Ghqc3TwLUDC3N0AI6PgOgBuQth9x9Mw7IBVQc3Cf l9kC8HwrumKOU//o5Pxpoaa0xLxyHCZYo9Kbvt04MTRQedLzxelOvR3SBGdvLOUIDRhg 9xFNTUqkXfC6Xf+ziqqN0q3F+D+Rsk54vCg3VuUnhf8UakLeGRx27YJTEF5nO1ooEkTE Es9Q== X-Forwarded-Encrypted: i=1; AJvYcCVt74ukEHfgpZQXlvhf3x2HymAbtUhswQgNHN2q9mh3UvIYHwK5ndssooZ/F/7SXHJAgX9uUnO0xFCcN57RO/IZsPrbSIcYlixHb5JFHP3t X-Gm-Message-State: AOJu0YwK1cz9z2ryqHUZYGqT8Ly5J3+IF+6BTHCX0IsosVhv9WSzO4Ie j4S6TrJ1bT2h3x2sztcqopJrhttPj6ffST22cBiKqsoCxYb7DLF4GISJXfVVGCc= X-Google-Smtp-Source: AGHT+IFojiSJMtNFkbwjsZN8NaRCsi8T66KA4mNJvMJYW4MrWNwyi3ZVaOA3AheA7mNLL9bhT2f25w== X-Received: by 2002:a17:907:720c:b0:a77:c5a5:f662 with SMTP id a640c23a62f3a-a780b68a9camr184732266b.12.1720521934301; Tue, 09 Jul 2024 03:45:34 -0700 (PDT) Received: from [192.168.105.194] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:33 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:29 +0200 Subject: [PATCH v5 1/5] drm/msm/adreno: Implement SMEM-based speed bin MIME-Version: 1.0 Message-Id: <20240709-topic-smem_speedbin-v5-1-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=6084; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EZnPsbf895Nk5+GhF8GX16MJZewwBwjtmiFmsqKVj/E=; b=ofzGt665lRV73DHN1FYY/bCFj4utkgtRqb78xzJO4AhiNNAaX88SPIUrJ7rZTp+qwl8D+dgx/ Qjtzuwfx42BCGsI3SBnFhMjoYrnCMLAynqXFghKGFuzriKzoFSYGeJk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++++----- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 42 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++- 4 files changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index bcaec86ac67a..0d8682c28ba4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2117,18 +2117,20 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* - * -ENOENT means that the platform doesn't support speedbin which is - * fine + * -ENOENT/EOPNOTSUPP means that the platform doesn't support speedbin + * which is fine */ - if (ret == -ENOENT) { + if (ret == -ENOENT || ret == -EOPNOTSUPP) { return 0; } else if (ret) { dev_err_probe(dev, ret, @@ -2283,7 +2285,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index cfc74a9e2646..0842ea76e616 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1c6626747b98..cf6652c4439d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1061,9 +1064,40 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret != -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n"); + +#ifdef CONFIG_QCOM_SMEM + u32 fcode; + + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret = qcom_smem_get_feature_code(&fcode); + if (!ret) + *fuse = ADRENO_SKU_ID(fcode); + else if (ret != -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return ret; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1102,9 +1136,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 1ab523a163a0..0d629343ebb4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -79,6 +79,10 @@ struct adreno_reglist { struct adreno_speedbin { uint16_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (fcode) + uint16_t speedbin; }; @@ -555,7 +559,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU From patchwork Tue Jul 9 10:45:30 2024 Content-Type: text/plain; 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:35 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:30 +0200 Subject: [PATCH v5 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 MIME-Version: 1.0 Message-Id: <20240709-topic-smem_speedbin-v5-2-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=1480; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qLAOTrSFtuBecm3+EwggXg43xqGrGY4RLrmT8vpNaLU=; b=felzT5CFkBH3CSD4+amuMEw8IiUfz80JoigCu+pRFOy5BlFTjJygWaDDjwtuKGHNKBhm30wZg NBUe1/jVPMZBLTAjuLJBMe6dl3+f4IGUf2f654Aut78+wx/zTfxZ3ug X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 68ba9aed5506..e3322f6aec13 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" +#include +#include + static const struct adreno_reglist a612_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1209,6 +1212,11 @@ static const struct adreno_info a7xx_gpus[] = { .gmu_chipid = 0x7020100, }, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family = ADRENO_7XX_GEN2, From patchwork Tue Jul 9 10:45:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13727656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AACE2C3DA41 for ; Tue, 9 Jul 2024 10:45:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E6E1E10E4F6; Tue, 9 Jul 2024 10:45:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ljkNMmy+"; dkim-atps=neutral Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29BCC10E4F6 for ; Tue, 9 Jul 2024 10:45:57 +0000 (UTC) Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a77c4309fc8so533864566b.3 for ; Tue, 09 Jul 2024 03:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720521955; x=1721126755; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OCdrWwyibH7SidMAd8gXxhcbnOnPffTnyQEY5fVW104=; b=ljkNMmy+Fx9bRsxPdGhNbPD/FqrC3dllpldI3xVYt31ggUukvdOyGWrQgPKBGP5VfH tej9YV1k2bSd6qsS65U1HvYvTAxjSDvRRrzDsYGVNZHDYFqGo5C0majrmayKPxzKiQkP X0cOxZx8Gx1A+o8TO/KGaWpPQKkLqVMKcmo8UfW2uMwzMJc71MWm1JXdKMFw4cKKUKTL M7DG88eqU66nXZnCUkYwsmzii91CKffv1WRHf29yK8XUPKdj15E2OMEnRvJIFsYKI/bs RJDWOL+EZkrStxrLdgs3Y69eYhrbpirB30YVWKUaxaa8Hs5vtoqIZKQbJXKOaGCdTe+0 XS+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720521955; x=1721126755; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OCdrWwyibH7SidMAd8gXxhcbnOnPffTnyQEY5fVW104=; b=oO9sE++9vn1gns/gpYjXPl1W6cN9KFHROpf2e4NFjTuKQowq2pKBtFf8zbw2pch48x 5ht6kvyCXBiKF+7tMBXE/CcOkkWVYxGbx8v7ZgK9xxdbut8RjVCeGFPF1UpOLha31aMU PjaURvv4qjQoI2MKaPqVhDZ19tksf3F2hTaeW/N85QbUEN8CCx6jTAiixki4sOTgY9ln 17dCRN1NAkCDLsgVaSEs0fijgKrMoJZdgvtJvUIMMQ8vMVXXsYpYweToZt2HkmKp14Pb HsxDHUacOp1LYs04MuLsgWQ/LFxn2cdbOsigfasoy8zRThdRBGxSdbUrJSBNUlgVR+oZ Dzzw== X-Forwarded-Encrypted: i=1; AJvYcCWAsBvJKENXU4As9H9x/9vXqu6zA0eGkFpOToyOZ5zNv3jd4Hmp2qhRiJTS20wRulJ5+RQ2+KaldnazQo8NrFwn5BF9bZSJw+inqhS33M5k X-Gm-Message-State: AOJu0Yx4coa4OfoB8BLSjVVcpLSZpxcomJKUM1jurkOX10Nd2R0xkwe6 5EeuH4S5A5vcWJWougX62resEDLtLh9aJ52wNCiMEBDOANY6S/i0OnO1zLmIM9c= X-Google-Smtp-Source: AGHT+IEnddeAQttVIjPlE5QwA1Ejq9Sgylm5fg+WQ2PeIGDvlnpy6g/83mPoUVgnq4+Ux2PORfhdCA== X-Received: by 2002:a17:907:3f20:b0:a72:554d:82af with SMTP id a640c23a62f3a-a780df5e5fbmr146263266b.20.1720521938009; Tue, 09 Jul 2024 03:45:38 -0700 (PDT) Received: from [192.168.105.194] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:37 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:31 +0200 Subject: [PATCH v5 3/5] drm/msm/adreno: Define A530 speed bins explicitly MIME-Version: 1.0 Message-Id: <20240709-topic-smem_speedbin-v5-3-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=874; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4D54MBq6zoAcYkfe7iD2ltE1UzYmVaRiFpw+gSQkiFQ=; b=WfLMIj4SCvcJlhKnPfLp36Ctyq2d6AHSfVTYR87sgyW+uMP6er36Q2p56z8XMiCz66+azs3NP ysIMX7TBRifDWp6wRSAsHAMRBbWj13kMAR33/CyVT8WKhZ6XMnbO7V7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c index 633f31539162..105b3d14bd75 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -129,6 +129,12 @@ static const struct adreno_info a5xx_gpus[] = { ADRENO_QUIRK_FAULT_DETECT_MASK, .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, From patchwork Tue Jul 9 10:45:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13727657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8582C2BD09 for ; Tue, 9 Jul 2024 10:46:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4F5510E4F5; Tue, 9 Jul 2024 10:46:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="sbe6RlLE"; dkim-atps=neutral Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB9CB10E4F5 for ; Tue, 9 Jul 2024 10:45:58 +0000 (UTC) Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a77baa87743so536498866b.3 for ; Tue, 09 Jul 2024 03:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720521957; x=1721126757; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+25nY/rYNm7YLajBTpZeCUf/L8baTplxhtXdEO1SETc=; b=sbe6RlLEq13dc8+x/14p6zGlynnd77ItrSSPfyj9NUPKPrMQdATxFe6wv8KMCzvD2S AnCxStyvv+zeQHHUVQVdAY907tLag7SBm58cloQLxT5TB4l5wpNLoOujNK1U6MXVvC80 iHRqLrW9hrXdKWlERYplbX+mfGeVjfu8cR4nDHnMhCJrCBIw316bJUfKyLMlkLBwcind 7hGPb55+jL4NESIu3N3Vf0OCZk5GTzjXnJZI8tXUkd795yu9C8LWsFmLdbTaa7qYYOk4 IwnGCWidtgxmf8OLdXhRI+lCJX1VpEAXB/03GgXQ55wozkqsLCrbTn5pdObKiqkH90BV rsLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720521957; x=1721126757; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+25nY/rYNm7YLajBTpZeCUf/L8baTplxhtXdEO1SETc=; b=bMBWFuSnvI31npUHmxY1Oij8gDSwk3w1KnchRWvh5Ucqvorgp83bf1GsiGgHETfag7 IhMBX+4lOrrgjT19OSGnGNLvtJG4ng2cQaggvVAQ/J0cgUC1K3xKw5ZkIqge5Mmt5k5X laoXm7nwj+s11puVK4tVKaU18b2LVxOhCvAf7BiWFA2hXELuXVD00z0RkaydUKtjVXEv nLVDLylBdhdy/WHF+Zfuljspu0fn5M/W1wIIEh+s9ta9sFr8ACD8CLdqqjFoMZQawFXx p1RrnsZJukeYCHrB604p+0s30Iho7MiX2YrO8t+1qocKvy/S5YhIA+rxK9NyoHvqP8FA PR0w== X-Forwarded-Encrypted: i=1; AJvYcCXKplur9bOi4Etdr2dKyHdfndOl868tAMp9L13xJYbj7zSroQ4DLKTwUAKaMIX343O01fdewkhdp0FkxFszL040L7PV4zLEjJB3QDBwlPB3 X-Gm-Message-State: AOJu0YyQ/uO+psCkgi6ElMwdkpTCl2Wv0g8uGnoJhMlweCI1SHoJpcHN LDwMJUiTFgXc7pdZE7gcxVqVRXWd71C86/QfdWGsxsyCDp+RQOZD0oFbharDobs= X-Google-Smtp-Source: AGHT+IG5FoktpVWK5QM17btN/ecwjh50i59Wtdzqowaj+yV2WoSrncfLxmfmu2om6K3T1xTR5sEtYQ== X-Received: by 2002:a17:906:d9d1:b0:a77:ec9f:d9c1 with SMTP id a640c23a62f3a-a780b89d4bemr184412766b.70.1720521956898; Tue, 09 Jul 2024 03:45:56 -0700 (PDT) Received: from [192.168.105.194] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:32 +0200 Subject: [PATCH v5 4/5] drm/msm/adreno: Redo the speedbin assignment MIME-Version: 1.0 Message-Id: <20240709-topic-smem_speedbin-v5-4-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=7871; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZSzgpQ49WT7GffGNsAbL1pXn75NnMBX03jO7rZdfrlQ=; b=NDdA24B5tdof5NaIKHu2eEqkNTFs05sN8KmxuwUU4w3M0iDVaZvuPQaCX9QUrvaMXzWhZfbMo 0Fi5mtGdvHRD+RHdXNtusFL9vK44fnT9giovlszJqlvGOEca3vV5/C5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There is no need to reinvent the wheel for simple read-match-set logic. Make speedbin discovery and assignment generation independent. This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx, which has no representation in hardware whatshowever. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 --------------------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 51 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -- 4 files changed, 45 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index c0b5373e90d7..d62b12efac57 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1709,38 +1709,6 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a5xx_get_timestamp, }; -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* - * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table - * doesn't get populated so pick an arbitrary value that should - * ensure the default frequencies are selected but not conflict with any - * actual bins - */ - val = 0x80; - - cell = nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf = nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin = *((u8 *) buf); - - val = (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - devm_pm_opp_set_supported_hw(dev, &val, 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -1768,8 +1736,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; - check_speed_bin(&pdev->dev); - nr_rings = 4; if (config->info->revn == 510) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0d8682c28ba4..849a14fe2319 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2105,55 +2105,6 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) -{ - if (!info->speedbins) - return UINT_MAX; - - for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) - if (info->speedbins[i].fuse == fuse) - return BIT(info->speedbins[i].speedbin); - - return UINT_MAX; -} - -static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, - struct device *dev, - const struct adreno_info *info) -{ - u32 supp_hw; - u32 speedbin; - int ret; - - ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); - /* - * -ENOENT/EOPNOTSUPP means that the platform doesn't support speedbin - * which is fine - */ - if (ret == -ENOENT || ret == -EOPNOTSUPP) { - return 0; - } else if (ret) { - dev_err_probe(dev, ret, - "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); - return ret; - } - - supp_hw = fuse_to_supp_hw(info, speedbin); - - if (supp_hw == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - speedbin); - supp_hw = BIT(0); /* Default */ - } - - ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; -} - static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -2285,13 +2236,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); - if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); - kfree(a6xx_gpu); - return ERR_PTR(ret); - } - if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index cf6652c4439d..6d0397a0554e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1064,8 +1064,8 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *fuse) +static int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { int ret; @@ -1100,6 +1100,46 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, return ret; } +#define ADRENO_SPEEDBIN_FUSE_NODATA 0xFFFF /* Made-up large value, expected by mesa */ +static int adreno_set_speedbin(struct adreno_gpu *adreno_gpu, struct device *dev) +{ + const struct adreno_info *info = adreno_gpu->info; + u32 fuse = ADRENO_SPEEDBIN_FUSE_NODATA; + u32 supp_hw = UINT_MAX; + int ret; + + /* No speedbins defined for this GPU SKU => allow all defined OPPs */ + if (!info->speedbins) { + adreno_gpu->speedbin = ADRENO_SPEEDBIN_FUSE_NODATA; + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + /* + * If a real error (not counting older devicetrees having no nvmem references) + * occurs when trying to get the fuse value, bail out. + */ + ret = adreno_read_speedbin(adreno_gpu, dev, &fuse); + if (ret) { + return ret; + } else if (fuse == ADRENO_SPEEDBIN_FUSE_NODATA) { + /* The info struct has speedbin data, but the DT doesn't => allow all OPPs */ + DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree\n"); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + adreno_gpu->speedbin = fuse; + + /* Traverse the known speedbins */ + for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) { + if (info->speedbins[i].fuse == fuse) { + supp_hw = BIT(info->speedbins[i].speedbin); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + } + + return dev_err_probe(dev, -EINVAL, "Unknown speed bin fuse value: 0x%x\n", fuse); +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) @@ -1109,7 +1149,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; adreno_gpu->funcs = funcs; @@ -1136,9 +1175,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) - speedbin = 0xffff; - adreno_gpu->speedbin = speedbin; + ret = adreno_set_speedbin(adreno_gpu, dev); + if (ret) + return ret; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0d629343ebb4..eef450dc3732 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -559,9 +559,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *speedbin); 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:58 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:33 +0200 Subject: [PATCH v5 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs MIME-Version: 1.0 Message-Id: <20240709-topic-smem_speedbin-v5-5-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=2474; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; b=UbAw9OwhyAwE8k7rUjhzv7OltpusBA6x/6YgB89OJWD+ojTrhyLuMSRDX4HAiIBsrrG0jevUW UobpDIs2ywfBIgClNuK2w9UxluMiW7//vluUrY7DilgVsJMyXYkgv3/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 4c9820adcf52..c1e3cec1540a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };