From patchwork Tue Jul 9 12:31:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13727790 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7871D14F9E9; Tue, 9 Jul 2024 12:31:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528310; cv=none; b=hAm7bNrATcwEFJjcBEnKWVg9KbDR2zFVSbxRn1ugBGM2KzoI2KDXKqjanJWQ3scQmGXxTuGYHZDyOZuFGyBGqvPvJcHAIHF1hyIu+4zI25VOqD7T5UPqd9ktfaUKMBqOOxp36hKCfauF1c8Sm6T3YARWmd/oft+ivwWPlL1YAFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528310; c=relaxed/simple; bh=DLUP+4DFqt8OqH54ZJCPXCGAcXTBzv6FQz/50YIgfYQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sEJJCjaq7ofZEmTx8SQ6cn5NK//AWf/KwGhyrGa5Bt8wZxw5cSQ87uMm1hgQFXcKmI8SrGOy+Wn6rUMjIhgPBNk1gduSx7brwDM7G0lJpwiX7lUimFRPp8iVwfY9tZZI+JakZF49tLGp6bKvd5KLpZvMXV+l+NjdVBqs8iCBWjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0T-00074P-3S; Tue, 09 Jul 2024 14:31:41 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 1/6] dt-bindings: clocks: add binding for generic clock-generators Date: Tue, 9 Jul 2024 14:31:16 +0200 Message-Id: <20240709123121.1452394-2-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In contrast to fixed clocks that are described as ungateable, boards sometimes use additional clock generators for things like PCIe reference clocks, that need actual supplies to get enabled and enable-gpios to be toggled for them to work. This adds a binding for such clock generators that are not configurable themself, but need to handle supplies for them to work. While in a lot of cases the type of the IC used is described in board schematics, in some cases just a generic type description like "100MHz, 3.3V" might also be used. The binding therefore allows both cases. Specifying the type is of course preferred. The clock-frequency is set in devicetree, because while some clock generators have pins to decide between multipls output rates, those are generally set statically on the board-layout-level. Signed-off-by: Heiko Stuebner --- .../bindings/clock/clock-generator.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/clock-generator.yaml diff --git a/Documentation/devicetree/bindings/clock/clock-generator.yaml b/Documentation/devicetree/bindings/clock/clock-generator.yaml new file mode 100644 index 0000000000000..f44e61e414e89 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/clock-generator.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/clock-generator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple clock generators + +maintainers: + - Heiko Stuebner + +properties: + $nodename: + anyOf: + - description: + Preferred name is 'clock-' with being the output + frequency as defined in the 'clock-frequency' property. + pattern: "^clock-([0-9]+|[a-z0-9-]+)$" + - description: Any name allowed + deprecated: true + + compatible: + oneOf: + - const: clock-generator + - items: + - enum: + - diodes,pi6c557-03b + - diodes,pi6c557-05b + - const: clock-generator + + "#clock-cells": + const: 0 + + clock-frequency: true + + clock-output-names: + maxItems: 1 + + enable-gpios: + description: + Contains a single GPIO specifier for the GPIO that enables and disables + the clock generator. + maxItems: 1 + + vdd-supply: + description: handle of the regulator that provides the supply voltage + +required: + - compatible + - "#clock-cells" + - clock-frequency + +additionalProperties: false + +examples: + - | + clock { + compatible = "clock-generator"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; +... From patchwork Tue Jul 9 12:31:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13727787 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7A4C152160; Tue, 9 Jul 2024 12:31:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528309; cv=none; b=QIypttmvUatXwleLO4wczJD7HqXpv0xklxs3/WJXhN+jv0KC1ryFLr5ovNt6RhSD6T8CBb5mjdBUsNk88VqeRVhXdsCRqM8KfsNLCEglFLnKqO6biQp12EzfWUhXddGr+7vcYWvaKDmMMYGaBU4+XNgHUf6jmUM71nt0S5AAx6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528309; c=relaxed/simple; bh=QqcrMcNEe3gEb6AUHDLKLCxKMChxZ1Lo+kHZ5kpcc78=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gqyeWI3XdCb2AVl0aFRkt5LviXEzZo+Z9zw1ZcLd/N8+6yx0j55On2+dOVnPCJcQeLScG9aR3VLGk402FzddqqQetYKP2tl1eUJOQQ2OFY4neTg0Yfkt/2+7FH7o2On1SRHIjOkziibGd2RwdbSpf+W2X4MvdJwxWagVb2pwNwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0T-00074P-LW; Tue, 09 Jul 2024 14:31:41 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 2/6] clk: add driver for generic clock generators Date: Tue, 9 Jul 2024 14:31:17 +0200 Message-Id: <20240709123121.1452394-3-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In contrast to fixed clocks that are described as ungateable, boards sometimes use additional clock generators for things like PCIe reference clocks, that need actual supplies to get enabled and enable-gpios to be toggled for them to work. This adds a driver for those generic unconfigurable clock generators. Signed-off-by: Heiko Stuebner --- drivers/clk/Kconfig | 7 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-generator.c | 133 ++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/clk/clk-generator.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3e9099504fad4..76c53ddc472ce 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -247,6 +247,13 @@ config COMMON_CLK_GEMINI This driver supports the SoC clocks on the Cortina Systems Gemini platform, also known as SL3516 or CS3516. +config COMMON_CLK_GENERATOR + tristate "Clock driver for generic clock generators" + depends on GPIOLIB && REGULATOR + help + This driver supports generic clock generators that are not + configurable but need supplies to be enabled to run. + config COMMON_CLK_LAN966X tristate "Generic Clock Controller driver for LAN966X SoC" depends on HAS_IOMEM diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4abe16c8ccdfe..9cb0801155771 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o +obj-$(CONFIG_COMMON_CLK_GENERATOR) += clk-generator.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o diff --git a/drivers/clk/clk-generator.c b/drivers/clk/clk-generator.c new file mode 100644 index 0000000000000..99737bab1f5ad --- /dev/null +++ b/drivers/clk/clk-generator.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Heiko Stuebner + * + * Generic unconfigurable clock generators + */ + +#include +#include +#include +#include +#include +#include +#include + +struct clk_generator { + struct device *dev; + struct clk_hw hw; + u32 rate; + struct regulator *supply; + struct gpio_desc *enable_gpio; +}; + +#define to_clk_generator(_hw) container_of(_hw, struct clk_generator, hw) + +static int clk_generator_prepare(struct clk_hw *hw) +{ + return regulator_enable(to_clk_generator(hw)->supply); +} + +static void clk_generator_unprepare(struct clk_hw *hw) +{ + regulator_disable(to_clk_generator(hw)->supply); +} + +static int clk_generator_enable(struct clk_hw *hw) +{ + gpiod_set_value(to_clk_generator(hw)->enable_gpio, 1); + return 0; +} + +static void clk_generator_disable(struct clk_hw *hw) +{ + gpiod_set_value(to_clk_generator(hw)->enable_gpio, 0); +} + +static unsigned long clk_generator_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return to_clk_generator(hw)->rate; +} + +const struct clk_ops clk_generator_ops = { + .prepare = clk_generator_prepare, + .unprepare = clk_generator_unprepare, + .enable = clk_generator_enable, + .disable = clk_generator_disable, + .recalc_rate = clk_generator_recalc_rate, +}; + +static int clk_generator_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_generator *clkgen; + const char *clk_name; + int ret; + + clkgen = devm_kzalloc(dev, sizeof(*clkgen), GFP_KERNEL); + if (!clkgen) + return -ENOMEM; + + clkgen->dev = dev; + + if (device_property_read_u32(dev, "clock-frequency", &clkgen->rate)) + return -EIO; + + ret = device_property_read_string(dev, "clock-output-names", &clk_name); + if (ret) + clk_name = fwnode_get_name(dev->fwnode); + + clkgen->supply = devm_regulator_get_optional(dev, "vdd"); + if (IS_ERR(clkgen->supply)) { + if (PTR_ERR(clkgen->supply) != -ENODEV) + return dev_err_probe(dev, PTR_ERR(clkgen->supply), + "failed to get regulator\n"); + clkgen->supply = NULL; + } + + clkgen->enable_gpio = devm_gpiod_get_optional(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(clkgen->enable_gpio)) + return dev_err_probe(dev, PTR_ERR(clkgen->enable_gpio), + "failed to get gpio\n"); + + ret = gpiod_direction_output(clkgen->enable_gpio, 0); + if (ret < 0) + return ret; + + clkgen->hw.init = CLK_HW_INIT_NO_PARENT(clk_name, &clk_generator_ops, 0); + + /* register the clock */ + ret = devm_clk_hw_register(dev, &clkgen->hw); + if (ret) + return dev_err_probe(dev, ret, + "failed to register clock\n"); + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &clkgen->hw); + if (ret) + return dev_err_probe(dev, ret, + "failed to register clock provider\n"); + + return 0; +} + +static const struct of_device_id clk_generator_ids[] = { + { .compatible = "clock-generator" }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_generator_ids); + +static struct platform_driver clk_generator_driver = { + .driver = { + .name = "clk_generator", + .of_match_table = clk_generator_ids, + }, + .probe = clk_generator_probe, +}; +module_platform_driver(clk_generator_driver); + +MODULE_AUTHOR("Heiko Stuebner "); +MODULE_DESCRIPTION("Clock-generator driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Jul 9 12:31:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13727788 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8EFB14532C; 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dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0U-00074P-6m; Tue, 09 Jul 2024 14:31:42 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 3/6] arm64: dts: rockchip: fix the pcie clock generator on Rock 5 ITX Date: Tue, 9 Jul 2024 14:31:18 +0200 Message-Id: <20240709123121.1452394-4-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its SATA controller with 2 lanes each. The supply for the clock generator is the same that supplies the M.2 slot, but the SATA controller port is supplied by a different rail. This leads to the effect that if the PCIe30x4 controller for the M.2 probes first, everything works normally. But if the PCIe30x2 controller that is connected to the SATA controller probes first, it will hang on the first DBI read as nothing will have enabled the refclock before. Fix this by describing the clock generator with its supplies so that both controllers can reference it as needed. Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5itx.dts | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts index 41d92ceeeb09c..21fb3d940b489 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts @@ -77,6 +77,15 @@ hdd-led2 { }; }; + /* Unnamed clock generator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-clock-generator { + compatible = "clock-generator"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + fan0: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -151,13 +160,14 @@ vcc3v3_lan: vcc3v3_lan_phy2: regulator-vcc3v3-lan { vin-supply = <&vcc_3v3_s3>; }; - vcc3v3_mkey: regulator-vcc3v3-mkey { + /* The PCIE30x4_PWREN_H controls two regulators */ + vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_pwren_h>; - regulator-name = "vcc3v3_mkey"; + regulator-name = "vcc3v3_pi6c_05"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; @@ -519,6 +529,14 @@ &pcie30phy { /* ASMedia ASM1164 Sata controller */ &pcie3x2 { + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, + <&pcie30_port1_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2_perstn_m1_l>; reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; @@ -528,6 +546,18 @@ &pcie3x2 { /* M.2 M.key */ &pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_perstn_m1_l>; From patchwork Tue Jul 9 12:31:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13727793 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 343D2160877; Tue, 9 Jul 2024 12:31:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528314; cv=none; b=Cd/ftLcVv1GWFYxH3upMhNeaVa0txoo2ODQRNLjB2dqmK/1cN54LciDVzUROs8yhbkES/wG+9iERN5IXMueZhno21bbrTtYArcgohQlpYrSAJ3gkX4MILTtScglvEjDqbz/RK3ZZwdQjkIOhsi4ydc9TFf0Rvdp3x0l9iyfQrcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528314; c=relaxed/simple; bh=tmZ6Uxzkf014Hxr8KQ0Tk9d1gGCwXt2cJ4n2Co2Nmz8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EPVTfCDqlTME06dOkF8xLI9IcjBF47Mtl4othpSiLaiy2AbNuP/CkzRgYa1ZN7NofJYcBNvSIOHo4gjiDcbFDugoY5VbzbJPiDv8v89jDsEO8uL72KMV782q6kZy9xOpGGbz/JmNdAEDYkwP5B5ZrKRoqcZyTrD0JZd5g+P6Scc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0U-00074P-Or; Tue, 09 Jul 2024 14:31:42 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 4/6] arm64: dts: rockchip: use clock-generator for pcie-refclk on rk3588-jaguar Date: Tue, 9 Jul 2024 14:31:19 +0200 Message-Id: <20240709123121.1452394-5-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the new clock-generator binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 71999f4f170af..b3c2aaedacf57 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -88,21 +88,16 @@ led-1 { * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE * clock generator. * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible = "fixed-clock"; + pcie_refclk: pcie-clock-generator { + compatible = "diodes,pi6c557-05b", "clock-generator"; #clock-cells = <0>; clock-frequency = <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible = "gpio-gate-clock"; - clocks = <&pcie_refclk_gen>; - #clock-cells = <0>; + clock-output-names = "pcie3_refclk"; enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */ pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_clkreqn_m0>; + vdd-supply = <&vcca_3v3_s0>; }; pps { From patchwork Tue Jul 9 12:31:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13727791 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E6EA14EC41; Tue, 9 Jul 2024 12:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528310; cv=none; b=htdwxSltQJswCS7ImDxeS4F4w9lySqRlFC6uqMOXb6CFx3qnCyOEJYo/Fh7soqFFqJIwJjSb/ZVOUGwynvcZq7ndt3LD8haCUKF9IQTzKpRQ3DSx9UVg5XUI17XgsOhbnMvqPYe8LsyoWOQxDCi+Pk+HF8Bd6J+ZyyqVHd+d6pY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528310; c=relaxed/simple; bh=DlzPkirboh4VclwZWaIpOoQYphFDi38NOQeBo0jwcis=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kbUtakY4TZSY65hpmDhgLRRo6XPgNaBE/BOpcldyc1dqftyI/SWlTcp6mzcVmx8TXJV5lI5F+R788eOJM0H3SbUDfBYp0kv7llqgILV3KvdIn33tOb/q9a+ruoWLKKqSfyW7RUTfjh6S0Pn1NaiUS4UiZFKS+ktdMFEDlyshE/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0V-00074P-AQ; Tue, 09 Jul 2024 14:31:43 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 5/6] arm64: dts: rockchip: use clock-generator for pcie-refclk on rk3588-tiger Date: Tue, 9 Jul 2024 14:31:20 +0200 Message-Id: <20240709123121.1452394-6-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the new clock-generator binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index f870f84da1e6d..4c5be356fa7fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -49,19 +49,14 @@ led-1 { * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE * clock generator. * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible = "fixed-clock"; + pcie_refclk: pcie-clock-generator { + compatible = "diodes,pi6c557-05b", "clock-generator"; #clock-cells = <0>; clock-frequency = <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible = "gpio-gate-clock"; - clocks = <&pcie_refclk_gen>; - #clock-cells = <0>; + clock-output-names = "pcie3_refclk"; enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ + vdd-supply = <&vcca_3v3_s0>; }; vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { From patchwork Tue Jul 9 12:31:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13727792 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7607C158203; Tue, 9 Jul 2024 12:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528311; cv=none; b=gFFpE5+U8frQgF5gFPy+SiztGBxEXFCzbJFrpkNKejEtPpU6BVPWylq12InNefCmafib4qLOYVFoViejjjQUyY69ejb7XfpKnI493wPwNazkIJbhm3taac96a0Q5SP/rwdDf/pI6B/t6r5G6KkFjs4NF83I0WAuuwPAinKL70uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720528311; c=relaxed/simple; bh=+q/lfmSkbMx1KbBQRYdQ9l6EhpiAU0lwIrUJmWJac04=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tmrl6LAriqPW4i2sB77KwD6SVU1tJMD6yBRky/O7mkKDpNTf5UhF2IGQUCr5WXWRgMnoUnwsonqoK/SP//caWAJE1dOky3lWmw0d6fLrclCmi8Q7Fhcc7iqS6fQ/5PA+hIVAJZ+LoY0C6GRdX1cD/wsassn+xIryFswrM+0hVXk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0V-00074P-Sp; Tue, 09 Jul 2024 14:31:43 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 6/6] arm64: dts: rockchip: add pinctrl for clk-generator gpio on rk3588-tiger Date: Tue, 9 Jul 2024 14:31:21 +0200 Message-Id: <20240709123121.1452394-7-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Having pinctrl entries defined for used gpios is helpful as it makes sure the pin isn't used anywhere else. The somewhat similar rk3588-jaguar board has a pinctrl entry already, so add the same for rk3588-tiger. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 4c5be356fa7fe..fb5f1fa25fb9e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -56,6 +56,8 @@ pcie_refclk: pcie-clock-generator { clock-frequency = <100000000>; clock-output-names = "pcie3_refclk"; enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1_l>; vdd-supply = <&vcca_3v3_s0>; }; @@ -339,6 +341,12 @@ module_led_pin: module-led-pin { }; }; + pcie30x4 { + pcie30x4_clkreqn_m1_l: pcie30x4-clkreqn-m1-l { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb3 { usb3_id: usb3-id { rockchip,pins =