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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF000023D8.mail.protection.outlook.com (10.167.244.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7762.1 via Frontend Transport; Tue, 9 Jul 2024 13:36:22 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 9 Jul 2024 08:36:21 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 9 Jul 2024 08:36:20 -0500 From: Stewart Hildebrand To: Bjorn Helgaas CC: Stewart Hildebrand , , Subject: [PATCH 1/6] PCI: don't clear already cleared bit Date: Tue, 9 Jul 2024 09:35:58 -0400 Message-ID: <20240709133610.1089420-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709133610.1089420-1-stewart.hildebrand@amd.com> References: <20240709133610.1089420-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D8:EE_|DM6PR12MB4267:EE_ X-MS-Office365-Filtering-Correlation-Id: 5932d28c-4c84-4aee-19f8-08dca01c1fb7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 13:36:22.8577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5932d28c-4c84-4aee-19f8-08dca01c1fb7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4267 pci_reassigndev_resource_alignment() performs a PCI config read, then then unconditionally clears a bit and issues a PCI config write. However, the bit in question (PCI_COMMAND_MEMORY) is a RW bit, so it is unnecessary to issue the PCI config write if the bit is already cleared. Make the write conditional. Signed-off-by: Stewart Hildebrand --- Should this be folded into ("pci: restore memory decoding after reallocation") in this series? --- drivers/pci/pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index df550953fa26..f017e7a8f028 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6632,8 +6632,10 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) } pci_read_config_word(dev, PCI_COMMAND, &command); - command &= ~PCI_COMMAND_MEMORY; - pci_write_config_word(dev, PCI_COMMAND, command); + if (command & PCI_COMMAND_MEMORY) { + command &= ~PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, command); + } for (i = 0; i <= PCI_ROM_RESOURCE; i++) pci_request_resource_alignment(dev, i, align, resize); From patchwork Tue Jul 9 13:35:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13728040 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2083.outbound.protection.outlook.com [40.107.244.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 974E915FA7A; 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Restore the alignment. Signed-off-by: Stewart Hildebrand --- drivers/pci/setup-bus.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 23082bc0ca37..ab7510ce6917 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1594,6 +1594,23 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge, } } +static void restore_child_resource_alignment(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + struct pci_bus *b; + + pci_reassigndev_resource_alignment(dev); + + b = dev->subordinate; + if (!b) + continue; + + restore_child_resource_alignment(b); + } +} + #define PCI_RES_TYPE_MASK \ (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ IORESOURCE_MEM_64) @@ -1648,6 +1665,8 @@ static void pci_bridge_release_resources(struct pci_bus *bus, r->start = 0; r->flags = 0; + restore_child_resource_alignment(bus); + /* Avoiding touch the one without PREF */ if (type & IORESOURCE_PREFETCH) type = IORESOURCE_PREFETCH; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 13:36:40.3576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb4cd595-f5d8-428b-c2fb-08dca01c2a27 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7329 Currently, the PCI subsystem unconditionally clears the memory decoding bit of devices with resource alignment specified. Unfortunately, some drivers assume memory decoding was enabled by firmware. Restore the memory decoding bit after the resource has been reallocated. Signed-off-by: Stewart Hildebrand --- Relevant prior discussion at [1] [1] https://lore.kernel.org/linux-pci/20160906165652.GE1214@localhost/ --- drivers/pci/pci.c | 1 + drivers/pci/setup-bus.c | 25 +++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 3 files changed, 28 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f017e7a8f028..7953e75b9129 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6633,6 +6633,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &command); if (command & PCI_COMMAND_MEMORY) { + dev->dev_flags |= PCI_DEV_FLAGS_MEMORY_ENABLE; command &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, command); } diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ab7510ce6917..6847b251e19a 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2131,6 +2131,29 @@ pci_root_bus_distribute_available_resources(struct pci_bus *bus, } } +static void restore_memory_decoding(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + struct pci_bus *b; + + if (dev->dev_flags & PCI_DEV_FLAGS_MEMORY_ENABLE) { + u16 command; + + pci_read_config_word(dev, PCI_COMMAND, &command); + command |= PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, command); + } + + b = dev->subordinate; + if (!b) + continue; + + restore_memory_decoding(b); + } +} + /* * First try will not touch PCI bridge res. * Second and later try will clear small leaf bridge res. @@ -2229,6 +2252,8 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) goto again; dump: + restore_memory_decoding(bus); + /* Dump the resource on buses */ pci_bus_dump_resources(bus); } diff --git a/include/linux/pci.h b/include/linux/pci.h index e83ac93a4dcb..cb5df4c6a999 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -245,6 +245,8 @@ enum pci_dev_flags { PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), /* Device does honor MSI masking despite saying otherwise */ PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), + /* Firmware enabled memory decoding, to be restored if BAR is updated */ + PCI_DEV_FLAGS_MEMORY_ENABLE = (__force pci_dev_flags_t) (1 << 13), }; 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Tue, 9 Jul 2024 08:36:42 -0500 From: Stewart Hildebrand To: Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" CC: Stewart Hildebrand , , , Subject: [RFC PATCH 4/6] x86: PCI: preserve IORESOURCE_STARTALIGN alignment Date: Tue, 9 Jul 2024 09:36:01 -0400 Message-ID: <20240709133610.1089420-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709133610.1089420-1-stewart.hildebrand@amd.com> References: <20240709133610.1089420-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|MN2PR12MB4126:EE_ X-MS-Office365-Filtering-Correlation-Id: c0223e0c-764d-4f0d-bb05-08dca01c2e62 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: KKNvhN/WTTj2j6v49eR1VScg/XCTjlijmfKSy0QJvjDKVklRSvvKW/fWsiTKAwwWPosH54LURhJOrGzUXbBZZa/D2M1OyUDib/WaR/wb1qWHXsdw3YabFpkDYDxK61B+1OCmJw/e5KCNZHjOwLsVD7xmmngku5KM52ZfOQRi68zFpXKbwDxHRoBoqnfR30QrFmJa3x00i5WqUeEtJ6kHB3truItRAxl76BTwdq3XyN3qS9k43EbXAPVzBlO6PPTKTY9pZcA5mgWYfAOiZO2i9W/cWsK5uwyhRi/jlP0TMTFuLbhOGF3s4CD7Jmfv9NgYTXrAQWQIrRzi3jZRR9VzUuDbROIeApb/Cizfnx836WaksoPkr4k9yJLJMRpesaVXx0psk4sMKTYGOQitxm5wTTrU07GvkZae9eP70ZbTtZaTlcOr0MSt3S3TA8DeskAT42DHaVPlnafgxg9ro8/H2mRt0RVhesRsdpX4egYeobU5yihPlhepQRaW2YMi6/QhJFqr6bdIah+dyQePhLTCSxR8AiP0pkycibpTLIQckagBMOxIykfLiq2/NtRPDwSxGV1WDsLVWNYGJErA/oG8gREenM2+a/hhIa62k7LVQ8xwW5ms11f4Dum5QKAF8Ir0rH0sz3Y4k1FrTbUm/a/0d+gdeSR4H9q71gn0XmFpaQalK1XBIEzmpzLjHUGrOYLamTmPFhN6Hc8tbY/fb8JHMIDHiNJjPzVf14fyLO2bRPsmQ8D5QXhVGw/iZTqsmP/Dn1fVrfeQNkYmsjX68dPJbe65XWgd1piQh/QFNkOk5fvcgCgNoH6s0yTtVBmItA6sKVhCu+wB5H0qKHFRdEgcf6d8FLxgxc/hR8FV3O68R1o++hV5d03tuM9m8glZtM6cvnq3cW6Xck/SE1lyFYTE3vd7F0tifEQ8mIa7Kyge6kA7YKGrXaNp5u6HMSsMrJ+UCKP1R4E9/TSiZ9SfvDyed1n2oYPV/s5OEUGC0JFIOuW6kpEOZjsAS5mNWiL8/9YyKzLqv83SnNBDeAnVH2GnK3362Ek8oHJVmTSIp3q6QwaDLkbV7m4TEJtlCIrAEbbXdc7llzDUmRYk8tw3A03BKzDKqlWxlzsOc0eFy59rCI/AtnNhcJAlceVRD1EBYEjE8Wu9D+/72el6qMjFpcLTR/US3oRCAXNUppUzilftkXsrR+ylE21ZvSY4Qy1Nc9XYdZlui7kZlM9Nb8hy2B6xvbIrGs6rOiBZfSTJMMPdTuf/MAaNQ8amG5CbfvVkRExiXuQSKB8293J4I5omswwkCwqg3jKo2Pipv5BjBNTAi8/A+4AyjTfnQXC5dq8X0wf+Vv/MQCdipp1f88PEwH9fSoStfaytgDH5k2WOPoOvZaQc4vkiJpx1nnJu1WrEHqAOaJevwUPRbwMhrnAqT3ErgpPaoHW+1alybivz4jal8jd8NYEGPZMP1Pn0y1exBKE5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 13:36:47.6424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0223e0c-764d-4f0d-bb05-08dca01c2e62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4126 Currently, it's not possible to use the IORESOURCE_STARTALIGN flag on x86 due to the alignment being overwritten in pcibios_allocate_dev_resources(). Make one small change in arch/x86 to make it work on x86. Signed-off-by: Stewart Hildebrand --- RFC: We don't have enough info in this function to re-calculate the alignment value in case of IORESOURCE_STARTALIGN. Luckily our alignment value seems to be intact, so just don't touch it... Alternatively, we could call pci_reassigndev_resource_alignment() after the loop. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 13:36:52.9778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a667d50-3dd2-40b1-ae10-08dca01c31a8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7656 As a follow-up to commit 0dde1c08d1b9 ("PCI: Don't reassign resources that are already aligned"), don't reassign already aligned resources that have requested alignment without resizing. Signed-off-by: Stewart Hildebrand --- drivers/pci/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7953e75b9129..9f7894538334 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6553,6 +6553,9 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, if (size >= align) return; + if (!resize && (r->start > align) && !(r->start & (align - 1))) + return; + /* * Increase the alignment of the resource. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 13:36:59.5579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 257e210a-3cbf-48b2-e335-08dca01c357c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4134 Issues observed when small (<4k) BARs are not 4k aligned are: 1. Devices to be passed through (to e.g. a Xen HVM guest) with small (<4k) BARs require each memory BAR to be page aligned. Currently, the only way to guarantee this alignment from a user perspective is to fake the size of the BARs using the pci=resource_alignment= option. This is a bad user experience, and faking the BAR size is not always desirable. See the comment in drivers/pci/pci.c:pci_request_resource_alignment() for further discussion. 2. Devices with multiple small (<4k) BARs could have the MSI-X tables located in one of its small (<4k) BARs. This may lead to the MSI-X tables being mapped in the same 4k region as other data. The PCIe 6.1 specification (section 7.7.2 MSI-X Capability and Table Structure) says we probably shouldn't do that. To improve the user experience, and increase conformance to PCIe spec, set the default minimum resource alignment of memory BARs to 4k. Choose 4k (rather than PAGE_SIZE) for the alignment value in the common code, since that is the value called out in the PCIe 6.1 spec, section 7.7.2. The new default alignment may be overridden by arches by implementing pcibios_default_alignment(), or by the user with the pci=resource_alignment= option. Signed-off-by: Stewart Hildebrand --- Preparatory patches in this series are prerequisites to this patch. --- drivers/pci/pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 9f7894538334..e7b648304383 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6453,7 +6453,12 @@ struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev) resource_size_t __weak pcibios_default_alignment(void) { - return 0; + /* + * Avoid MSI-X tables being mapped in the same 4k region as other data + * according to PCIe 6.1 specification section 7.7.2 MSI-X Capability + * and Table Structure. + */ + return 4 * 1024; } /*