From patchwork Tue Jul 9 14:53:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tengfei Fan X-Patchwork-Id: 13728191 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A6A61E864; Tue, 9 Jul 2024 14:54:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720536855; cv=none; b=LjJ10VnHW5mwSFcQjpP+4/0AwXlrkgIw5KXcDPuRTDblihxuk7lvadzWu+sN7u80MgIGfNWdBSZtovTpUL1oHqEl0zRe/iVZFLDM8SQBAvGy3qo/SSQw6cI7AvZHpwOCeSNM66kHmzq/osciT/yf/IaDf8+S5SFvHVH5CC6I9QQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720536855; c=relaxed/simple; bh=oAUhPtcZ0FUV5xoeA71k+/wIZLEOdCXNurgZIHXvnKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=aHzt9cR1CzWJwen0Cr4B3D665BZ5dlD/x6d7Ofk91NVpCEfD+Lhb2LlOyLb7uttME5Z5CpLqladst6rtEbJOFAjEoQEF8JwRYUTEOfjRb2uw9E7DolG8rk1KdLkyeZILaycbhHZox3izNA35MRsSpIG6dNxurnVuFJ2itCsLmTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Dspl8lMR; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Dspl8lMR" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 469Ah5nk020426; Tue, 9 Jul 2024 14:54:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= otF8zgKHb7fx/Ai4X9xXwiyDJmakSRghKVOBUjZhzuA=; b=Dspl8lMRzkB2TAzS MoHWst/TlEQ7RYZnUdmCsu9Jz26/bLzLxzMz0a+5YNrsWjvc5mQmeYRZP/CsWCF8 +oujsPtHRUv/8pQMNu5G1Azlg4BMsXs2D7Y0wmTXltYqWkGFTQnn7gt9+07bihKU hjsi845s+HLhO0QXBSOLadolh0qu26Rco1qfA1tlleGwR/Zg/iLwYodEzdxZcMF5 rQPQbKmejCmkeJ4LhwR3/vDrdwbyf8E5mJay2fAuVJ5LNCUrzWatpGK52c42iU6C j2ItXo8oChyNprh0VlWqn5pGu8LYvFgihkud76O7Aap4p6EmHtdICtF0TKkd1Z9P 3UPpZg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 406xa66ps3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jul 2024 14:54:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 469Es39h022682 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 Jul 2024 14:54:04 GMT Received: from tengfan-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 9 Jul 2024 07:53:55 -0700 From: Tengfei Fan Date: Tue, 9 Jul 2024 22:53:43 +0800 Subject: [PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240709-add_qcs9100_pcie_ep_compatible-v2-1-217742eac32b@quicinc.com> References: <20240709-add_qcs9100_pcie_ep_compatible-v2-0-217742eac32b@quicinc.com> In-Reply-To: <20240709-add_qcs9100_pcie_ep_compatible-v2-0-217742eac32b@quicinc.com> To: Manivannan Sadhasivam , "Lorenzo Pieralisi" , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley CC: , , , , , Tengfei Fan X-Mailer: b4 0.15-dev-a66ce X-Developer-Signature: v=1; a=ed25519-sha256; t=1720536832; l=1307; i=quic_tengfan@quicinc.com; s=20240709; h=from:subject:message-id; bh=oAUhPtcZ0FUV5xoeA71k+/wIZLEOdCXNurgZIHXvnKc=; b=oilqxqn2muqSlMy5K0dHc+LpyB2djSuOC0D1u5hOndfX1sCLK0yoy7xpqMvVLiONonE/3YLJ+ 4ES3evUVI6AA6b59F1ZV9VBbjH84jG4eDMUFJrxe+cFnJTNkNsuOo2B X-Developer-Key: i=quic_tengfan@quicinc.com; a=ed25519; pk=4VjoTogHXJhZUM9XlxbCAcZ4zmrLeuep4dfOeKqQD0c= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3piS_-ABQ97feVsMKrZ51UqTsEy7NNhN X-Proofpoint-ORIG-GUID: 3piS_-ABQ97feVsMKrZ51UqTsEy7NNhN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-09_04,2024-07-09_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=667 suspectscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407090097 Add devicetree bindings support for QCS9100 SoC. It has DMA register space and dma interrupt to support HDMA. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI based PCIe. Signed-off-by: Tengfei Fan --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..8012663e7efc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - qcom,qcs9100-pcie-ep - qcom,sa8775p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep @@ -203,6 +204,7 @@ allOf: compatible: contains: enum: + - qcom,qcs9100-pcie-ep - qcom,sa8775p-pcie-ep then: properties: From patchwork Tue Jul 9 14:53:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tengfei Fan X-Patchwork-Id: 13728193 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E00C519CCF6; Tue, 9 Jul 2024 14:57:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720537035; cv=none; b=M8cjsQvIgdFw4PB51xxot0uNRDpxhKtx4ZehLr4RRPHgAyfCId9C1OrkVrWQZmbCoGgf0TaeANRRczLHZKCMfGMHgMvVgY3CUbPpT/SYkdx7vAvePUz2/hn94nbL2v/tzq37x9DDhXcNFSKtKvPg+eWMOkQvmYx3o9jIz1bMQlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720537035; c=relaxed/simple; bh=q183F0/HFGC/8U/gLjzUqH8Bv64w+2hrHp8UiRG815A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=h9T9ngcaoWQb39fxjKU1c7HRdbuh6yf3IeTBRWLGLGD2wdcZXrW1IoUiiWuj9wgojWPxRmKSQnO8cGOrMpL26eptoOOrkzReUvm8t1mQBaJ5NWbCMQuB5ub5nOEDq7UJJVGzzudfJJQ3BBUWl29c1LFokR1K4LQFpqHByxRelmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=k/R4UAdb; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="k/R4UAdb" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 469A7KVD012432; Tue, 9 Jul 2024 14:54:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CSDkESbCmZqUgbZ09QMkhUrOl3ltgh7Fjn3q70aFm1M=; b=k/R4UAdb5OrEjdUi 18iOvHVTqKYUXYx7R46QfueRAIYntkh0OOR6S6GDVDV6CmF/vPq1gvqKdYaJBpUZ jyGRGEy9dam/aVAkwipkF6/QP9ZPUHBKgSNfVKgtQc6j5TqGj/Ez8T2pQZKp3T/k SrWkKhYGM6afqqoKLNP5zJPT6leB3unFS+ycOpfQJPfJZ57GsNtpukKQYCDCpevi tWxlOFcMl0hO+vJxxrbqE/vWSD7jp219ubVpy1f3mhmdDgM84L2wriSEUH0enZGZ zMQjvo6x8zuFA6DzZcwNn4T2JzTuzunk5ZzQw54APcAgE+vzx28kXpWSHUaRwHW7 w338WA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 406x0t70d4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jul 2024 14:54:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 469Es39i022682 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 Jul 2024 14:54:04 GMT Received: from tengfan-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 9 Jul 2024 07:53:58 -0700 From: Tengfei Fan Date: Tue, 9 Jul 2024 22:53:44 +0800 Subject: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240709-add_qcs9100_pcie_ep_compatible-v2-2-217742eac32b@quicinc.com> References: <20240709-add_qcs9100_pcie_ep_compatible-v2-0-217742eac32b@quicinc.com> In-Reply-To: <20240709-add_qcs9100_pcie_ep_compatible-v2-0-217742eac32b@quicinc.com> To: Manivannan Sadhasivam , "Lorenzo Pieralisi" , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley CC: , , , , , Tengfei Fan X-Mailer: b4 0.15-dev-a66ce X-Developer-Signature: v=1; a=ed25519-sha256; t=1720536832; l=1616; i=quic_tengfan@quicinc.com; s=20240709; h=from:subject:message-id; bh=q183F0/HFGC/8U/gLjzUqH8Bv64w+2hrHp8UiRG815A=; b=x91GX2Ia9pAYVTMaewFVd/hPIWWGFBfLU9N3N31guIhozOdaji+JGEv53rHm2j57YMAwZaRjQ bxidEQXStQACkxrVqP4TSNMgIABdpoeiMlDzBCF8kmH5q0o8gWmFTuS X-Developer-Key: i=quic_tengfan@quicinc.com; a=ed25519; pk=4VjoTogHXJhZUM9XlxbCAcZ4zmrLeuep4dfOeKqQD0c= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AA7X_SZwvdZ6RL3bOpGGaLv4OhPi776m X-Proofpoint-ORIG-GUID: AA7X_SZwvdZ6RL3bOpGGaLv4OhPi776m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-09_04,2024-07-09_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 mlxlogscore=970 priorityscore=1501 malwarescore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407090097 QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, so add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device match table. Signed-off-by: Tengfei Fan --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..e2775f4ca7ee 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { }; static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", },