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No functional change. Signed-off-by: Frank Li --- drivers/edac/fsl_ddr_edac.c | 62 ++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index d148d262d0d4d..a7982370e2381 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -35,13 +35,17 @@ static u32 orig_ddr_err_disable; static u32 orig_ddr_err_sbe; static bool little_endian; -static inline u32 ddr_in32(void __iomem *addr) +static inline u32 ddr_in32(struct fsl_mc_pdata *pdata, unsigned int off) { + void __iomem *addr = pdata->mc_vbase + off; + return little_endian ? ioread32(addr) : ioread32be(addr); } -static inline void ddr_out32(void __iomem *addr, u32 value) +static inline void ddr_out32(struct fsl_mc_pdata *pdata, unsigned int off, u32 value) { + void __iomem *addr = pdata->mc_vbase + off; + if (little_endian) iowrite32(value, addr); else @@ -60,7 +64,7 @@ static ssize_t fsl_mc_inject_data_hi_show(struct device *dev, struct mem_ctl_info *mci = to_mci(dev); struct fsl_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", - ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI)); + ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_HI)); } static ssize_t fsl_mc_inject_data_lo_show(struct device *dev, @@ -70,7 +74,7 @@ static ssize_t fsl_mc_inject_data_lo_show(struct device *dev, struct mem_ctl_info *mci = to_mci(dev); struct fsl_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", - ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO)); + ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_LO)); } static ssize_t fsl_mc_inject_ctrl_show(struct device *dev, @@ -80,7 +84,7 @@ static ssize_t fsl_mc_inject_ctrl_show(struct device *dev, struct mem_ctl_info *mci = to_mci(dev); struct fsl_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", - ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT)); + ddr_in32(pdata, FSL_MC_ECC_ERR_INJECT)); } static ssize_t fsl_mc_inject_data_hi_store(struct device *dev, @@ -97,7 +101,7 @@ static ssize_t fsl_mc_inject_data_hi_store(struct device *dev, if (rc) return rc; - ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val); + ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_HI, val); return count; } return 0; @@ -117,7 +121,7 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev, if (rc) return rc; - ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val); + ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_LO, val); return count; } return 0; @@ -137,7 +141,7 @@ static ssize_t fsl_mc_inject_ctrl_store(struct device *dev, if (rc) return rc; - ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val); + ddr_out32(pdata, FSL_MC_ECC_ERR_INJECT, val); return count; } return 0; @@ -286,7 +290,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci) int bad_data_bit; int bad_ecc_bit; - err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); + err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT); if (!err_detect) return; @@ -295,14 +299,14 @@ static void fsl_mc_check(struct mem_ctl_info *mci) /* no more processing if not ECC bit errors */ if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect); + ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect); return; } - syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC); + syndrome = ddr_in32(pdata, FSL_MC_CAPTURE_ECC); /* Mask off appropriate bits of syndrome based on bus width */ - bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) & + bus_width = (ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG) & DSC_DBW_MASK) ? 32 : 64; if (bus_width == 64) syndrome &= 0xff; @@ -310,8 +314,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci) syndrome &= 0xffff; err_addr = make64( - ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS), - ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS)); + ddr_in32(pdata, FSL_MC_CAPTURE_EXT_ADDRESS), + ddr_in32(pdata, FSL_MC_CAPTURE_ADDRESS)); pfn = err_addr >> PAGE_SHIFT; for (row_index = 0; row_index < mci->nr_csrows; row_index++) { @@ -320,8 +324,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci) break; } - cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI); - cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO); + cap_high = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_HI); + cap_low = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_LO); /* * Analyze single-bit errors on 64-bit wide buses @@ -367,7 +371,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci) row_index, 0, -1, mci->ctl_name, ""); - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect); + ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect); } static irqreturn_t fsl_mc_isr(int irq, void *dev_id) @@ -376,7 +380,7 @@ static irqreturn_t fsl_mc_isr(int irq, void *dev_id) struct fsl_mc_pdata *pdata = mci->pvt_info; u32 err_detect; - err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); + err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT); if (!err_detect) return IRQ_NONE; @@ -396,7 +400,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci) u32 cs_bnds; int index; - sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG); + sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG); sdtype = sdram_ctl & DSC_SDTYPE_MASK; if (sdram_ctl & DSC_RD_EN) { @@ -444,7 +448,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci) csrow = mci->csrows[index]; dimm = csrow->channels[0]->dimm; - cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 + + cs_bnds = ddr_in32(pdata, FSL_MC_CS_BNDS_0 + (index * FSL_MC_CS_BNDS_OFS)); start = (cs_bnds & 0xffff0000) >> 16; @@ -558,11 +562,11 @@ int fsl_mc_err_probe(struct platform_device *op) fsl_ddr_init_csrows(mci); /* store the original error disable bits */ - orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE); - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0); + orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE); + ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0); /* clear all error bits */ - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0); + ddr_out32(pdata, FSL_MC_ERR_DETECT, ~0); res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups); if (res) { @@ -571,15 +575,15 @@ int fsl_mc_err_probe(struct platform_device *op) } if (edac_op_state == EDAC_OPSTATE_INT) { - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, + ddr_out32(pdata, FSL_MC_ERR_INT_EN, DDR_EIE_MBEE | DDR_EIE_SBEE); /* store the original error management threshold */ - orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase + + orig_ddr_err_sbe = ddr_in32(pdata, FSL_MC_ERR_SBE) & 0xff0000; /* set threshold to 1 error per interrupt */ - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000); + ddr_out32(pdata, FSL_MC_ERR_SBE, 0x10000); /* register interrupts */ pdata->irq = platform_get_irq(op, 0); @@ -620,12 +624,12 @@ void fsl_mc_err_remove(struct platform_device *op) edac_dbg(0, "\n"); if (edac_op_state == EDAC_OPSTATE_INT) { - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0); + ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0); } - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, + ddr_out32(pdata, FSL_MC_ERR_DISABLE, orig_ddr_err_disable); - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe); + ddr_out32(pdata, FSL_MC_ERR_SBE, orig_ddr_err_sbe); edac_mc_del_mc(&op->dev); edac_mc_free(mci); From patchwork Tue Jul 9 20:23:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13728458 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2043.outbound.protection.outlook.com [40.107.22.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 089B9182A5E; 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No function change. Signed-off-by: Frank Li --- drivers/edac/fsl_ddr_edac.c | 21 +++++++++------------ drivers/edac/fsl_ddr_edac.h | 3 +++ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index a7982370e2381..10b0a46669f3d 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -31,22 +31,18 @@ static int edac_mc_idx; -static u32 orig_ddr_err_disable; -static u32 orig_ddr_err_sbe; -static bool little_endian; - static inline u32 ddr_in32(struct fsl_mc_pdata *pdata, unsigned int off) { void __iomem *addr = pdata->mc_vbase + off; - return little_endian ? ioread32(addr) : ioread32be(addr); + return pdata->little_endian ? ioread32(addr) : ioread32be(addr); } static inline void ddr_out32(struct fsl_mc_pdata *pdata, unsigned int off, u32 value) { void __iomem *addr = pdata->mc_vbase + off; - if (little_endian) + if (pdata->little_endian) iowrite32(value, addr); else iowrite32be(value, addr); @@ -511,7 +507,7 @@ int fsl_mc_err_probe(struct platform_device *op) * Get the endianness of DDR controller registers. * Default is big endian. */ - little_endian = of_property_read_bool(op->dev.of_node, "little-endian"); + pdata->little_endian = of_property_read_bool(op->dev.of_node, "little-endian"); res = of_address_to_resource(op->dev.of_node, 0, &r); if (res) { @@ -535,7 +531,7 @@ int fsl_mc_err_probe(struct platform_device *op) goto err; } - sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG); + sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG); if (!(sdram_ctl & DSC_ECC_EN)) { /* no ECC */ pr_warn("%s: No ECC DIMMs discovered\n", __func__); @@ -562,7 +558,7 @@ int fsl_mc_err_probe(struct platform_device *op) fsl_ddr_init_csrows(mci); /* store the original error disable bits */ - orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE); + pdata->orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE); ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0); /* clear all error bits */ @@ -579,7 +575,7 @@ int fsl_mc_err_probe(struct platform_device *op) DDR_EIE_MBEE | DDR_EIE_SBEE); /* store the original error management threshold */ - orig_ddr_err_sbe = ddr_in32(pdata, + pdata->orig_ddr_err_sbe = ddr_in32(pdata, FSL_MC_ERR_SBE) & 0xff0000; /* set threshold to 1 error per interrupt */ @@ -628,8 +624,9 @@ void fsl_mc_err_remove(struct platform_device *op) } ddr_out32(pdata, FSL_MC_ERR_DISABLE, - orig_ddr_err_disable); - ddr_out32(pdata, FSL_MC_ERR_SBE, orig_ddr_err_sbe); + pdata->orig_ddr_err_disable); + ddr_out32(pdata, FSL_MC_ERR_SBE, pdata->orig_ddr_err_sbe); + edac_mc_del_mc(&op->dev); edac_mc_free(mci); diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h index c0994a2a003c2..de66f9822fba1 100644 --- a/drivers/edac/fsl_ddr_edac.h +++ b/drivers/edac/fsl_ddr_edac.h @@ -70,6 +70,9 @@ struct fsl_mc_pdata { int edac_idx; void __iomem *mc_vbase; int irq; + u32 orig_ddr_err_disable; + u32 orig_ddr_err_sbe; + bool little_endian; }; int fsl_mc_err_probe(struct platform_device *op); void fsl_mc_err_remove(struct platform_device *op); From patchwork Tue Jul 9 20:23:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13728459 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2041.outbound.protection.outlook.com [40.107.22.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D3F5187856; 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If bad_data_bit is below 32, bad_data_bit - 32 will be a negative value. Left shifting a negative value in C is undefined behavior. Fix this by checking the range of bad_data_bit. Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx") Signed-off-by: Priyanka Singh Reviewed-by: Sherry Sun Signed-off-by: Li Yang Signed-off-by: Frank Li --- drivers/edac/fsl_ddr_edac.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index 10b0a46669f3d..da743cf8a95e9 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -338,11 +338,18 @@ static void fsl_mc_check(struct mem_ctl_info *mci) fsl_mc_printk(mci, KERN_ERR, "Faulty ECC bit: %d\n", bad_ecc_bit); - fsl_mc_printk(mci, KERN_ERR, - "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", - cap_high ^ (1 << (bad_data_bit - 32)), - cap_low ^ (1 << bad_data_bit), - syndrome ^ (1 << bad_ecc_bit)); + if ((bad_data_bit > 0 && bad_data_bit < 32) && bad_ecc_bit > 0) { + fsl_mc_printk(mci, KERN_ERR, + "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", + cap_high, cap_low ^ (1 << bad_data_bit), + syndrome ^ (1 << bad_ecc_bit)); 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Tue, 9 Jul 2024 20:23:47 +0000 From: Frank Li Date: Tue, 09 Jul 2024 16:23:05 -0400 Subject: [PATCH 4/6] dt-bindings: memory: fsl: Add compatible string nxp,imx9-memory-controller Message-Id: <20240709-imx95_edac-v1-4-3e9c146c1b01@nxp.com> References: <20240709-imx95_edac-v1-0-3e9c146c1b01@nxp.com> In-Reply-To: <20240709-imx95_edac-v1-0-3e9c146c1b01@nxp.com> To: York Sun , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Borislav Petkov , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1720556601; l=1903; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=sEQ2s5DOaJpFElpdRGOeANeI0KjitaYMW7pvhbkIm/o=; b=Vn4XK7e4+72Pi4m92N5oOm/JDIRynHBP8bwx2ivq6Qq5Aq+1ByMcJxulB0TemTYYyw79FST35 MR90BpuRCgwC/GukSWTTSdmCUIs1G8hfDgKGMUAZTUuKcCN6oq/Lge8 X-Developer-Key: i=Frank.Li@nxp.com; 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But some register layout has a little bit difference, so add new compatible string 'nxp,imx9-memory-controller' for it. imx9 need two 'reg', one for DDR controller and the other is ECC inject engine register space. Keep the same restriction for other compatible string. Signed-off-by: Frank Li Reviewed-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/fsl/fsl,ddr.yaml | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml index 84f778a99546b..e0786153eec73 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml @@ -40,6 +40,7 @@ properties: - fsl,p1021-memory-controller - fsl,p2020-memory-controller - fsl,qoriq-memory-controller + - nxp,imx9-memory-controller interrupts: maxItems: 1 @@ -51,13 +52,41 @@ properties: type: boolean reg: - maxItems: 1 + items: + - description: Controller register space + - description: Inject register space + minItems: 1 + + reg-names: + items: + - const: ctrl + - const: inject + minItems: 1 required: - compatible - interrupts - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - nxp,imx9-memory-controller + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: false + additionalProperties: false examples: From patchwork Tue Jul 9 20:23:06 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?Fm6Mc+Xcw2S85SRuc/FlgRGZNLcX?= =?utf-8?q?nt0EDo/JjZ+KqcaCMGkWuRzS3XwE7Snq5+vTIuA7UTU4O+gXaD05Chw0vvp/nmh1e?= =?utf-8?q?QTFdOqzqduWMXb3IwiG0uJRZ23cu2mj7Ad/EAcXSdHUECxJKrQk4C1GFOKQnEYTJT?= =?utf-8?q?stNo81c9rvx7drqG29arvK4LMo1RN4HFWuq+UUHrSW8D+Jy1Cw5PEshrrTkdiivXd?= =?utf-8?q?al9anZ6W23UxlhJtgAm8TMwOT4IGXS4FnX+CMezolYo4N3NtoarmJCpMX4C7EN6XH?= =?utf-8?q?JEF5ex+ISnVy+TU/M4JwrMzlF36mIYHKe9Qblf64PdrSUnpF5P/Jaq+d04goS2mwM?= =?utf-8?q?2XXZwQtmgUUoqWTDsO0TnyKt2hkuv5nn8QgB9on+Zob4bmBZY8tdw5O0/1roCV/Oq?= =?utf-8?q?x3jEVuN16V0buEFpzZKvEaY1Wc7uzQe23fi9sAaKvEgSpZeCcjPXbweEpFU4K2JTH?= =?utf-8?q?ln8vBmEyBu9tQSNtgsKfPHPgPRqrLfAjwkhAwiZ4+GB409ct43I9zURpXHUskXgj0?= =?utf-8?q?rGuu9jDh11J78gidSc3n7z/OE/w1OoH9SM38WuayLsGJQkf4dU914sOKC9RahfJZd?= =?utf-8?q?JIwqbbh8fgtsNIfx6I6yhUulB7ePVGPXixIM2I51YNg9W74InNrnJ1iVY23iji0+b?= =?utf-8?q?aem+W2DmoiGP21mIeBqGW8lSj2hzY+uO8oGl5RjG+npL9TUZj9fvbpvpq2B9zxzHS?= =?utf-8?q?W5yFAonOhK50RMGiKszjEI+Dz4uTF8mZZ89ho9atM+CZ/v8TkTegw35bA7MZG2FbM?= =?utf-8?q?MhwdcfUAXf/OUFZpAgtU+KpCNOq8xiSV8kYFvLlrvN15yQl/KLfzyGMVwpl4UoZDC?= =?utf-8?q?AlSjNF9dFHiE2ifky1cYlosbb2puJwp1uH01ftvniYfGKpLjYkm0F3FqhBBy69ck3?= =?utf-8?q?G/kut4Pjwf4di+XrcgDNf/td7Ph9W4cG6IafuNlEksBc9yTwodAYdJ2/LgSOp0eXc?= =?utf-8?q?WFUuqCRgK6aZz03GDnvkN+fSJUhTXbRujPJ42kbpeYAGjBQ6VZ/K4tzFnBtrvdSBO?= =?utf-8?q?jiUXXTiB8LyzXbfNNFbMLjlJ3dcwbceYgD+PMblfZY4Y+r1H7uMaH2zNzSAHJ0iGu?= =?utf-8?q?B9QXR+4DkYE5z5PCiKGsWtVrqvc19y1r27mKT+mL9mSB/c3Ra+IXeOsfvEBzpEjma?= =?utf-8?q?CGnhiKmoxvNZs85FqGrqmNKI9c//GDJxP8hjYVY3I+dNwaTjKrY1+Ny+IWmrfB0lO?= =?utf-8?q?/dm/wPu8grVuW+Gy3URCC3ydWadOeRSNJerE4cm7PqsNDxxbMPckQHbEHCAB8zZjm?= =?utf-8?q?F5rcxI1aM7uYp3MHmt60d3BDyI4/jqHnzifCQlK1pk1I3AWMhbINPN+xFAgVwBDxD?= =?utf-8?q?SDelKshx35UQGQa2JVdyIzu8gPWhUoalRiKwEVmrctNNTVhIc80ddcF48vvVYijhT?= =?utf-8?q?5uYc0z5sg999yXMmfGu33/LfDn9Jgby1Bm1kyykdta3mKqR885vJgXhZtN9b399q7?= =?utf-8?q?ubAA5T4w30+FWYLzIP4Dio4TS0cS2kJyX74wMxMLbW/D2DWvzP8WyGHdcbIs6P5Dj?= =?utf-8?q?bgKXh3tHXFYH?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: eaa65157-5fb5-4466-8a5c-08dca0550cc2 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 20:23:52.7567 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TUZ37exuyuQbl9uFcGG/cvbjh7VEIw0iyg1QGMlmELG5HIlcQ/gBnLjIwGOeTBX3KWoOu1XUgAs7oUdrdM0D3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8267 From: Ye Li i.MX9 uses an DDR controller that has registers offset and some function changed, but the ECC and Error inject functions are almost same with fsl_ddr controller. So update and re-use the driver for i.MX9. A special type is added for i.MX9 controller only to distinguish the difference. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Frank Li --- drivers/edac/fsl_ddr_edac.c | 48 ++++++++++++++++++++++++++++++++++++------ drivers/edac/fsl_ddr_edac.h | 10 +++++++++ drivers/edac/layerscape_edac.c | 1 + 3 files changed, 53 insertions(+), 6 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index da743cf8a95e9..438b995066f2a 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -31,16 +31,28 @@ static int edac_mc_idx; +static inline void __iomem *ddr_reg_addr(struct fsl_mc_pdata *pdata, unsigned int off) +{ + if (pdata->flag == TYPE_IMX9 && off >= FSL_MC_DATA_ERR_INJECT_HI && off <= FSL_MC_ERR_SBE) + return pdata->inject_vbase + off - FSL_MC_DATA_ERR_INJECT_HI + + IMX9_MC_DATA_ERR_INJECT_OFF; + + if (pdata->flag == TYPE_IMX9 && off >= IMX9_MC_ERR_EN) + return pdata->inject_vbase + off - IMX9_MC_ERR_EN; + + return pdata->mc_vbase + off; +} + static inline u32 ddr_in32(struct fsl_mc_pdata *pdata, unsigned int off) { - void __iomem *addr = pdata->mc_vbase + off; + void __iomem *addr = ddr_reg_addr(pdata, off); return pdata->little_endian ? ioread32(addr) : ioread32be(addr); } static inline void ddr_out32(struct fsl_mc_pdata *pdata, unsigned int off, u32 value) { - void __iomem *addr = pdata->mc_vbase + off; + void __iomem *addr = ddr_reg_addr(pdata, off); if (pdata->little_endian) iowrite32(value, addr); @@ -438,6 +450,9 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci) case 0x05000000: mtype = MEM_DDR4; break; + case 0x04000000: + mtype = MEM_LPDDR4; + break; default: mtype = MEM_UNKNOWN; break; @@ -471,7 +486,9 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci) dimm->grain = 8; dimm->mtype = mtype; dimm->dtype = DEV_UNKNOWN; - if (sdram_ctl & DSC_X32_EN) + if (pdata->flag == TYPE_IMX9) + dimm->dtype = DEV_X16; + else if (sdram_ctl & DSC_X32_EN) dimm->dtype = DEV_X32; dimm->edac_mode = EDAC_SECDED; } @@ -483,6 +500,7 @@ int fsl_mc_err_probe(struct platform_device *op) struct edac_mc_layer layers[2]; struct fsl_mc_pdata *pdata; struct resource r; + u32 ecc_en_mask; u32 sdram_ctl; int res; @@ -510,6 +528,8 @@ int fsl_mc_err_probe(struct platform_device *op) mci->ctl_name = pdata->name; mci->dev_name = pdata->name; + pdata->flag = (unsigned long)device_get_match_data(&op->dev); + /* * Get the endianness of DDR controller registers. * Default is big endian. @@ -538,8 +558,23 @@ int fsl_mc_err_probe(struct platform_device *op) goto err; } - sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG); - if (!(sdram_ctl & DSC_ECC_EN)) { + if (pdata->flag == TYPE_IMX9) { + pdata->inject_vbase = devm_platform_ioremap_resource_byname(op, "inject"); + if (IS_ERR(pdata->inject_vbase)) { + res = -ENOMEM; + goto err; + } + } + + if (pdata->flag == TYPE_IMX9) { + sdram_ctl = ddr_in32(pdata, IMX9_MC_ERR_EN); + ecc_en_mask = ERR_ECC_EN | ERR_INLINE_ECC; + } else { + sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG); + ecc_en_mask = DSC_ECC_EN; + } + + if ((sdram_ctl & ecc_en_mask) != ecc_en_mask) { /* no ECC */ pr_warn("%s: No ECC DIMMs discovered\n", __func__); res = -ENODEV; @@ -550,7 +585,8 @@ int fsl_mc_err_probe(struct platform_device *op) mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR | MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 | MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 | - MEM_FLAG_DDR4 | MEM_FLAG_RDDR4; + MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 | + MEM_FLAG_LPDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->edac_cap = EDAC_FLAG_SECDED; mci->mod_name = EDAC_MOD_STR; diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h index de66f9822fba1..73618f79e587f 100644 --- a/drivers/edac/fsl_ddr_edac.h +++ b/drivers/edac/fsl_ddr_edac.h @@ -39,6 +39,9 @@ #define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54 #define FSL_MC_ERR_SBE 0x0e58 +#define IMX9_MC_ERR_EN 0x1000 +#define IMX9_MC_DATA_ERR_INJECT_OFF 0x100 + #define DSC_MEM_EN 0x80000000 #define DSC_ECC_EN 0x20000000 #define DSC_RD_EN 0x10000000 @@ -46,6 +49,9 @@ #define DSC_DBW_32 0x00080000 #define DSC_DBW_64 0x00000000 +#define ERR_ECC_EN 0x80000000 +#define ERR_INLINE_ECC 0x40000000 + #define DSC_SDTYPE_MASK 0x07000000 #define DSC_X32_EN 0x00000020 @@ -65,14 +71,18 @@ #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ +#define TYPE_IMX9 0x1 /* MC used by iMX9 having registers changed */ + struct fsl_mc_pdata { char *name; int edac_idx; void __iomem *mc_vbase; + void __iomem *inject_vbase; int irq; u32 orig_ddr_err_disable; u32 orig_ddr_err_sbe; bool little_endian; + unsigned long flag; }; int fsl_mc_err_probe(struct platform_device *op); void fsl_mc_err_remove(struct platform_device *op); diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c index 0d42c1238908b..9a0c92ebbc3c4 100644 --- a/drivers/edac/layerscape_edac.c +++ b/drivers/edac/layerscape_edac.c @@ -21,6 +21,7 @@ static const struct of_device_id fsl_ddr_mc_err_of_match[] = { { .compatible = "fsl,qoriq-memory-controller", }, + { .compatible = "nxp,imx9-memory-controller", .data = (void *)TYPE_IMX9, }, {}, }; MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match); From patchwork Tue Jul 9 20:23:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13728462 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2071.outbound.protection.outlook.com [40.107.22.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2257A189F39; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 4a3f42355cb8f..6faba848fe286 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1279,6 +1279,14 @@ usbmisc2: usbmisc@4c200200 { #index-cells = <1>; }; + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = ; + little-endian; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>;