From patchwork Wed Jul 10 20:58:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13729699 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32DB1198A37; Wed, 10 Jul 2024 20:58:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645128; cv=none; b=PNWdH/wca8TSbNaGraKYfkmg05YiCnugfowPvv+zMwLg68Z/Ic7M2Pz34e42ObgO51sFTvQNRdt2PHUmJZgr5uTK8Qu/YJeemaAYUotb9P7T2j3Y9A/vn3IT+OMa9XZst4UXHtGOfvCzgTS2MpQm5DZmly/Ol3ebqHP06XFRE9w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645128; c=relaxed/simple; bh=ZCgND8fYZ7yP5CCsx/FWgBFuQOdUwdsY9anxzQLS25c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FubFY3+E0W+DdnEbxR5Dxqm9i3L+necYl+xlBiQpFkx7JxF86ZvU9N7S1D8wKdDeommbBrLmvSBuZ1XkpzGO1r4tOUv2l8yq94ZjPi/7GJW1DDw96Hu/dnkkC98sxVRqjRNd5snwQ1DZ7YLC/W+676FGWv4MU27BgRPzsINJjf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ckWBo0JT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ckWBo0JT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4631C4AF09; Wed, 10 Jul 2024 20:58:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720645127; bh=ZCgND8fYZ7yP5CCsx/FWgBFuQOdUwdsY9anxzQLS25c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ckWBo0JTLDjVfhdxzXFrTybT+54AKOBysEWDrnBK+WketDLkMCbYjqOEPjH/0kvWA uguEM/+3cftopaSoAiH3wq0Mnz39cy/a9lRiY4kbCFB+2voUwZizz/AJ1uUlL26Xqy Oub9XO/4/zJpWz71cn1jv1/krwTLcyCQMsoMeGtPPPBWKwiqbQLOyI97KheJ1wJ7Lz 4d4m9YpcBYX8CU7qZYn0SZ85fcyqtH2cKgw7RHk2cZLMtfZ7XiakVXuV6pqcrM6Gnc fiq/mORJ8x5VJIj3IfsCPvTSbZLxS6cXTrpCAIyroj/iTIP5GUh2ZetDwkMUlWcmbR TrxThg9XwuPMg== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v2 1/4] PCI: Check PCI_PM_CTRL in pci_dev_wait() Date: Wed, 10 Jul 2024 15:58:35 -0500 Message-ID: <20240710205838.2413465-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240710205838.2413465-1-superm1@kernel.org> References: <20240710205838.2413465-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello A device that has gone through a reset may return a value in PCI_COMMAND but that doesn't mean it's finished transitioning to D0. On devices that support power management explicitly check PCI_PM_CTRL on everything but system resume to ensure the transition happened. Devices that don't support power management and system resume will continue to use PCI_COMMAND. Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 35fb1f17a589c..4ad02ad640518 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1270,21 +1270,34 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) * the read (except when CRS SV is enabled and the read was for the * Vendor ID; in that case it synthesizes 0x0001 data). * - * Wait for the device to return a non-CRS completion. Read the - * Command register instead of Vendor ID so we don't have to - * contend with the CRS SV value. + * Wait for the device to return a non-CRS completion. On devices + * that support PM control and on waits that aren't part of system + * resume read the PM control register to ensure the device has + * transitioned to D0. On devices that don't support PM control, + * or during system resume read the command register to instead of + * Vendor ID so we don't have to contend with the CRS SV value. */ for (;;) { - u32 id; if (pci_dev_is_disconnected(dev)) { pci_dbg(dev, "disconnected; not waiting\n"); return -ENOTTY; } - pci_read_config_dword(dev, PCI_COMMAND, &id); - if (!PCI_POSSIBLE_ERROR(id)) - break; + if (dev->pm_cap && strcmp(reset_type, "resume") != 0) { + u16 pmcsr; + + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); + if (!PCI_POSSIBLE_ERROR(pmcsr) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D0) + break; + } else { + u32 id; + + pci_read_config_dword(dev, PCI_COMMAND, &id); + if (!PCI_POSSIBLE_ERROR(id)) + break; + } if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", From patchwork Wed Jul 10 20:58:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13729700 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BE071990A2; Wed, 10 Jul 2024 20:58:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645129; cv=none; b=Ft8Y0yvIXgBRyQY32EA6/sSkXwaItAzOqEUBJGidSlP/oA1ptSQ6RNO5lmvfv0E1KFhcch0eN8S87JRxvNdatK90ETlD9wxk/A13XZzUcBhLmyeEp1qlh4UmY3z7rNsYp/Z6M2SV5SX0XlRzP4DigBRopaqRPj41jh2nqdSdkYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645129; c=relaxed/simple; bh=Sf//l44VgFBV264bHR4zMgdtmXA3iNg9kC65iwFdMXs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=onTe/ku+LEoN4UTSjtkBaJIpWPvQ6zH8jZGwmUJ1eAZLookQ10cqXQkxL3o6T3FzQ+47UGdqxMbqrlaBaczAxtvmxwdaVPQ5A+PxFmH7tZh/UlbHKkLHsPIMi9FbVwg4YO5toT7EU2e/oAegHQTgxCr5hCrFj1i5X5uUWqCLPpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i2luYN4D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i2luYN4D" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0479C4AF16; Wed, 10 Jul 2024 20:58:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720645128; bh=Sf//l44VgFBV264bHR4zMgdtmXA3iNg9kC65iwFdMXs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i2luYN4DKORwTCxfJDxCgcPHVWXq8GKs8SVlKkDGBpVi0nCVjPIH2bXGHwnz4xvu3 1hWl3iYS2WHZmFspw9yyNv1FVKexko9S9JBpjCjrifkXVA8azcRzPEact5rE4GVe/L 7NepBgu/77bBmFJnUaEkjCpjgbDB8KPAaYBAaSUSLNTBkIqgjfm0qJ5QVD26Y6qouW N/5dk7gW3yrnmKhyEE/KproCWEQ2+UNGL5amcwJKzKYzjB0j6jr2wrq7vnV3p+WzbR 8Trf707SW2FtJ26mBNpPqJoY7BqOwn/Caqs+4fy3MGd3PTcIZzWTGO7ygsNqrvv92I +UtAlYfS+iUqQ== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v2 2/4] PCI: Verify functions currently in D3cold have entered D0 Date: Wed, 10 Jul 2024 15:58:36 -0500 Message-ID: <20240710205838.2413465-3-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240710205838.2413465-1-superm1@kernel.org> References: <20240710205838.2413465-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello It is reported that USB4 routers and downstream devices may behave incorrectly if a dock cable is plugged in at approximately the time that the autosuspend_delay is configured. In this situation the device has attempted to enter D3cold, but didn't finish D3cold entry when the PCI core tried to transition it back to D0. Empirically measuring this situation an "aborted" D3cold exit takes ~60ms and a "normal" D3cold exit takes ~10ms. The PCI-PM 1.2 spec specifies that the restore time for functions in D3cold is either 'Full context restore or boot latency'. As PCIe r6.0 sec 5.8 specifies that the device will have gone through a conventional reset it may take some time for the device to be ready. Wait up to 1 sec as specified in PCIe r6.0 sec 6.6.1 for a device in D3cold to return to D0. Signed-off-by: Mario Limonciello Reviewed-by: Ilpo Järvinen --- drivers/pci/pci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4ad02ad640518..9af324ab6bb02 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1388,6 +1388,17 @@ int pci_power_up(struct pci_dev *dev) else if (state == PCI_D2) udelay(PCI_PM_D2_DELAY); + /* + * D3cold -> D0 will have gone through a conventional reset and may need + * time to be ready. + */ + if (dev->current_state == PCI_D3cold) { + int ret; + + ret = pci_dev_wait(dev, "D3cold->D0", PCI_RESET_WAIT); + if (ret) + return ret; + } end: dev->current_state = PCI_D0; if (need_restore) From patchwork Wed Jul 10 20:58:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13729701 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AF521990DE; Wed, 10 Jul 2024 20:58:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645130; cv=none; b=Xm/VfmGRxaRf6T+U49F6OLqDSZ1VXboNnJlMxeudTzGHwTpUuNiqE5p5OZUf6Of00Eq5S06z5ORg4+V3phlPWVZYMu5XRybZxKGBoMxKt/aV7KV0Pu64meBLFJkvdywyj3kaanxXlIcNwlDOUnqSPG16lYH1jxhMBGQ73r2YcCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645130; c=relaxed/simple; bh=XkyMbsI6TVShd93USRG6pyg6b357zF8DKYVQEt0c2Zo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dv4nIy5htB2Fs8Uh1RnQvQnWKdQGO3MzNHwWGKbyeMFpE87F/uz/I2+NP0ZBkRNYIvU7ygcVgMWm2imUG4pzaBD5gRFPGG+Ewd9z2NeqEAyDQ86FJ8hwpPwqvTn0vTDYDELUNZ2dsZter+tB+FW8RHXES0fhEnQX5Mq1LbyFovQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M8GgV4WG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M8GgV4WG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F68FC32781; Wed, 10 Jul 2024 20:58:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720645130; bh=XkyMbsI6TVShd93USRG6pyg6b357zF8DKYVQEt0c2Zo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M8GgV4WG96JgK0PhhmJFp/U0GkQtLyOsnP0ZMpA31/8j5tp+klw5pD45ZAcCcfq6l UsYonROQGU7Hy6RPaZ/LvdjDXAt5q1XjSwJxErXG6dPChp3Wyoeyi6JqnlsT6x2fZa wIZzabFQKIIlNHqUY7/tysN+rCIFZvSF2b8619L9dEXehQPIqRs1hCLgTVHGmAo0H1 GvfUpGmhZTbVrgIfdrAu702IuFVkfmvV9tKCWkQYpT8Z0yfDWYjQLyJb1JN2vieSNW lwgvQi5CgTkgs2o5DLXRILtj5/KW3eNkdwzwggWPLZjuc2W3MwMftHV1DUcPQWEvO3 4SGeP3AfvNhxA== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v2 3/4] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays Date: Wed, 10 Jul 2024 15:58:37 -0500 Message-ID: <20240710205838.2413465-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240710205838.2413465-1-superm1@kernel.org> References: <20240710205838.2413465-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello As the PCI core now waits for D0 after D3cold exit, the Ryzen XHCI controllers that were quirked to not use D3cold and to add a delay on D3hot no longer need these quirks. Drop both the PCI and XHCI sets of quirks. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 17 ----------------- drivers/usb/host/xhci-pci.c | 11 ----------- drivers/usb/host/xhci.h | 11 +++++------ 3 files changed, 5 insertions(+), 34 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 568410e64ce64..942d0fe12cb1a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2059,23 +2059,6 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_nvidia_hda_pm); -/* - * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. - * https://bugzilla.kernel.org/show_bug.cgi?id=205587 - * - * The kernel attempts to transition these devices to D3cold, but that seems - * to be ineffective on the platforms in question; the PCI device appears to - * remain on in D3hot state. The D3hot-to-D0 transition then requires an - * extended delay in order to succeed. - */ -static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) -{ - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); - #ifdef CONFIG_X86_IO_APIC static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) { diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 018f242d09104..1c3c8378e6ddb 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -315,10 +315,6 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) xhci->quirks |= XHCI_U2_DISABLE_WAKE; - if (pdev->vendor == PCI_VENDOR_ID_AMD && - pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) - xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; - if (pdev->vendor == PCI_VENDOR_ID_INTEL) { xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_INTEL_HOST; @@ -750,13 +746,6 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) if (xhci->quirks & XHCI_COMP_MODE_QUIRK) pci_d3cold_disable(pdev); -#ifdef CONFIG_SUSPEND - /* d3cold is broken, but only when s2idle is used */ - if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && - xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) - pci_d3cold_disable(pdev); -#endif - if (xhci->quirks & XHCI_PME_STUCK_QUIRK) xhci_pme_quirk(hcd); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 78d014c4d884a..137955311313a 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1622,12 +1622,11 @@ struct xhci_hcd { #define XHCI_DISABLE_SPARSE BIT_ULL(38) #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) #define XHCI_NO_SOFT_RETRY BIT_ULL(40) -#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) -#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) -#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) -#define XHCI_RESET_TO_DEFAULT BIT_ULL(44) -#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) -#define XHCI_ZHAOXIN_HOST BIT_ULL(46) +#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(41) +#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(42) +#define XHCI_RESET_TO_DEFAULT BIT_ULL(43) +#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(44) +#define XHCI_ZHAOXIN_HOST BIT_ULL(45) unsigned int num_active_eps; unsigned int limit_active_eps; From patchwork Wed Jul 10 20:58:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13729702 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA7A9199229; Wed, 10 Jul 2024 20:58:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645131; cv=none; b=KkCBYnIrr86RRfuNsjtfXwapVYOhHpohKFxDO5trKINzNyeuSWNu8p4UMrORvHmHqAQUGDi+hQgDl2uLJWTBRRsysMOHDDWWfOAWm2dBdITdji7TiyAKHR2+CpwYqH/KNWj1cldcbRXbfYD4DxRcpcnv3DI6ZeNPgHSBTZe5jSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720645131; c=relaxed/simple; bh=I3YOKrgcX9tYEahHIc86VPfwH1MjXcqGLk7gRDw/2fI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nlfCf1uNVslbpIZ0woImMdNu26RK8Wh+EF/cBt4HSRZIW+SPa4/IWc8jC8mxWYFTmH0zgUdp664O4EE2S9QsVEooU9gtg1A/dzaSkZm8Te6RoPNwT8/TzvIEJrFLpmJi5odO8jK0qhXeiTFlI2L+TRVK/KaR/E7JN1o1bE5EtS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fUwEXMYc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fUwEXMYc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49E72C4AF07; Wed, 10 Jul 2024 20:58:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720645131; bh=I3YOKrgcX9tYEahHIc86VPfwH1MjXcqGLk7gRDw/2fI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fUwEXMYcVUojiT6jCDSqB/JPgH1/Q4cnLyJeW5r+bl5dTWHvRDZjjRp5VgyeXeNeP NfRXtvwFqiST+aGDNgd+YGKY/ZWvkqUP0cyUJ57b0aLCc/9ZLBszq+SNfZGBI1aCqO 2kHJCRJMBDBD6ebg/Gov98BO0PNEyIHTGnykDzFDc9battr0urkiIRH2wr/w4gQakg mvG3PFTFo763eIdQonjWHfaKTbwYGsQld4NJWBqQ3Jd+2CD+hCDPDK24X7WnndM5FT ayejLwfv8fraJIHjUV52TErFjDcBxwm0PueQwFU/zZbAnD15M348zJGDuMGGhdZjSp 1DwjKaRDus2bQ== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v2 4/4] PCI: Drop Radeon quirk for Macbook Pro 8.2 Date: Wed, 10 Jul 2024 15:58:38 -0500 Message-ID: <20240710205838.2413465-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240710205838.2413465-1-superm1@kernel.org> References: <20240710205838.2413465-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello commit 5938628c51a7 ("drm/radeon: make MacBook Pro d3_delay quirk more generic") introduced a generic quirk for Macbook Pro 8.2s that contain Radeon graphics to ensure that enough time had past when the device was powered on. As the PCI core now verifies the device is in D0 during power on this extra artificial delay is no longer necessary. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 942d0fe12cb1a..19be953c9f373 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2038,14 +2038,6 @@ static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) dev->d3hot_delay); } -static void quirk_radeon_pm(struct pci_dev *dev) -{ - if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && - dev->subsystem_device == 0x00e2) - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); - /* * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus * reset is performed too soon after transition to D0, extend d3hot_delay