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These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ signal is also an active-low signal and is used to request the reference clock. Signed-off-by: Anand Moon --- V2: Update the commit messge to describe the changs. use pinctl group as its pre define in pinctl dtsi --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) base-commit: 34afb82a3c67f869267a26f593b6f8fc6bf35905 diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 2e7512676b7e..ab3a20986c6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -301,7 +301,7 @@ &pcie30phy { &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie30x4m1_pins>; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; @@ -341,10 +341,6 @@ pcie2_2_rst: pcie2-2-rst { }; pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; };