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Thu, 11 Jul 2024 06:16:13 -0700 (PDT) Received: from eichest-laptop.gad.local ([2a02:168:af72:0:49a:1bc0:a7da:9525]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4267255858asm74132645e9.0.2024.07.11.06.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 06:16:13 -0700 (PDT) From: Stefan Eichenberger To: vkoul@kernel.org, kishon@kernel.org, sergio.paracuellos@gmail.com, florian.fainelli@broadcom.com, krzysztof.kozlowski@linaro.org, eichest@gmail.com, robh@kernel.org, frank.li@vivo.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] phy: marvell: phy-mvebu-cp110-comphy: improve eth_port1 on comphy4 Date: Thu, 11 Jul 2024 15:12:47 +0200 Message-ID: <20240711131612.98952-1-eichest@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240711_061616_674992_3275D146 X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org According to the CN9100_MPP_information document, CP_SRD4 (comphy 4) supports 2500 BASE-X and 5000 BASE-R for ETH_PORT1. I was able to test that 2500 BASE-X is indeed supported. Unfortunately, our HW does not support 5000 BASE-R, but I assume from the document that it does, so I set the muxing there too to 0x1. Signed-off-by: Stefan Eichenberger --- drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c index da5e8f4057490..fefc02d921e69 100644 --- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c +++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c @@ -244,8 +244,8 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), - ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_2500BASEX), - ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, -1, COMPHY_FW_MODE_XFI), + ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX), + ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, 0x1, COMPHY_FW_MODE_XFI), ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI), /* lane 5 */ ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),