From patchwork Fri Jul 12 08:38:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13731409 Received: from mail-oi1-f172.google.com (mail-oi1-f172.google.com [209.85.167.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3559D13DDB9 for ; Fri, 12 Jul 2024 08:39:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773552; cv=none; b=lYPQF8ptw9qa4n904rZHrkwJspnAz1qPX+DteLPuuy/AFh9J3WA7Vq9SSgcEnNqDnJAAk8/TRRDFHCdSxgZijLiWFI+fkw8OifmfGd76/N4hwOSrKZEqUQ9NN90wg2D+X74nhtqrvOT6j+0ApsWMfLLNOi2bIj/wS5tcv3jJEFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773552; c=relaxed/simple; bh=jgJLTxGXPrChjpov/CnTXn4AWGI9w4XWVBN+DHBh0xg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Zaetd+YH2T/jZeVxsragVHbvtjBGYI2jjiua3tSFQatU/QjQbB99YHl/jHkwHra4kU40KiC9bPt8OVasizQXM8i7n5vxoIapd80GGy3u5m73KWiFR9fCaiIxsuP5L8DnP+u+bddqkAhgf6vivtC3edBjL5ujyPaC+7cwdUQInpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=SmeADkoO; arc=none smtp.client-ip=209.85.167.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="SmeADkoO" Received: by mail-oi1-f172.google.com with SMTP id 5614622812f47-3c9cc681ee4so898361b6e.0 for ; Fri, 12 Jul 2024 01:39:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1720773548; x=1721378348; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=NoYP43ZgdyLcgRKntnfdP6muemOL2yUyMByTZlsLQGs=; b=SmeADkoOU9OiwI8eUymbnmKuXh8a3X1ksrsKcLF0rx70W80TR2pf19b4PR3NYqopLv gSjgIt71xZ3xmWCZcMaXFaTrpuyySXW5EgcUcrjFzc6UgbNrVxntwGJi/h0WP2cKF10O LAN8VM3kpu/uHXMmHcNjKdeEnqv0TtyXk/KjatokzCSVkjeFAK4jAXnynwHacQrZBUtU 1vl7k0hrVl4GtnYZokRLvZs/DICr0FaNkikXrXEeF4cNtB51dsa2Dm6RVWu9z95s8fkx pE0bu9iV5hAo0oH4PF565xp6az/oiSAtTqG95n+DvezkAaaprmCqTYFbDEyoWP/+dlCg n4YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720773548; x=1721378348; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NoYP43ZgdyLcgRKntnfdP6muemOL2yUyMByTZlsLQGs=; b=gfhRIOTyJWBBlsmBnGvjEGHGp9VVPU0tfHZC3fDs4C58KWU9uph6f0v38VqdUBF1Q/ U4pXsUyhXbrPMCwSNyiMw5+vpiT1T+65wvzD1bp6y/7pKwhjMMXmqyM/MpKgMlFt/I0V 5ED8DDrI1HSBicQiFVOjJtZEEJmB6OWnFKiG5yTVja17Ni8Vor7x+QTdCmuwxTqiwn20 T4wh9p/fLk3Kj1bN/g/vjRx/aiqjo+V969pPjLejYz59V9TPBPgsR8shpSPFHaNjDBF/ w6DhkmL6WFIJwFoO5i2VydWXws7+JKVIXYQLbEwczwVQH2/MwnJ8K199VBCIVG8BRC/l Qs4Q== X-Forwarded-Encrypted: i=1; AJvYcCUX/wp0kFImhywvCZ8ybLBIm5947JSEz3bdBHL2aPHyGJeFI+mFWVKhmQ7zetznnhIlD7QBOHwzApfQrLJascIQ3PSF X-Gm-Message-State: AOJu0YxrgUdVYYOqBeFE25wRoYduOJhaoqZZ7Zetd8RqFQgitfyGruAJ SvdseHfMID7rsd+FZLisaTTfFj4xa+mWHdVhd8n2CdFI8EC71B3PNIyX/dKVG0E= X-Google-Smtp-Source: AGHT+IFvHBbmqbAuR3HIaTkO4x6lvhZ0ISwrkTRlVQ6l2auVT/ORD0WyzAIWLSQFoMZSchMNJnl+UQ== X-Received: by 2002:a05:6808:309b:b0:3da:ae17:50c0 with SMTP id 5614622812f47-3daae17540emr713772b6e.1.1720773548053; Fri, 12 Jul 2024 01:39:08 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:07 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , Samuel Ortiz , Daniel Henrique Barboza , Samuel Holland , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , Kemeng Shi , "Mike Rapoport (IBM)" , Leonardo Bras , Charlie Jenkins , "Matthew Wilcox (Oracle)" , Jisheng Zhang Subject: [PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support Date: Fri, 12 Jul 2024 16:38:45 +0800 Message-Id: <20240712083850.4242-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Svade and Svadu extensions represent two schemes for managing the PTE A/D bits. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. Since the Svade extension is mandatory and the Svadu extension is optional in RVA23 profile, by default the M-mode firmware will enable the Svadu extension in the menvcfg CSR when only Svadu is present in DT. This patch detects Svade and Svadu extensions from DT and adds arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() when we have the PTE A/D bits hardware updating support. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Reviewed-by: Alexandre Ghiti --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 13 ++++++++++++- arch/riscv/kernel/cpufeature.c | 32 ++++++++++++++++++++++++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0525ee2d63c7..3d705e28ff85 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -36,6 +36,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..524cd4131c71 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -195,6 +195,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..35d7aa49785d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADE 75 +#define RISCV_ISA_EXT_SVADU 76 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index aad8b8ca51f1..ec0cdacd7da0 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -120,6 +120,7 @@ #include #include #include +#include #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) } #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include static __always_inline bool has_svnapot(void) { @@ -624,6 +624,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) return __pgprot(prot); } +/* + * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By + * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in + * DT. + */ +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5ef48cb20ee1..b2c3fe945e89 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), @@ -554,6 +556,21 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) clear_bit(RISCV_ISA_EXT_v, isainfo->isa); } + /* + * When neither Svade nor Svadu present in DT, it is technically + * unknown whether the platform uses Svade or Svadu. Supervisor may + * assume Svade to be present and enabled or it can discover based + * on mvendorid, marchid, and mimpid. When both Svade and Svadu present + * in DT, supervisor must assume Svadu turned-off at boot time. To use + * Svadu, supervisor must explicitly enable it using the SBI FWFT extension. + */ + if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); + else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't @@ -619,6 +636,21 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) of_node_put(cpu_node); + /* + * When neither Svade nor Svadu present in DT, it is technically + * unknown whether the platform uses Svade or Svadu. Supervisor may + * assume Svade to be present and enabled or it can discover based + * on mvendorid, marchid, and mimpid. When both Svade and Svadu present + * in DT, supervisor must assume Svadu turned-off at boot time. To use + * Svadu, supervisor must explicitly enable it using the SBI FWFT extension. + */ + if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); + else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); + /* * All "okay" harts should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't. From patchwork Fri Jul 12 08:38:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13731410 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CBA8142633 for ; Fri, 12 Jul 2024 08:39:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773554; cv=none; b=Yd6uAA1xXqh05+6MRA3dvKQoCi0T2/afJvmB5T4CVA14mVVCG5MrJQHjSKWPz2GWq40Ci3+TM+xCTHU4OBIXi1TkudgNZ3tzOa8BBeoTZP892mNJ/xDh/o5NlCVUlWthAT5UoJioAQ5Yf7R4iiuUKgYrEuVXTB8lPtrM77TvLiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773554; c=relaxed/simple; bh=HyKnjgHnajVWdAjv50AK0JmCEqgbEGPN3v54AqK7auo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=glqdCusGbNXEulX+I44kRxRmCIEhdfFrUPiLTjkQnwpPxYrj/PgMsLxoNjZDcx/wnmV48qmC8OriE7JFidGP94NS6HNlW62oJROhx66Njy6Z1ZpDdmhvKQ5sKQq+nqOngS2PxENZxAkOaRj0bWAnFxSyxmvr88y9BAmGQbGDODg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=BtVV/AGU; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="BtVV/AGU" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-70b04cb28acso1454600b3a.0 for ; Fri, 12 Jul 2024 01:39:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1720773552; x=1721378352; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=s8FxVWkBbUSRwzKSDXaD3IouygOhaOZodT8e7MKio/0=; b=BtVV/AGUzPc9mO+Esgacpo5S+0MRDepHc/tmeP9jDd6NCJELeWOB0QgCXwySQJAxc9 gZvL6R3TO5rNwfuH4tdYCnYzLvIQ6v1RcVQopnvg0F68RYBAX4j1GgARqnDJs53eQTEN +jDoRMR5r0s+IDF7WSXhfGdDJBZOKybNql91JFKgn/X69Eadvd96gb+dpYx5xyIALhV6 8WwoPvmx5TLYXkdqOl5n3byFByf57a0w+Q7TxvTooWNVq3j2hdysGVnN2QohTMSihP9a NK/cafxRWzM8c0KQWSkpaQp/8+dIFN+LkNEBnCQDE2HEHVzVweVIKK7qkiCXKmKgwIVg dLGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720773552; x=1721378352; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=s8FxVWkBbUSRwzKSDXaD3IouygOhaOZodT8e7MKio/0=; b=cS9tc0YDz0KStFKrDXazi/fs9qnbHJacccQQtzdAVyuLpwIajEHhHtoTV+GsA/sg9z bs1Ummzxo6KJwaJdctKOg/LM/Jkym+E10NwCkDouPkD+GOzmoMNKydBQAj52jwn3JpRu 4GTV3wassLgR+G2313BmwjCHLaDd8fS5Lv0iaKHCrA8gVyqRv0wvxDorYvYk84MoC3Px riPY/6gx/TZsYuI6tl/yj+hmNeUkRVnPz5fW+x9TpE2q7y5wfAzp6DKq87jpinkbFaKD 57kvxamCTaGlMGpcYVq0trVqMNultc3v5ILJiZA6kL5wZiXg9NDj5khe/Bv5/slcG9gA QrtA== X-Forwarded-Encrypted: i=1; AJvYcCXlkTshuXev31mWnWRoP1/QMyBSmd4kgGvnsaKe5ijPYuR9xOkghE4Wm8Ck95fMC5YgsRVwZJU62W2NN3LWTiCRUx0N X-Gm-Message-State: AOJu0Yx+bx6nh6xHp887UNwBml8Vs8+w533JqUPcEihD/cqE6JctMe8L Q4b9vF4HrAZu5jFj0jZWLb/8s2iHot3LkE7DoLU9XUJr4rg9SB4UrCwvCBrSN5Y= X-Google-Smtp-Source: AGHT+IGFZpUIicB4zZC9hrvnR3WIEBPWN8+7c0RwydpX4SwJwlx7pWYViWf5LIEdN2ZgdD/fy0d2ww== X-Received: by 2002:a05:6a00:8d95:b0:70a:f521:52da with SMTP id d2e1a72fcca58-70b6c976927mr2334016b3a.16.1720773552263; Fri, 12 Jul 2024 01:39:12 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:12 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Date: Fri, 12 Jul 2024 16:38:46 +0800 Message-Id: <20240712083850.4242-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang Acked-by: Conor Dooley Reviewed-by: Alexandre Ghiti Reviewed-by: Samuel Holland --- .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..e91a6f4ede38 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,34 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed PTE A/D + bit updates as ratified in the 20240213 version of the privileged + ISA specification. + + Both Svade and Svadu extensions control the hardware behavior when + the PTE A/D bits need to be set. The default behavior for the four + possible combinations of these extensions in the device tree are: + 1) Neither Svade nor Svadu present in DT => It is technically + unknown whether the platform uses Svade or Svadu. Supervisor + software should be prepared to handle either hardware updating + of the PTE A/D bits or page faults when they need updated. + 2) Only Svade present in DT => Supervisor must assume Svade to be + always enabled. + 3) Only Svadu present in DT => Supervisor must assume Svadu to be + always enabled. + 4) Both Svade and Svadu present in DT => Supervisor must assume + Svadu turned-off at boot time. To use Svadu, supervisor must + explicitly enable it using the SBI FWFT extension. + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware updating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade + dt-binding description for more details. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grained From patchwork Fri Jul 12 08:38:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13731411 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AC7D1448E7 for ; Fri, 12 Jul 2024 08:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773558; cv=none; b=Rp94UyN9HbBmXalNoyB3uvA/nfAbmPCMjuyluCvxxt2YUaEDgcgDwwXUSSY35syXsJjS2HOesgswdrnsfRWd5hq7S8b0rozz+bsJZCn0aMOgoHkdHWyLzedz5QVrHJwwmi8T2EFvpgtPb3H5FY07jaNqlJ6Y/EFg1B3n2Wz8gRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773558; c=relaxed/simple; bh=pqlexpUvH8SdD7gCfl41+7ECvKrO2BeW1xpubtVDq1Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=OX/XGn1ri/4Z3cNdkPA70ftngrAvWP8rHaKRvD05nu79ApJH3H6SYoCuxqsAgJD5Ync8r11Ucd7izbQKU5JJNb5huBwHaLcmhZDcTnIwjFX+aigC37Q/Kn5gbkwqpxARnra2dKIFob/c5syiPgD+lXvB+4rGGzr5id+WIDk2VdU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=KGAy22/C; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="KGAy22/C" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-70af0684c2bso1382892b3a.0 for ; Fri, 12 Jul 2024 01:39:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1720773556; x=1721378356; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=qOZOdNqYBv8WGomeUEUfCET+0Nz9/2nmPAIIjSAFF/o=; b=KGAy22/Crd5sYNFh+Pak/0vDr6WvZOkn6b+2t1pykq/tSW52UHcCkoL8L49uTZH6xx gdcErVeTz55p6k/0RgoBNLQJjByR1s0x6UOR3TpHt1Uyz5u5hilg4yef2oPxqMoWbZYy squFwoSE9PHHdhcP5w6hBHkeSenv/4BNn9ClNFUrllGzngWMr43BkerA5aOnJ2pwU9DC FMvQCPV5SSxMFRIc2kZRSabHqkRG5dvsoLc2Rf4s8zOj9DDmAw113wf0kPeqKZaiwIuD nSvP79q8UosBMQPY1qLzF4GldGChQZk3GG0/NOjJHTJtlF/dHoyzjTzrc2WpZk6FX808 NYlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720773556; x=1721378356; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qOZOdNqYBv8WGomeUEUfCET+0Nz9/2nmPAIIjSAFF/o=; b=ob7s9yyBOINvvo0yZD01M1Pr3JPlZoc1YZBe3vCOfD27C93zNOkDlucag0Y5gyCLYS nDVw2pOaL2uio9vEWSSCtsikyjiCK4EW6xHSRVUQtDfDLWYe/NtqxEDjqTkmPILLXC/J 3G/8Y/UNr3MHMhuN2zmBOBDAAnExkSnn87WQv95XMJ1ZJ3Syav3cgpdW+9wH5vsbLOb6 It7QYN2yaK2P4AkOB9QkW8vWj5PEBW0M/7yrsTFjh10WGnjaJriDudYRtjwDvQmdGMAI pXL0Ls4tkhUY2ttZf/pd8EOvZObr8k3r8HvlksLfhour0hAIcTUx+ipZGAvOiyyS8TL9 7U2Q== X-Forwarded-Encrypted: i=1; AJvYcCWkojsy4GwLe3Vz8Z0UK4PzKDOUQ1kbQ2D69K7l/EoD+6iPjxK7cgZKdm5ymq0qgFlyM63BlXWpwb/YXzO1Cxmx2UW/ X-Gm-Message-State: AOJu0Yz4Rx0ZB6YbCUauUyod3Hj07EJJxJ8D9X1cb0DFaLMVAm4jub/P SdJ7nmMStsfqgSQ3j6LKBoLUml/8RePB5mmthExs2b0lWkcxIShYBvFOtag6DuI= X-Google-Smtp-Source: AGHT+IFUgJGXqGz1rR6VQacB/sQPEJI/kBTqgZjcalyfvrrbdgNBckvS4WIfC6u8yM9C/ItjyrZEtw== X-Received: by 2002:a05:6a00:3392:b0:706:348a:528a with SMTP id d2e1a72fcca58-70b4355854fmr11327085b3a.10.1720773556295; Fri, 12 Jul 2024 01:39:16 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:16 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v7 3/4] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM Date: Fri, 12 Jul 2024 16:38:47 +0800 Message-Id: <20240712083850.4242-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svade and Svadu extensions for Guest/VM. Since the henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu extension is available for Guest/VM and the Svade extension is allowed to disabledonly when arch_has_hw_pte_young() is true. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Reviewed-by: Samuel Holland --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_onereg.c | 15 +++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index e878e7cc3978..a5e0c35d7e9a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_SSCOFPMF, + KVM_RISCV_ISA_EXT_SVADE, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 17e21df36cc1..64a15af459e0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -540,6 +540,9 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |= ENVCFG_CBZE; + if (riscv_isa_extension_available(isa, SVADU)) + cfg->henvcfg |= ENVCFG_ADUE; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { cfg->hstateen0 |= SMSTATEEN0_HSENVCFG; if (riscv_isa_extension_available(isa, SSAIA)) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 62874fbca29f..474fdeafe9fe 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) @@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -105,6 +108,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); case KVM_RISCV_ISA_EXT_V: return riscv_v_vstate_ctrl_user_allowed(); + case KVM_RISCV_ISA_EXT_SVADU: + /* + * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. + * Guest OS can use Svadu only when host os enable Svadu. + */ + return arch_has_hw_pte_young(); default: break; } @@ -167,6 +176,12 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) /* Extensions which can be disabled using Smstateen */ case KVM_RISCV_ISA_EXT_SSAIA: return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN); + case KVM_RISCV_ISA_EXT_SVADE: + /* + * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. + * Svade is not allowed to disable when the platform use Svade. + */ + return arch_has_hw_pte_young(); default: break; } From patchwork Fri Jul 12 08:38:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13731412 Received: from mail-oi1-f179.google.com (mail-oi1-f179.google.com [209.85.167.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66138140E58 for ; Fri, 12 Jul 2024 08:39:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773562; cv=none; b=aB9O9nJwDT36gzL6+DRNJteqMWWdxyULB5NSlGIFgEQ81p0rlV1UZeOitM/TLGAEQ6hdBelZjWmoApC269tKSupokAp8iKXgJI2AbivD6y+3Qo463Q7alyhPSEOFndwDweeq5j89MlSoF9FnUjms6Lvu6l4tkXVnHQK+8XSQ0e4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773562; c=relaxed/simple; bh=rAYKbcFrJvZXsWHsMuE+Qgzs7qeLTNluD8iqVeBQttI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=CYwGbQeycLFqqBP9O1hDX8bRP+2ZXL8IE8VekBcQajbZRBB7O3lwwxObaSXRORFPJPeqFjx3VJOshRgZeuqfi1c8VCrwdkJnqEd0tiW0hK+Rw4Jh2d/1aldqE8dOX3iLHcou9OabrbpUNziCh652Cnh9GXiC+sApT2l1dfnmDB8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=f2URke/+; arc=none smtp.client-ip=209.85.167.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="f2URke/+" Received: by mail-oi1-f179.google.com with SMTP id 5614622812f47-3d6301e7279so1072760b6e.3 for ; Fri, 12 Jul 2024 01:39:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1720773560; x=1721378360; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=PpDCA7CnSWtIO6seFJ4J0hDKtH06inwXMPU5CaySLhw=; b=f2URke/+ts/fgwVmW9dtm6CzYNesfhTBx6FwJbxGNxc+u8sZOT5eycV3B4/C5Yof8j 2oVsI8/o23/nyda5EheN/KAeqmlb7P31UpbLNllvWIWlwEki3ID+QbLSCnZChssPV7Be wglntLrfUUsM1+/DHGVnceBtA6rTL62iBXZEdJ53nlT+q2utrj0yHzp1jZfEzfMnstwn 4+8PfprMQO9irs0QaU4XV9S6/e6BKOIqKsYY6srjM5yV6Wl+o0Esp6vrXyJCgMJthBKW nDpGPARXfwhP8Zy6TbGSQkgrSf1hZCZBrBfGU95eIh69yvliAB+3eMgVxzL/2OyTN6LD jzYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720773560; x=1721378360; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PpDCA7CnSWtIO6seFJ4J0hDKtH06inwXMPU5CaySLhw=; b=ZKcfuKNb1Bm/3E16mBlO/zBn1diEWsOSGHn1T0Rc96jaImwgpo4zjbEcMOkHd48Q2o svMWmEpAzZD8de5yj/+K1VWqVW/hc/igDplG4gpC51+Uo5zQWrNnB0j+jGIWpy5OtUWN T8TKaz/7XRQ9d2tI/l90T4oLKLeHpUSv9ZAXkihSVRMLrnb4jSOl5dGAEwCP1Csqu5lu /3EzpdIOHkAEOmNGcM0Yw+6Wv98P2X+oWtB+TXhKKB4q6IRPmjbjrmM1Aed0BNWwxjiP Zvyw0IRKZhduEegfFlHTzQGD+zaN27fWuFoM/Edx9TRto1IJ9+6ui0988NjNqks+uKw6 gDtw== X-Forwarded-Encrypted: i=1; AJvYcCXPrh6I/oujQ6hJu98Mq51zOaAZlcRTY46+8rNnk7ZdgUjkMzEke/Un3xsgR0MJCbzhpx8e/TSxEVwP5sdCgoLkFOSL X-Gm-Message-State: AOJu0YwgZ6qjoilQ+SxnDGjYhTBcBIQrj5nk4i+mqebrHEMde3hJt7Vh AGYgd3lJKk40Jq7U8572TdhhjJPJRF7nvwk2AyjgvD/XTTeElQQC192fNLtVTTM= X-Google-Smtp-Source: AGHT+IHmBxrEAG3WPd6oj+/586lglgYzxY+9BouYb6jIFT5EHBZDlB4+cb5Y4B3ynyNiUyxupNCiwQ== X-Received: by 2002:a05:6808:1982:b0:3da:a6ce:f017 with SMTP id 5614622812f47-3daa6cef5a9mr3909532b6e.46.1720773560484; Fri, 12 Jul 2024 01:39:20 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:20 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org Subject: [PATCH v7 4/4] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test Date: Fri, 12 Jul 2024 16:38:48 +0800 Message-Id: <20240712083850.4242-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Update the get-reg-list test to test the Svade and Svadu Extensions are available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 222198dd6d04..1d32351ad55e 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -45,6 +45,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: @@ -411,6 +413,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -935,6 +939,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -991,6 +997,8 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_smstateen, &config_sscofpmf, &config_sstc, + &config_svade, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt,