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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2024 09:52:28.7556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dec7d2e-dbf4-4d16-6fd9-08dca258577e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6995 Received-SPF: permerror client-ip=40.107.244.69; envelope-from=ravi.bangoria@amd.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.142, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 12 Jul 2024 09:27:44 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Upcoming AMD uarch will support Bus Lock Detect (called Bus Lock Trap in AMD docs). Bus Lock Detect is enumerated with cpuid Fn0000_0007_ECX_x0 bit [24 / BUSLOCKTRAP]. It can be enabled through MSR_IA32_DEBUGCTLMSR. When enabled, hardware clears DR6[11] and raises a #DB exception on occurrence of Bus Lock if CPL > 0. More detail about the feature can be found in AMD APM[1]. Qemu supports remote debugging through host gdb (the "gdbstub" facility) where some of the remote debugging features like instruction and data breakpoints relies on the same hardware infrastructure (#DB, DR6 etc.) that Bus Lock Detect also uses. Instead of handling internally, KVM forwards #DB to Qemu when remote debugging is ON and #DB is being intercepted. It's Qemu's responsibility to re-inject the exception to guest when some of the exception source bits (in DR6) are not being handled by Qemu remote debug handler. Bus Lock Detect is one such case. [1]: AMD64 Architecture Programmer's Manual Pub. 40332, Rev. 4.07 - June 2023, Vol 2, 13.1.3.6 Bus Lock Trap https://bugzilla.kernel.org/attachment.cgi?id=304653 Signed-off-by: Ravi Bangoria --- Kernel and KVM patches: https://lore.kernel.org/r/20240712093943.1288-1-ravi.bangoria@amd.com target/i386/cpu.h | 1 + target/i386/kvm/kvm.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c64ef0c1a2..89bcff2fa3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -271,6 +271,7 @@ typedef enum X86Seg { | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \ | CR4_LAM_SUP_MASK)) +#define DR6_BLD (1 << 11) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) #define DR6_BT (1 << 15) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6c864e4611..d128d4e5ca 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5141,14 +5141,14 @@ static int kvm_handle_debug(X86CPU *cpu, } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { ret = EXCP_DEBUG; } - if (ret == 0) { + if (ret == 0 || !(arch_info->dr6 & DR6_BLD)) { cpu_synchronize_state(cs); assert(env->exception_nr == -1); /* pass to guest */ kvm_queue_exception(env, arch_info->exception, arch_info->exception == EXCP01_DB, - arch_info->dr6); + ret == 0 ? arch_info->dr6 ^ DR6_BLD : DR6_BLD); env->has_error_code = 0; }