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Each component of PCIe communication have the following control signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ signal is also an active-low signal and is used to request the reference clock. Rename node from 'pcie3' to 'pcie30x4' to align with schematic nomenclature. Signed-off-by: Anand Moon --- V3: use pinctrl local to board V2: Update the commit messge to describe the changs. use pinctl group as its pre define in pinctrl dtsi --- .../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 966bbc582d89..721e87a3a464 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -338,7 +338,7 @@ &pcie30phy { &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie30x4_pins>; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; @@ -377,14 +377,20 @@ pcie2_2_rst: pcie2-2-rst { }; }; - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - + pcie30x4 { pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 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Each component of PCIe communication have the following control signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ signal is also an active-low signal and is used to request the reference clock. Rename node from 'pcie2' to 'pcie30x1' to align with schematic nomenclature. Signed-off-by: Anand Moon --- .../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 721e87a3a464..c5ac233264fc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -318,7 +318,7 @@ map2 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie30x1_pins>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay"; @@ -364,16 +364,24 @@ hp_detect: hp-detect { }; pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; + }; + pcie30x1 { pcie2_0_vcc3v3_en: pcie2-0-vcc-en { rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x1_pins: pcie30x1-pins { + rockchip,pins = + /* PCIE30x1_0_CLKREQn_M1_L */ + <4 RK_PA3 4 &pcfg_pull_down>, + /* PCIE30x1_0_PERSTn_M1_L */ + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, + /* PCIE30x1_0_WAKEn_M1_L */ + <4 RK_PA4 4 &pcfg_pull_down>; }; }; From patchwork Fri Jul 12 16:45:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 13731982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB9ADC2BD09 for ; Fri, 12 Jul 2024 16:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Each component of PCIe communication have the following control signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ signal is also an active-low signal and is used to request the reference clock. Rename node from 'pcie2' to 'pcie20x1' to align with schematic nomenclature. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index c5ac233264fc..a1e83546f1be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -326,7 +326,7 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie20x12_pins>; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; @@ -363,9 +363,15 @@ hp_detect: hp-detect { }; }; - pcie2 { - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie20x1 { + pcie20x12_pins: pcie20x12-pins { + rockchip,pins = + /* PCIE20_1_2_CLKREQn_M1_L */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* PCIE_PERST_L */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + /* PCIE20_1_2_WAKEn_M1_L */ + <3 RK_PD0 4 &pcfg_pull_up>; }; };