From patchwork Fri Jul 12 18:12:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13732124 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5312517C9FF; Fri, 12 Jul 2024 18:12:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807973; cv=none; b=FCxRhGzKmfSx02YchcgqRZog9VKIa1KXCnhqcCmIPtaUJQv6dkVgYJmgqbyRW8jqnTJbhNIZRmgjrciFbXF9aK4S3IWFRlyens1+qO+dIlObR4+a28OELgO15CUK6xycEQ0Ii/da/So8eWYll99NRkzLctrThs2V8LivCCBbwbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807973; c=relaxed/simple; bh=ew5pNI3HWPmom56HlNUgJiu2Xg17zI+AJEeyLfo4fo8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HQa9sMsp7/XN7D97XnrW/hUmL1oq+iYancFC1VOQvAmpdE0YSy5mwXpfc0TtMUvIo+bwr/NhjocfReU7ioqGK23rq2I7vsOLyyHCh+LZhFx8SNt9HRtVkFCA3SY5KTsQChxvf4harjVKNaRBQlSapsZa9P9xOWAoXuG1KU1sGGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IxvLccrG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IxvLccrG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF050C4AF1B; Fri, 12 Jul 2024 18:12:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720807973; bh=ew5pNI3HWPmom56HlNUgJiu2Xg17zI+AJEeyLfo4fo8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IxvLccrGlo88juCdz6pXviETrsp2Xr2qqTdQnQpbrpu8nrbzhUQFq3495fDSKHmic 0ar+Wht+9tnskwZre+oPUh/P/3FrBEOByO+WY9vN86E3BfFdQiXUsnuYhmbVyDrDvH LUU9elXs3jO8ApIdTptHBKBzzaJforN4pEOL0xJed01Zm6wRErWB4BQ1bRX6j5Lk6h BALew+f/W0uO50Xu9q5WXEt0yLEjMBIfOwTSRfVIrBTsF7Z+cjviPBqqYYUkPLynIa eKj9HjviF1kbtiB76pdi5zp6QwCQx/46GQ3ZmlOzyzbZcH12mXjgCZDUM+8iUc+KgS wI3GTm7cHf8BA== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v3 1/5] PCI: Use an enum for reset type in pci_dev_wait() Date: Fri, 12 Jul 2024 13:12:42 -0500 Message-ID: <20240712181246.811044-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240712181246.811044-1-superm1@kernel.org> References: <20240712181246.811044-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello A string is passed to all callers of pci_dev_wait() which is utilized to demonstrate what kind of reset happened when there was a problem. This doesn't allow making the behavior for different reset types conditional though. Lay some plumbing to allow making comparisons of reset types with integers instead. No functional changes. Suggested-by: Ilpo Järvinen Signed-off-by: Mario Limonciello --- drivers/pci/pci-driver.c | 2 +- drivers/pci/pci.c | 29 +++++++++++++++++++---------- drivers/pci/pci.h | 11 ++++++++++- drivers/pci/pcie/dpc.c | 2 +- 4 files changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index af2996d0d17ff..ff97d08741df7 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -572,7 +572,7 @@ static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev) { int ret; - ret = pci_bridge_wait_for_secondary_bus(pci_dev, "resume"); + ret = pci_bridge_wait_for_secondary_bus(pci_dev, PCI_DEV_WAIT_RESUME); if (ret) { /* * The downstream link failed to come up, so mark the diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 35fb1f17a589c..115361a08d9e3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -181,6 +181,15 @@ static int __init pcie_port_pm_setup(char *str) } __setup("pcie_port_pm=", pcie_port_pm_setup); +const char * const pci_reset_types[] = { + "FLR", + "AF_FLR", + "PM D3HOT->D0", + "bus reset", + "resume", + "DPC", +}; + /** * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children * @bus: pointer to PCI bus structure to search @@ -1250,7 +1259,7 @@ void pci_resume_bus(struct pci_bus *bus) pci_walk_bus(bus, pci_resume_one, NULL); } -static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) +static int pci_dev_wait(struct pci_dev *dev, enum pci_reset_type reset_type, int timeout) { int delay = 1; bool retrain = false; @@ -1288,7 +1297,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", - delay - 1, reset_type); + delay - 1, pci_reset_types[reset_type]); return -ENOTTY; } @@ -1301,7 +1310,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) } } pci_info(dev, "not ready %dms after %s; waiting\n", - delay - 1, reset_type); + delay - 1, pci_reset_types[reset_type]); } msleep(delay); @@ -1310,10 +1319,10 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > PCI_RESET_WAIT) pci_info(dev, "ready %dms after %s\n", delay - 1, - reset_type); + pci_reset_types[reset_type]); else pci_dbg(dev, "ready %dms after %s\n", delay - 1, - reset_type); + pci_reset_types[reset_type]); return 0; } @@ -4465,7 +4474,7 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_FLR, PCIE_RESET_READY_POLL_MS); } EXPORT_SYMBOL_GPL(pcie_flr); @@ -4532,7 +4541,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) */ msleep(100); - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_AF_FLR, PCIE_RESET_READY_POLL_MS); } /** @@ -4577,7 +4586,7 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_D3HOT_D0, PCIE_RESET_READY_POLL_MS); } /** @@ -4751,7 +4760,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) * Return 0 on success or -ENOTTY if the first device on the secondary bus * failed to become accessible. */ -int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) +int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, enum pci_reset_type reset_type) { struct pci_dev *child; int delay; @@ -4885,7 +4894,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) { pcibios_reset_secondary_bus(dev); - return pci_bridge_wait_for_secondary_bus(dev, "bus reset"); + return pci_bridge_wait_for_secondary_bus(dev, PCI_DEV_WAIT_BUS_RESET); } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index fd44565c47562..88f54d22118dc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -4,6 +4,15 @@ #include +enum pci_reset_type { + PCI_DEV_WAIT_FLR, + PCI_DEV_WAIT_AF_FLR, + PCI_DEV_WAIT_D3HOT_D0, + PCI_DEV_WAIT_BUS_RESET, + PCI_DEV_WAIT_RESUME, + PCI_DEV_WAIT_DPC, +}; + /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 @@ -94,7 +103,7 @@ void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); -int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); +int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, enum pci_reset_type reset_type); static inline void pci_wakeup_event(struct pci_dev *dev) { diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index a668820696dc0..306efc399e503 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -174,7 +174,7 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, PCI_EXP_DPC_STATUS_TRIGGER); - if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) { + if (pci_bridge_wait_for_secondary_bus(pdev, PCI_DEV_WAIT_DPC)) { clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); ret = PCI_ERS_RESULT_DISCONNECT; } else { From patchwork Fri Jul 12 18:12:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13732125 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC96617D35D; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZGmcLY1c" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57E3BC4AF13; Fri, 12 Jul 2024 18:12:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720807974; bh=AMtk4b2IlFGIBldcx6HMuJbUNmXf2iqdlc1O1ICsuTg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZGmcLY1cEouptx9VXFMDD6hB8itjvpeUsKLDbxROK2AvjDLYed2Gz7BVk6YUKUjf4 M3vomZtilLfZmhhy4vS/m5DTUAXsZKse6MHPslgIxyR1dVVjPDBkM2CdzGHchF8+un M/uZ+ydwZplcCUcSTibuTuCF8XcvhF3CnVTVT3P3rPnujrbhk/+VTvxBVLf3UutyN2 zluHaFrbQoWZbNyzr/aXKKSOvfazv5e0je5UN47ELZG1CKZbTGgb4vN01opzLxcaee KkkjscBdv+SUeMaOtylR0Dtpb4/6XSWdiXI44AdDMWcA0G3WunkHVRSHYkFlUD2ivw 1Ln6qOnKSyKwQ== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v3 2/5] PCI: Check PCI_PM_CTRL instead of PCI_COMMAND in pci_dev_wait() Date: Fri, 12 Jul 2024 13:12:43 -0500 Message-ID: <20240712181246.811044-3-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240712181246.811044-1-superm1@kernel.org> References: <20240712181246.811044-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello A device that has gone through a reset may return a value in PCI_COMMAND but that doesn't mean it's finished transitioning to D0. On devices that support power management explicitly check PCI_PM_CTRL on everything but system resume to ensure the transition happened. Devices that don't support power management and system resume will continue to use PCI_COMMAND. Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 115361a08d9e3..658a139f74ab0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1279,21 +1279,33 @@ static int pci_dev_wait(struct pci_dev *dev, enum pci_reset_type reset_type, int * the read (except when CRS SV is enabled and the read was for the * Vendor ID; in that case it synthesizes 0x0001 data). * - * Wait for the device to return a non-CRS completion. Read the - * Command register instead of Vendor ID so we don't have to - * contend with the CRS SV value. + * Wait for the device to return a non-CRS completion. On devices + * that support PM control and on waits that aren't part of system + * resume read the PM control register to ensure the device has + * transitioned to D0. On devices that don't support PM control, + * or during system resume read the command register to instead of + * Vendor ID so we don't have to contend with the CRS SV value. */ for (;;) { - u32 id; - if (pci_dev_is_disconnected(dev)) { pci_dbg(dev, "disconnected; not waiting\n"); return -ENOTTY; } - pci_read_config_dword(dev, PCI_COMMAND, &id); - if (!PCI_POSSIBLE_ERROR(id)) - break; + if (dev->pm_cap && reset_type != PCI_DEV_WAIT_RESUME) { + u16 pmcsr; + + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); + if (!PCI_POSSIBLE_ERROR(pmcsr) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D0) + break; + } else { + u32 id; + + pci_read_config_dword(dev, PCI_COMMAND, &id); + if (!PCI_POSSIBLE_ERROR(id)) + break; + } if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", From patchwork Fri Jul 12 18:12:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13732126 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A64A17D898; Fri, 12 Jul 2024 18:12:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807976; cv=none; b=LWjFjIlU0z0be8pH9C322b2UPZ+JcqGWvTmeQxJWNEA2VXK117n6l1bsnL3hx3kV6qOeBemel9hER3dUJAZeAcf9N0IcoouPW+Nej7JzuDb9FoYgvjlzIvt98azx2sEVo99/Z4IhZoTX2RM/Wcf1VVvpyUOdsMoQQJEB72deU2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807976; c=relaxed/simple; bh=hLZ13tB6qAQEHvHpUsidz/Qnom4FichvzgyqtE0sOJw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZZAQNkucNpGpCk/IRrNKvlSBMeVpqIG2JZ81C6PlMdmTyOpaFKy2fUkQOSx2vxHgGGM/1oITQ5SkY8RaLDboJix0V3wtL5WJUk52KgzORnO3urufIM6eUgCiJrtVZbo7e3AMiepvfVat74f0hkRZkCTd8Ll7eqyXr2Ac075SO3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oibZr1LI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oibZr1LI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A43D8C4AF12; Fri, 12 Jul 2024 18:12:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720807975; bh=hLZ13tB6qAQEHvHpUsidz/Qnom4FichvzgyqtE0sOJw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oibZr1LIQWv1tC997nGrg8NSafblI/Uv6Mgy30HhWxzN5aOrL0agOBXi9y7Weo3CU +9pBEMHGJRcQ2XqHYqYbYT4JEUTEB0Bp/oAtwJA1+IIFKX6SPpLb9Fu+A4kaWpVS/h hgiMks3LioZnDfGWCgFneN2BeNs6/fewsrcokSP1BrEeIhwrUDcwJZp8nY2rxzLA4A gQDA/TSPNJzHPgBvwPDvMoFWgP1b+kdJTbyeCOdKAKH0DxwgHx4aMWerTMFSdg4DXV A11910we7S8LsTZ2JgsdYWJiribIqwImSJHwa1vGhp/lyQwxvmEJGgJzi71p3Blb+2 KyEChaAligCHg== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v3 3/5] PCI: Verify functions currently in D3cold have entered D0 Date: Fri, 12 Jul 2024 13:12:44 -0500 Message-ID: <20240712181246.811044-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240712181246.811044-1-superm1@kernel.org> References: <20240712181246.811044-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello It is reported that USB4 routers and downstream devices may behave incorrectly if a dock cable is plugged in at approximately the time that the autosuspend_delay is configured. In this situation the device has attempted to enter D3cold, but didn't finish D3cold entry when the PCI core tried to transition it back to D0. Empirically measuring this situation an "aborted" D3cold exit takes ~60ms and a "normal" D3cold exit takes ~6ms. The PCI-PM 1.2 spec specifies that the restore time for functions in D3cold is either 'Full context restore or boot latency'. As PCIe r6.0 sec 5.8 specifies that the device will have gone through a conventional reset, it may take some time for the device to be ready. Wait up to 1 sec as specified in PCIe r6.0 sec 6.6.1 for a device in D3cold to return to D0. Reviewed-by: Ilpo Järvinen Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 11 +++++++++++ drivers/pci/pci.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 658a139f74ab0..14dab7bc64ba4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1396,6 +1396,17 @@ int pci_power_up(struct pci_dev *dev) else if (state == PCI_D2) udelay(PCI_PM_D2_DELAY); + /* + * D3cold -> D0 will have gone through a conventional reset and may need + * time to be ready. + */ + if (dev->current_state == PCI_D3cold) { + int ret; + + ret = pci_dev_wait(dev, PCI_DEV_WAIT_D3COLD_D0, PCI_RESET_WAIT); + if (ret) + return ret; + } end: dev->current_state = PCI_D0; if (need_restore) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 88f54d22118dc..9482539b9830a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -11,6 +11,7 @@ enum pci_reset_type { PCI_DEV_WAIT_BUS_RESET, PCI_DEV_WAIT_RESUME, PCI_DEV_WAIT_DPC, + PCI_DEV_WAIT_D3COLD_D0, }; /* Number of possible devfns: 0.0 to 1f.7 inclusive */ From patchwork Fri Jul 12 18:12:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13732127 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C5F417D373; Fri, 12 Jul 2024 18:12:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807977; cv=none; b=AILqG2Aoc4s4LfEBbCwolFFVEv3QaiMlCILgQAcKt7KLXrGpBOKxzWMJmnFAiop3KmQJ/DRM5RWTxtY8XyNfqvMPzKux5m5WohlSeexwSa4n3UJcqTSOGRSzEjvRfvV46gDbC+pM5QX+lPYmVQBwcRJUcFLl5PzX3/rAsu5pbuE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807977; c=relaxed/simple; bh=OW3Vxq0AOIhs0nIM51oiQFN+ssUmHJ7uh7zPe/sF3Zs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=frsVRCIikVN6RgL0SCyAcp/q0OiH40/OnaeEg954OwyEpax+ezMoevqoULxRn8LUFr4eLBgUrM8IafSEg3sjM/2M+btAP31a/fBqFMU/9SYQp07rePwsuUFJy7XTK2MkksExTcWOErRAX9Z27ViaIaxrWTY8b5JC0cBzG3Jd8fo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hwErQmZk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hwErQmZk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFAE7C4AF16; Fri, 12 Jul 2024 18:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720807976; bh=OW3Vxq0AOIhs0nIM51oiQFN+ssUmHJ7uh7zPe/sF3Zs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hwErQmZkd/Ll6aC+yt9yfpzMQIEUW8BuJ+TBjPXV7/mxsa8lY9qJrATEp8VMJFCrZ t+QVYLVT+JcdA9pygxRY7SfHscCxP5WoFxQtQ4CaCs2WILFlZ3kcbqw35CUuWwSosF KMAaIuxmMRbPHEcQu/rqdfXQwjFt0KOkaB+IJNG4JhQeqd1yyXH+YRubETzzixH5vl 7EeMrc7MBJe5Wo0hkEUNFNgkpdOIpxXlKk43zyxwCXtWxdUkMglPKjlOHmrqPBM7UE xklKyMRrsYATk5gG1dc8C3CIVkkLf+95CINYKB9DSVa53Xw02bjhMpqcVRNIrWXkuW 5aYDXclNFCb5w== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v3 4/5] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays Date: Fri, 12 Jul 2024 13:12:45 -0500 Message-ID: <20240712181246.811044-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240712181246.811044-1-superm1@kernel.org> References: <20240712181246.811044-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello As the PCI core now has a delay after D3cold exit, the Ryzen XHCI controllers that were quirked to not use D3cold and to add a delay on D3hot no longer need these quirks. Drop both the PCI and XHCI sets of quirks. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 17 ----------------- drivers/usb/host/xhci-pci.c | 11 ----------- 2 files changed, 28 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 568410e64ce64..942d0fe12cb1a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2059,23 +2059,6 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_nvidia_hda_pm); -/* - * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. - * https://bugzilla.kernel.org/show_bug.cgi?id=205587 - * - * The kernel attempts to transition these devices to D3cold, but that seems - * to be ineffective on the platforms in question; the PCI device appears to - * remain on in D3hot state. The D3hot-to-D0 transition then requires an - * extended delay in order to succeed. - */ -static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) -{ - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); - #ifdef CONFIG_X86_IO_APIC static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) { diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 05881153883ec..8eb7abf6be1ac 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -315,10 +315,6 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) xhci->quirks |= XHCI_U2_DISABLE_WAKE; - if (pdev->vendor == PCI_VENDOR_ID_AMD && - pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) - xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; - if (pdev->vendor == PCI_VENDOR_ID_INTEL) { xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_INTEL_HOST; @@ -750,13 +746,6 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) if (xhci->quirks & XHCI_COMP_MODE_QUIRK) pci_d3cold_disable(pdev); -#ifdef CONFIG_SUSPEND - /* d3cold is broken, but only when s2idle is used */ - if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && - xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) - pci_d3cold_disable(pdev); -#endif - if (xhci->quirks & XHCI_PME_STUCK_QUIRK) xhci_pme_quirk(hcd); From patchwork Fri Jul 12 18:12:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13732128 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC1A717DE03; Fri, 12 Jul 2024 18:12:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807978; cv=none; b=qtgvsa6Kxs5anu0VqNQfmYGum3x2R09v+sU+7ELzq8kGS/5y5QhTBEMHBI+anhBNI4+VVfJIuxyFuOFPX2b3oIqePuZWeDM/7TEz6Mppj99OofxJkADUI5Qiac2jtcL5fczByNVFJkT45HThkpWO6/G/1Axsot27C+Qtb2IC2eg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720807978; c=relaxed/simple; bh=I3YOKrgcX9tYEahHIc86VPfwH1MjXcqGLk7gRDw/2fI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WkIo22CRY03jOCcl4bjWXXXZeTmjXSmLzmWUD6Uwe2UG2c1BvYkkGQ6REXk/O3RTaWCX0kkD8VXdfy6aQHG/wxs1Ss1r5bmsJhEUQI5USUgNr53gviUOSe49GSrdtmwHXDpl2VrbfTWgxiqB8b0qyrzGgyC3UINplhSn6M8ZYDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XzUGdd9h; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XzUGdd9h" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 43485C4AF0B; Fri, 12 Jul 2024 18:12:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720807978; bh=I3YOKrgcX9tYEahHIc86VPfwH1MjXcqGLk7gRDw/2fI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XzUGdd9hxzX8GfjEwuF0oDiL740HXQIoEZOCyRPWXRX0Bv7uuTnG/d7jslvwJNJ2w iGV8yn3ogTMp6RQ1Po3Qpd2cxjvsk7p0U/dwie8LMWORRHHk7WxWzj8Iy3JjWZLw24 ffJyV2nIhfaKLjk9NsgGCgL8UtC5XbZD9tvZMT3WLu3z/3fM67psVQjvbpCh6v3BR7 6X2L4Da69mjTsW7snnGtDR4ynwk97E4SmfBi9CjbEUbp6OEKM1cPXbCHlESPNeFKip 9ayt7nNHMkZx/2KWUlYuT/t/f0CKULEgXeleb/78HgDcJGqHBowlotrO840eKt4m5y EnRzU3B7084uA== From: superm1@kernel.org To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , Mario Limonciello Subject: [PATCH v3 5/5] PCI: Drop Radeon quirk for Macbook Pro 8.2 Date: Fri, 12 Jul 2024 13:12:46 -0500 Message-ID: <20240712181246.811044-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240712181246.811044-1-superm1@kernel.org> References: <20240712181246.811044-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello commit 5938628c51a7 ("drm/radeon: make MacBook Pro d3_delay quirk more generic") introduced a generic quirk for Macbook Pro 8.2s that contain Radeon graphics to ensure that enough time had past when the device was powered on. As the PCI core now verifies the device is in D0 during power on this extra artificial delay is no longer necessary. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 942d0fe12cb1a..19be953c9f373 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2038,14 +2038,6 @@ static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) dev->d3hot_delay); } -static void quirk_radeon_pm(struct pci_dev *dev) -{ - if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && - dev->subsystem_device == 0x00e2) - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); - /* * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus * reset is performed too soon after transition to D0, extend d3hot_delay