From patchwork Mon Jul 15 16:45:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13733655 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 096F41CF92 for ; Mon, 15 Jul 2024 16:46:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721062004; cv=none; b=C2KigbSMUY03uaYPxbPluQgRoVHHuX+RMEOzczqdM2KG/ok2baSSBlVzi86QXPbmoIg7gybGkn5U9ofz5e4HZaDE+31PjdmoYy27OvWhVPOfnt1TraKRyvmcSbuZ6xmFSn3t3orYL82/cLFTcvXXaQbBXM2c0WAVJtlEzJ1ucW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721062004; c=relaxed/simple; bh=KxhhSwZpJ8R3MqZlHHkvsmpFuMpX/g8ZczfW80IX57A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=THOu4D+yjTW+ZaZz5N8FqdWygeATnkNLNi+DihF7kJrYbXNHnY6VuJhJvTxTIOSXtJPdXo7Uskjsx2WnuJIPbmDmIAMF7nvTc23zvtdTo4u7a9ayeMlT+Zbj9pOIhjxw/t7JSpxuFQbrmHwrsX2/I8LCuhAQDUZMfYKwbUzMG48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IjjG4rqd; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IjjG4rqd" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4266fcb311cso31517795e9.1 for ; Mon, 15 Jul 2024 09:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721062001; x=1721666801; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BE107BcHqsNE5dZ7htAOIriFiMS47OFGE7QlqBRD04Y=; b=IjjG4rqddmo1+R7YwUMVwrVcPjgO1ncmI8THmZufkkQQKruPFApvvzYEz9CWBq+H21 uYex3oKr6pdVuyW90krpVOL5AHPwUQticSVoMPR8Gg3VPp+wBc/d8f/STlLzG5ciFwKf E1hGo+I/VphlIVHxiUiCsnBqcgXIa921l6IAMPas4utyqA11KL3A3xgn5S5+zJKFkR7W bSgkHZCpiVbSD0Ee96D1cY2Xtq47d6F1AkG5VmDhmKUl9eaNZ23e1HQVvcdeQMQWGVky sQrY7Y/ei5qfmlVkBFus5154hc2vGomkaJoyvqnV+VJ2Le6ZEZX7QMCBzjqHbSZ1Ni/d YQOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721062001; x=1721666801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BE107BcHqsNE5dZ7htAOIriFiMS47OFGE7QlqBRD04Y=; b=rwz+n1wCgqtmweD95TbFqZKC0u08divdmuYF4moNnNuVlzeWjfSDcmlHME6wR7W7bU mJ9mhi5UXV89/s0BdL+AW2bz0Fb6gzmpqB0xSjhlYK1wDWpHbdThk51Dvahy/x2IPLXM a+iV9DzFsMg4Zzl1MKJgipLyCGyBJmVEJgVeNna3sr/ga+gIuFHn9Hr5PB2LH9vNGoze HdDln4oPI7xpBdY52Cmg503KwjqTH2DsvyWR6LlEhZsY4zFGTBFXvh7CZZgwcKLhRyGM py6f1zDcbeqTSKgAZvvm6xVds1WXjpz9FRJXbRwAnuFNIO7mbhb861JtzKlm17Kiy68p IsNA== X-Forwarded-Encrypted: i=1; AJvYcCVX5khdZ53YIAgFqpYgoNs8WvTQ0bw+q3yQ+3YsJoDxzdZF3II8+/NQi/z0s617R7N+FDIUlbnuj+s+6WJ6zSvr2lJF X-Gm-Message-State: AOJu0Yyq8XcaEzLfsEZKdpQUqvmzyPV8WSfb/5wAAcEwfHF/4tHStuzq MyTaPo7+7xcQORXBWvu9CUG0Jmb0i3nFdAgujeQcCogM/5sDBMdf X-Google-Smtp-Source: AGHT+IHIy6chjAutKf/iJIZQURe9szXYTSWbYLQqamzyq1p7dzNS2ZlGs2F6yEGiZtrsigYIbUcOnQ== X-Received: by 2002:a05:600c:4e90:b0:426:5d0d:a2c9 with SMTP id 5b1f17b1804b1-427b8893008mr1417175e9.10.1721062001372; Mon, 15 Jul 2024 09:46:41 -0700 (PDT) Received: from playground.localdomain ([188.25.209.252]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e7749esm94316975e9.2.2024.07.15.09.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jul 2024 09:46:40 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: reset: add schema for imx8ulp SIM reset Date: Mon, 15 Jul 2024 12:45:12 -0400 Message-Id: <20240715164514.8718-2-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240715164514.8718-1-laurentiumihalcea111@gmail.com> References: <20240715164514.8718-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea Add schema for imx8ulp's SIM reset controller. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- .../reset/nxp,imx8ulp-avd-sim-reset.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml new file mode 100644 index 000000000000..ae03c5750fa7 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nxp,imx8ulp-avd-sim-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP System Integration Module Reset Controller + +maintainers: + - Liu Ying + +description: > + Some instances of i.MX8ULP's SIM may offer control + over the reset of some components of a certain domain + (e.g: AVD-SIM). + +properties: + compatible: + items: + - enum: + - nxp,imx8ulp-avd-sim-reset + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#reset-cells': + const: 1 + + mux-controller: + $ref: /schemas/mux/reg-mux.yaml# + +required: + - compatible + - reg + - '#reset-cells' + - mux-controller + - clocks + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim-reset", "syscon"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + #reset-cells = <1>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; From patchwork Mon Jul 15 16:45:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13733656 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A770481CE for ; Mon, 15 Jul 2024 16:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721062007; cv=none; b=qg9fgrHZV+QgfK+3Jgyac2p2fZ+oaoUoI9Ek/W9PhIELdb/DzF/I0btAOL+YruPHbUOFLMV9etWUsYsdjnSNJjXE9w1ly5FevGsGfLshXazLxSqbTuhfuBDbyNIooMVJXIwyl77r56J1sDbKqBRKF8WIaR71zpPYsj6WnFpTCPg= ARC-Message-Signature: i=1; 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Mon, 15 Jul 2024 09:46:43 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] reset: add driver for imx8ulp SIM reset controller Date: Mon, 15 Jul 2024 12:45:13 -0400 Message-Id: <20240715164514.8718-3-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240715164514.8718-1-laurentiumihalcea111@gmail.com> References: <20240715164514.8718-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea Certain components can be reset via the SIM module. Add reset controller driver for the SIM module to allow drivers for said components to control the reset signal(s). Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-imx8ulp-sim.c | 106 ++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 drivers/reset/reset-imx8ulp-sim.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 67bce340a87e..8e9cbf2859d6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -100,6 +100,13 @@ config RESET_IMX8MP_AUDIOMIX help This enables the reset controller driver for i.MX8MP AudioMix +config RESET_IMX8ULP_SIM + tristate "i.MX8ULP SIM Reset Driver" + depends on ARCH_MXC + help + This enables the SIM (System Integration Module) reset driver + for i.MX8ULP SoC. + config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 27b0bbdfcc04..685e08982283 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_GPIO) += reset-gpio.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o +obj-$(CONFIG_RESET_IMX8ULP_SIM) += reset-imx8ulp-sim.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_K210) += reset-k210.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o diff --git a/drivers/reset/reset-imx8ulp-sim.c b/drivers/reset/reset-imx8ulp-sim.c new file mode 100644 index 000000000000..04ff11d41e10 --- /dev/null +++ b/drivers/reset/reset-imx8ulp-sim.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N 0 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N 1 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N 2 + +#define IMX8ULP_SIM_RESET_NUM 3 + +#define AVD_SIM_SYSCTRL0 0x8 + +struct imx8ulp_sim_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const u32 imx8ulp_sim_reset_bits[IMX8ULP_SIM_RESET_NUM] = { + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N] = BIT(3), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N] = BIT(4), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N] = BIT(5), +}; + +static inline struct imx8ulp_sim_reset * +to_imx8ulp_sim_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct imx8ulp_sim_reset, rcdev); +} + +static int imx8ulp_sim_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr = to_imx8ulp_sim_reset(rcdev); + const u32 bit = imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, 0); +} + +static int imx8ulp_sim_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr = to_imx8ulp_sim_reset(rcdev); + const u32 bit = imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, bit); +} + +static const struct reset_control_ops imx8ulp_sim_reset_ops = { + .assert = imx8ulp_sim_reset_assert, + .deassert = imx8ulp_sim_reset_deassert, +}; + +static const struct of_device_id imx8ulp_sim_reset_dt_ids[] = { + { .compatible = "nxp,imx8ulp-avd-sim-reset", }, + { /* sentinel */ }, +}; + +static int imx8ulp_sim_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx8ulp_sim_reset *simr; + int ret; + + simr = devm_kzalloc(dev, sizeof(*simr), GFP_KERNEL); + if (!simr) + return -ENOMEM; + + simr->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(simr->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(simr->regmap), + "failed to get regmap\n"); + + simr->rcdev.owner = THIS_MODULE; + simr->rcdev.nr_resets = IMX8ULP_SIM_RESET_NUM; + simr->rcdev.ops = &imx8ulp_sim_reset_ops; + simr->rcdev.of_node = dev->of_node; + + ret = devm_of_platform_populate(dev); + if (ret) + return ret; + + return devm_reset_controller_register(dev, &simr->rcdev); +} + +static struct platform_driver imx8ulp_sim_reset_driver = { + .probe = imx8ulp_sim_reset_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = imx8ulp_sim_reset_dt_ids, + }, +}; +module_platform_driver(imx8ulp_sim_reset_driver); + +MODULE_AUTHOR("Liu Ying "); +MODULE_DESCRIPTION("NXP i.MX8ULP System Integration Module Reset driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Jul 15 16:45:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13733657 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DF684D8CB for ; Mon, 15 Jul 2024 16:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721062010; cv=none; b=sk3ZeEWtnPU2nm/pDj4NdJl7g5wgOMcBXigpFEKKfyYPn520DnpOfTNunqMwBquGN4W4MDVUdO3e9DO2ruXMO6qW/1kJMysldsZHW7dgSIeCmfv6ePNcNNrOErynGnPImz9mf5DnDqMAfU89hnpMXv04eUcD2AtFc939mlG0BwA= ARC-Message-Signature: i=1; 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Mon, 15 Jul 2024 09:46:45 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: imx8ulp: add AVD-SIM node Date: Mon, 15 Jul 2024 12:45:14 -0400 Message-Id: <20240715164514.8718-4-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240715164514.8718-1-laurentiumihalcea111@gmail.com> References: <20240715164514.8718-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea Add node for imx8ulp's AVD-SIM module. This also includes its children. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index e32d5afcf4a9..1ffa4da23042 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -614,6 +614,19 @@ per_bridge5: bus@2d800000 { #size-cells = <1>; ranges; + avd_sim: syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim-reset", "syscon"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + #reset-cells = <1>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>;