From patchwork Tue Jul 16 10:30:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F694C3DA59 for ; Tue, 16 Jul 2024 10:31:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=m+t2iUwoBkyJVwzS5G9sIz5eBU+IKXxBFR+xf16zt+k=; b=WX7pbdEpH55/Jo6nYMF82fu3ix ekgk6HjalvztW/HCadS/AGgGIr48ija5j7sAN8RfmGNAJyZr9FtWfBZJxonSc1jHa3rsyaPmKxM33 +ZFVYucNDXngJhvc+zyD7n0IETs1380iD0fQU4GBIfgZJ5d0ukBmVWvagEd83S7ler6EiUQ574Pi5 Lq3x1FZVJj1BCf3iOlEETugmtnQyRkXd2vMp0uuDESAFXAzab9ADHrMsRLuLrithBZvmaoXFOk5Xd rQzlEhD+KP29a5o5dsboVJtrs1kwT18wdnj09lhIGBI685k4Rk9i/fo3OCIbPznci/Uc4xxu0XUzX wpeASSBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSo-0000000A2hg-2VUl; Tue, 16 Jul 2024 10:31:18 +0000 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSB-0000000A2Q7-2Uny for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:41 +0000 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4266ea6a488so41801115e9.1 for ; Tue, 16 Jul 2024 03:30:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125837; x=1721730637; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m+t2iUwoBkyJVwzS5G9sIz5eBU+IKXxBFR+xf16zt+k=; b=JZy43d2A67L3dmB7tw5MfisNh5K3IC8COXhe7LCb+Dq2GOrVilPnfnDWSIBJTkua14 AgWnJBKsJ3SoQXDpPkw6F8MiCw63HOy3OPWU37Yksaz9EVVpyCdJi5kCRkSoiKhGyC48 trpVUpOCw6rDodYq4sBTQf3LJQ94Ty866Ke5J0LHeJGy4GI8qZrBZk3kkCkm8mn8hVwe 9MqJR8VSIbiQVVO4pDAUTFjtzXjxuFMEzgyErAB4s9mQ6FNSmPuDdKeGPXWdgh61GKEj 8icimnhvvSRHPxTom1Bu5T1hwwTey89T1BTFOEDXFHzjVY/3MC4nA1n3l7amW3X905H+ eb5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125837; x=1721730637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m+t2iUwoBkyJVwzS5G9sIz5eBU+IKXxBFR+xf16zt+k=; b=wk4C+XRuBybYb3DvqzUktf1d4DFubSnKxzcmrtmUtR0mqw7Xp4TKll9AYp8AWyvR8E 223prVaoCTch1T95QPO0i8mTWspXI5CCR3RHrbn2+22T0zaRxjKvo+kNJGExPLfxpc/A SeRZqqJBoy/LfitV6BbZJ1B/262HLweUU7KFGieWHFVGjj+YFgOXGgMKgvSIgi7RIs7b fdSBrfOD63EgWmiSz8G3iuZ4APgld7nbUNSB+85mMb2CE/D6AEmokoYfuovAq0E7jRLv kZt/c8ygM6eSm/ZSCtNyEElKqVYs9nOoyE+NGINecx+L7GLGfEDFIWcT6GAXzliT0ZCF jPyw== X-Forwarded-Encrypted: i=1; AJvYcCWADmgAiDgpaFAnQyvGOsBpuy+mu6Qp1JbzGlodY9yCMSYf/uHK8Yjxu3XTqzkMZ30eaMJj+kflonkwZYj4nRHY7mdQ8yIhJscYnPXh4SCE8+xj6qo= X-Gm-Message-State: AOJu0Yzw7xClVWCa54Y6fAGo7p8vWgPqMS9PKFQvwpW1XkwUoObt41Gr f2TS5WUMdWPYv8mBoaUNX6ZTiSEAlhgsAlbE48ACgbXY306kpzS5j4kuqEp8eC8= X-Google-Smtp-Source: AGHT+IHoCx27U64ppPVt17G0OQgQVeXv/aVHB8D419FiaAyPY/jxCEMgyQzJMiTajzb/yMCyNj5SZA== X-Received: by 2002:a05:600c:4f44:b0:424:aa35:9fb9 with SMTP id 5b1f17b1804b1-427ba64ce8dmr13240765e9.2.1721125837292; Tue, 16 Jul 2024 03:30:37 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 01/11] dt-bindings: mfd: renesas,r9a08g045-vbattb: Document VBATTB Date: Tue, 16 Jul 2024 13:30:15 +0300 Message-Id: <20240716103025.1198495-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033039_665459_1F9EAF21 X-CRM114-Status: GOOD ( 15.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. Add documentation for it. Signed-off-by: Claudiu Beznea --- Changes in v2: - changed file name and compatible - updated title, description sections - added clock controller part documentation and drop dedicated file for it included in v1 - used items to describe interrupts, interrupt-names, clocks, clock-names, resets - dropped node labels and status - updated clock-names for clock controller to cope with the new logic on detecting the necessity to setup bypass .../mfd/renesas,r9a08g045-vbattb.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml diff --git a/Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..30e4da65e2f6 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + ranges: true + + interrupts: + items: + - description: tamper detector interrupt + + interrupt-names: + items: + - const: tampdi + + clocks: + items: + - description: VBATTB module clock + + clock-names: + items: + - const: bclk + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^clock-controller@1c+$": + type: object + description: VBATTCLK clock + + properties: + compatible: + const: renesas,r9a08g045-vbattb-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: input clock for VBATTCLK + + clock-names: + description: | + Use xin if connected to an external crystal oscillator. + Use clkin if connected to an external hardware device generating the + clock. + enum: + - xin + - clkin + + '#clock-cells': + const: 0 + + renesas,vbattb-load-nanofarads: + description: load capacitance of the on board xtal + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 4000, 7000, 9000, 12500 ] + + required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - renesas,vbattb-load-nanofarads + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + vbattb@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + ranges = <0 0 0x1005c000 0 0x1000>; + interrupts = ; + interrupt-names = "tampdi"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names = "bclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@1c { + compatible = "renesas,r9a08g045-vbattb-clk"; + reg = <0 0x1c 0 0x10>; + clocks = <&vbattb_xtal>; + clock-names = "xin"; + #clock-cells = <0>; + renesas,vbattb-load-nanofarads = <12500>; + }; + }; From patchwork Tue Jul 16 10:30:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 511A0C3DA59 for ; Tue, 16 Jul 2024 10:31:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wPLuLQoZENDdi//jkP+m+sJa9j1xpR49CY9yYB9V7TA=; b=wCv+VMTa2WokwPU3z47SJgrRDO VRnwlflmLq+u8VUEMWXjky94kbAb8H7iVyQhsCfxYbgaxLFVeyI9FLB48LjPSRAHAlMGbXfTSauQy J1nnsxiy3wkwbJqxlY7kBxA8tkse9b5ApxYg0TZVWY3O960WgK5BmIh0iSXVWIaP1/CGqP+EEwavr LrzFVQl38nGn4jyX+IQfF5D7lGE1ppfgxRhTxKdpJlw6QidEWPX/aX/ZEuqaiA2QGZXCf6G4Ctbqj C0bfXdi1oyvRxYZgEb2wx3YL2kTW1QIP6Fo8UtDLo6daz0FO30oyspfpRiKgdCIoap9j+lEgW5TLj l4B5HMKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfT6-0000000A2of-0GIb; Tue, 16 Jul 2024 10:31:36 +0000 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSC-0000000A2Qr-3J9P for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:42 +0000 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-427b4c621b9so10301215e9.1 for ; Tue, 16 Jul 2024 03:30:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125839; x=1721730639; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wPLuLQoZENDdi//jkP+m+sJa9j1xpR49CY9yYB9V7TA=; b=Z1KPLTfjVOyrpN3VOwHfbTRDqrUxXFJvNLb+6CWjCdM2aWuChjtklke0+N9oLMxTXd adUGYJUGmTFjy87GRQkTF0ejozVjOhaSuaZcDzuD6sfVdSd2aJwWlASCYsbGbauUxa+A B1h+QxeI0QFB8s7pF2VByiarIJx4CSq/ouOfrX9/X2rEX62F4+6dj3dhX8CdZLnyOGdE 1o+QDDQJZLEQflh2o2i6aQBWBHLown+4s9PvU0E/Ue3+Vmb6qbOEuOpQ4JgiqcRy9uO9 YztyBEYZbLxvYm2NWHKHL0+AUEVpsiA8AUerp8yCecWeC1dFtA9o5p02KDKd8LP1rcvz NRlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125839; x=1721730639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wPLuLQoZENDdi//jkP+m+sJa9j1xpR49CY9yYB9V7TA=; b=ATfTRIIoHpfLPpf0hxKQVOkc39M7fOhkldMT1oh/VenJjPT+F/ljC1yUqpYumYOGXx OSPO5a6RRhhwzgT+wIFlhFChacYd2GUaQNM65LyzRUc5neIykhCBfOWMcwr15L1n2qsz elmwPpKdt8b0z7LyqmcBI4jfuZEfsv+x0e+I3qfSWLGaSAwV8YIgKofScZ/TOGNV7pNP eleJ1HOyzUYCioiZPWEsh90bJ8gy0hj4EIhKzAIJSa5jPLieNmKm9QMFaHEqIjVNzUKc qgaXn+3+O+EQCJ1vysBoCBNoefu6ghvwEfhJrqQ6L50IiYTdsGDGH4piuR0MPXYqUi3t uPSQ== X-Forwarded-Encrypted: i=1; AJvYcCUaI/Gk2YQ/K8rKqMQmlIp6KAnvqiMu9ijyDuFBk+R59LtsP17DXpmcRIDmmPsYSX/4vSlZnmSdvPlSrdzGZq3Cg9/i1BrR9v1D9mQete+QNQvjbWE= X-Gm-Message-State: AOJu0YyC31oKU/4X0nBFNfHKAtg9iuVLVcIS8DiuMQkNCWXze7esYl9u Y8fFGutcKYT/C6Li4JVcq+elnqEey4l7FzW2cC6vM7ejaJXF8rhaDnuLQKGE7Tg= X-Google-Smtp-Source: AGHT+IHVW6yRfdgEc3IWW0j9GtIckJ7vtGhNTVh5Ka58Ken968QRPKCQQvNko4nwFp7mgOiOKSesPg== X-Received: by 2002:a05:600c:4e92:b0:426:5cee:4abc with SMTP id 5b1f17b1804b1-427ba691136mr12483235e9.20.1721125839410; Tue, 16 Jul 2024 03:30:39 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:38 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 02/11] mfd: renesas-vbattb: Add a MFD driver for the Renesas VBATTB IP Date: Tue, 16 Jul 2024 13:30:16 +0300 Message-Id: <20240716103025.1198495-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033040_859522_23F06D2F X-CRM114-Status: GOOD ( 22.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Renesas VBATTB IP has logic to control the RTC clock, tamper detection and a small 128B memory. Add a MFD driver to do the basic initialization of the VBATTB IP for the inner components to work. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this driver is new drivers/mfd/Kconfig | 8 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/renesas-vbattb.c | 78 ++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/mfd/renesas-vbattb.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index bc8be2e593b6..df93e8b05065 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1383,6 +1383,14 @@ config MFD_SC27XX_PMIC This driver provides common support for accessing the SC27xx PMICs, and it also adds the irq_chip parts for handling the PMIC chip events. +config MFD_RENESAS_VBATTB + tristate "Renesas VBATTB driver" + depends on (ARCH_RZG2L && OF) || COMPILE_TEST + select MFD_CORE + help + Select this option to enable Renesas RZ/G3S VBATTB driver which + provides support for the RTC clock, tamper detector and 128B SRAM. + config RZ_MTU3 tristate "Renesas RZ/G2L MTU3a core driver" depends on (ARCH_RZG2L && OF) || COMPILE_TEST diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 02b651cd7535..cd2f27492df2 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -186,6 +186,7 @@ pcf50633-objs := pcf50633-core.o pcf50633-irq.o obj-$(CONFIG_MFD_PCF50633) += pcf50633.o obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o +obj-$(CONFIG_MFD_RENESAS_VBATTB) += renesas-vbattb.o obj-$(CONFIG_RZ_MTU3) += rz-mtu3.o obj-$(CONFIG_ABX500_CORE) += abx500-core.o obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o diff --git a/drivers/mfd/renesas-vbattb.c b/drivers/mfd/renesas-vbattb.c new file mode 100644 index 000000000000..5d71565b8cbf --- /dev/null +++ b/drivers/mfd/renesas-vbattb.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +static int vbattb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct reset_control *rstc; + int ret; + + rstc = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(rstc); + if (ret) + goto rpm_put; + + platform_set_drvdata(pdev, rstc); + + ret = devm_of_platform_populate(dev); + if (ret) + goto reset_assert; + + return 0; + +reset_assert: + reset_control_assert(rstc); +rpm_put: + pm_runtime_put(dev); + return ret; +} + +static void vbattb_remove(struct platform_device *pdev) +{ + struct reset_control *rstc = platform_get_drvdata(pdev); + + reset_control_assert(rstc); + pm_runtime_put(&pdev->dev); +} + +static const struct of_device_id vbattb_match[] = { + { .compatible = "renesas,r9a08g045-vbattb" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, vbattb_match); + +static struct platform_driver vbattb_driver = { + .probe = vbattb_probe, + .remove_new = vbattb_remove, + .driver = { + .name = "renesas-vbattb", + .of_match_table = vbattb_match, + }, +}; +module_platform_driver(vbattb_driver); + +MODULE_ALIAS("platform:renesas-vbattb"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_DESCRIPTION("Renesas VBATTB driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Jul 16 10:30:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DB60C3DA49 for ; Tue, 16 Jul 2024 10:32:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UsiHF9UHWXiqB8tTS54Gqt7gUxmJuXlqvb9fFcrRGd4=; b=0kX9NTEokFAcDF0HQqgDOMhkgd iHHvZaD0mLdkeVAQ/A5YXgKIqj/YXOCIZQYeUn0/OSxOM4ovwVLLjmJO8YQMgwQWMGtwjmf3BG2IO dKSAqwj3XHDhhVHsP/B7U5U95A0WdjPJKgi4fVTK0l4TtTbsaQ1xJ0F1rtn0JKScaHujZONV0cVCo /mTAXy0tgj6vKhaVCJ9XSq9dXA1K6g+4PI16qPpEH9LShFW0nPkxP29iYfbKAQ+Ojk2SqpmqfGkeh o/YbJrIiEabWU3rkzuaOrkHDXo5RpU/4ol0nN5+1B+na6x8nYLgXjh/2yC0RSfyQkJ6Ttngn9UnM8 1zs416ug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfTO-0000000A2wc-30aY; Tue, 16 Jul 2024 10:31:55 +0000 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSE-0000000A2RI-2Hym for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:44 +0000 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4266edee10cso33869145e9.2 for ; Tue, 16 Jul 2024 03:30:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125841; x=1721730641; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UsiHF9UHWXiqB8tTS54Gqt7gUxmJuXlqvb9fFcrRGd4=; b=Au/bVZy0uPntnfREiDd4Y41wh3Y1u+nQ+ngJyeaS/KNj6VjyIGN1WMbFM1NhZjTHas gBz/VSI7YNUnPuICxk0yc4Rqqy+EYzsheSmUVyybl6WXo9bKzbWdTaIM+SCtukFdPsa/ 6g/7aytruP9uQuzxbaYsNUhCRnvBG63hw8F8WpL6BZuWuCBcj79BgXnnyzHb8zFCVhCb V66ZZeeXzkY5Wble2AfmwR49CpTq9/PeVi7miASuzwow2rxd5odY4CT9RPpMgU6dB959 I/jeOstKX/aF95WLPpsk7viP0J4GrFpn1pbnz5ct6W9eQ/jlm4O8CLoi+pJUITr2C51H uJ8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125841; x=1721730641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UsiHF9UHWXiqB8tTS54Gqt7gUxmJuXlqvb9fFcrRGd4=; b=L0X7EyE0TUQliZy/IGAXkSgMX0Q1s2cvEEG2i7KfgU8htvKez9Wrt/OpR+oNUH3m23 4fu51Wb5/wtbkdxZUMlTsL6vh+ph/GD6DXxWh0HbQ7YVg8l0Hy143yYlLDHNbdMYh4XZ +sMYHJbDtAYVQVNofQKF2i15+NRuEfwxdDjFJJuKrK1fAUfToqey6h9vPR4SU7yzLfDZ HXYWW3bbIwD0DefvIQpzmfvjBK+Bbrl/6iZ/nvOAOihfEsoDFv6DQl5ancfyAxwa93ak 81clC/vcYen3wstefwogKVf0gSDXZFougREmfhwC858NmK0Sn3P6fNJordMDSqW//44I lH+g== X-Forwarded-Encrypted: i=1; AJvYcCUoX6w5B3QVDRcsCPMz57GwRMEr4CAvuySZRbuDQFz3hvEBhLcs4A4KWUrgagDJIJZkq3tEbtg3cLCqEXw4cbKWAMZR75TPmU1PJ0Q9gqjWxbZqbwk= X-Gm-Message-State: AOJu0YyfFDN7Q6L8u4H34JflhQzjNvS4Cm4seBBKayeeVHwcTeGTp0Go BbH+pCrjCIt1sOxubtaXyOaQ16XcfC6c5+jIQGkz/dmJcaWeobb+TKuJZMCoDtI= X-Google-Smtp-Source: AGHT+IFeE6ju3CaHVf1REaatVqyeVrgOXii30q0HVq5lQbTES2loCmA1tuKk+ODjr1JSy91v2RZI8A== X-Received: by 2002:a05:600c:470f:b0:426:6353:4b88 with SMTP id 5b1f17b1804b1-427ba70097amr10672395e9.37.1721125840937; Tue, 16 Jul 2024 03:30:40 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 03/11] clk: renesas: clk-vbattb: Add VBATTB clock driver Date: Tue, 16 Jul 2024 13:30:17 +0300 Message-Id: <20240716103025.1198495-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033042_619961_FFFFF07E X-CRM114-Status: GOOD ( 27.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal oscillator or an external clock device. The driver detects the type of the input clock based on the device tree clock name (xin for crystal, clkin for external clock device). The load capacitance of the on-board oscillator need to be configured with renesas,vbattb-load-nanofarads DT property. Signed-off-by: Claudiu Beznea --- Changes in v2: - updated patch description - added vendor name in Kconfig flag - used cleanup.h lock helpers - dropped the MFD code - updated registers offsets - added vbattb_clk_update_bits() and used it where possible - added vbattb_clk_need_bypass() to detect the bypass setup necessity - changed the compatible and driver names drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 212 +++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 4410d16de4e2..1f5f38136eb2 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -228,6 +228,11 @@ config CLK_RZG2L bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RENESAS_VBATTB + bool "Renesas VBATTB clock controller" + depends on MFD_RENESAS_VBATTB + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index f7e18679c3b8..84a2783a7b46 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..8effe141fc0b --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define VBATTB_BKSCCR 0x0 +#define VBATTB_BKSCCR_SOSEL BIT(6) +#define VBATTB_SOSCCR2 0x8 +#define VBATTB_SOSCCR2_SOSTP2 BIT(0) +#define VBATTB_XOSCCR 0x14 +#define VBATTB_XOSCCR_OUTEN BIT(16) +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @hw: clk hw + * @lock: lock + * @load_capacitance: load capacitance + */ +struct vbattb_clk { + void __iomem *base; + struct clk_hw hw; + spinlock_t lock; + u8 load_capacitance; +}; + +#define to_vbattb_clk(_hw) container_of(_hw, struct vbattb_clk, hw) + +static void vbattb_clk_update_bits(void __iomem *base, u32 offset, u32 mask, u32 val) +{ + u32 tmp; + + tmp = readl_relaxed(base + offset); + tmp &= ~mask; + tmp |= (val & mask); + writel_relaxed(tmp, base + offset); +} + +static int vbattb_clk_enable(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk = to_vbattb_clk(hw); + void __iomem *base = vbclk->base; + + guard(spinlock)(&vbclk->lock); + + vbattb_clk_update_bits(base, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, 0); + vbattb_clk_update_bits(base, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN | VBATTB_XOSCCR_XSEL, + VBATTB_XOSCCR_OUTEN | vbclk->load_capacitance); + + return 0; +} + +static void vbattb_clk_disable(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk = to_vbattb_clk(hw); + void __iomem *base = vbclk->base; + + guard(spinlock)(&vbclk->lock); + + vbattb_clk_update_bits(base, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN, 0); + vbattb_clk_update_bits(base, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, VBATTB_SOSCCR2_SOSTP2); +} + +static int vbattb_clk_is_enabled(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk = to_vbattb_clk(hw); + void __iomem *base = vbclk->base; + unsigned int xosccr, sosccr2; + + guard(spinlock)(&vbclk->lock); + + xosccr = readl_relaxed(base + VBATTB_XOSCCR); + sosccr2 = readl_relaxed(base + VBATTB_SOSCCR2); + + return ((xosccr & VBATTB_XOSCCR_OUTEN) && !(sosccr2 & VBATTB_SOSCCR2_SOSTP2)); +} + +static const struct clk_ops vbattb_clk_ops = { + .enable = vbattb_clk_enable, + .disable = vbattb_clk_disable, + .is_enabled = vbattb_clk_is_enabled, +}; + +static int vbattb_clk_validate_load_capacitance(struct vbattb_clk *vbclk, u32 load_capacitance) +{ + switch (load_capacitance) { + case 4000: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int vbattb_clk_need_bypass(struct device *dev) +{ + struct clk *clkin, *xin; + + clkin = devm_clk_get_optional(dev, "clkin"); + xin = devm_clk_get_optional(dev, "xin"); + + if (!IS_ERR_OR_NULL(clkin) && !IS_ERR_OR_NULL(xin)) + return -EINVAL; + else if (!clkin && !IS_ERR_OR_NULL(xin)) + return 0; + else if (!IS_ERR_OR_NULL(clkin) && !xin) + return 1; + + return -EINVAL; +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data parent_data = {}; + struct device *dev = &pdev->dev; + struct clk_init_data init = {}; + struct vbattb_clk *vbclk; + u32 load_capacitance; + struct clk_hw *hw; + int ret, bypass; + + vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + vbclk->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + bypass = vbattb_clk_need_bypass(dev); + if (bypass < 0) { + return bypass; + } else if (bypass) { + parent_data.fw_name = "clkin"; + bypass = VBATTB_BKSCCR_SOSEL; + } else { + parent_data.fw_name = "xin"; + } + + ret = of_property_read_u32(np, "renesas,vbattb-load-nanofarads", &load_capacitance); + if (ret) + return ret; + + ret = vbattb_clk_validate_load_capacitance(vbclk, load_capacitance); + if (ret) + return ret; + + vbattb_clk_update_bits(vbclk->base, VBATTB_BKSCCR, VBATTB_BKSCCR_SOSEL, bypass); + + spin_lock_init(&vbclk->lock); + + init.name = "vbattclk"; + init.ops = &vbattb_clk_ops; + init.parent_data = &parent_data; + init.num_parents = 1; + init.flags = 0; + + vbclk->hw.init = &init; + hw = &vbclk->hw; + + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ret; + + return of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,r9a08g045-vbattb-clk" }, + { /* sentinel */ } +}; + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "renesas-vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Tue Jul 16 10:30:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56070C3DA59 for ; Tue, 16 Jul 2024 10:32:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DutJfFYyPW6LbOov2zw2hBuFnpsIDvuTXHPgZwrrhHw=; b=nPwSQAWlKztaX92ysMy/7gmSDT dwWVGRyIfFy5BecimelgYril5AC13cRP4GhVLZHLPKj4H5t6khHsEXXQHd9A3x5xHGGreD8frp5nt d6NY8dZAegT5EUpCmRnbz94UlFpoMsB2R1+PrF07PlgBOJEsHN5YP7TCuydv2sT8bX6U71cfql2ec dBTxEfhrb1VQ+NwSlm6cEE1VWpx0EDAooddMuC0zF0PSS5k5qpzXtjHsr4xL+8ZiePmJcQU8TuIRB 1NccPsO1yN9uCHFHc5LXE4yJ2xAcyp3S7iD+knheP9FovhobQw5kCv05wJ+gcKwkIHs+omAHejy0J zKqqUj9g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfTh-0000000A34b-0uGB; Tue, 16 Jul 2024 10:32:13 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSG-0000000A2Rt-22Ni for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:46 +0000 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-367a9ab4d81so3235532f8f.1 for ; Tue, 16 Jul 2024 03:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125842; x=1721730642; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DutJfFYyPW6LbOov2zw2hBuFnpsIDvuTXHPgZwrrhHw=; b=fR9Dv4F8bGA+iTzHe25CdF8rbvgadByREFApXpLAuilokQw5z24S6TVbla+jDg4fs2 HMaGyufVugMbozkxtoAWy5RrTp+zqjV7rVtzRuydyi2P9QEf0y6iXPc01gXhgEDSDwcr eLbTZB+MPmGYaaC1mmR2xvI6IrAHr8VeP4GxYMYnFhDRIrkdLlgT6tJMAMqwh4iF6uDA 4BeZkS5YNjBoGllJ9AC6Q/LMPqRDhjqvo/qeI55DBzbTtA/0jogGFTGu+8D6DMZVx8Qx TD4ZL5IiMz8DtHwKD484dKNahznNo1d5kyfYkCUgCrJf+2nqMmKJhWyuy/aSpGTk9Ade E6ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125842; x=1721730642; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DutJfFYyPW6LbOov2zw2hBuFnpsIDvuTXHPgZwrrhHw=; b=Ve7lVdh4Z5S2KvMo3jnapK/CDa0h67thRkgkXYglsX6Y3eoXNkzNtMGilXRjKkVW7p AjyftiDcExNCBCfqogUtOOU0qtzHEEFfCgVB4C4v0c3IYKkcXADVtdufa4M/mC0UNKax TQHsKx559J2I/zwL3wO+yFWtWNGzsYKNDiHJuDiB4ImNF+QJtqtl2uHD1BbFaXiEZrGV XrC+y88tPhcoVfG2sXx7UUg99vqJcJp5C1BFiMJFXiUHzylQrWPzmYM6MPQqFQXqAaTE /aWCua2WFLtpMnlZx/oJ3AKQVUiJERXYPRJpX3y4Kg0v3IKONCjQnck1/ufdnB3OIt65 nYgA== X-Forwarded-Encrypted: i=1; AJvYcCWpY0/FbN+lYJlviDw1c4SbqGL+++kwn8mWGwvHFh+ftJbZVj+YjYZEcasph/1/qzpqn0RaxAS5B9dgWxbHrxS/Wpebflpm1WHqyKorUARZsJPKhRY= X-Gm-Message-State: AOJu0Yzj0Noqp1YxyqL/f6FTNclgUIa7x8TBOZlNj+uSW0mjehfKpoU5 qOLSQfVfOhqF6XMi/vrK+pWYuHr/vjKMafxH9NAToZqL3A7d20aV8A92LK8xi30= X-Google-Smtp-Source: AGHT+IFU3cDQXFUWCvhj2jbJm95VoDDyWAcY2PCPxU3FwC7xwW2+LqlxWB/VeBVZJ81bc0MyLsa17w== X-Received: by 2002:a5d:6487:0:b0:367:91d8:a1d2 with SMTP id ffacd0b85a97d-3682614a8a8mr1354950f8f.30.1721125842490; Tue, 16 Jul 2024 03:30:42 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 04/11] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Tue, 16 Jul 2024 13:30:18 +0300 Message-Id: <20240716103025.1198495-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033044_618195_DA9C313F X-CRM114-Status: GOOD ( 15.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley --- Changes in v2: - updated patch description and title - included reference to rtc.yaml - updated compatible list with a generic compatible as explained in patch description; with this the node in examples section has also been updated - used items to describe interrupts, interrupt-names, clock, clock-names - updated title section .../bindings/rtc/renesas,rz-rtca3.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..21f104b1e86b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC counter clock + + clock-names: + items: + - const: counter + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&vbattclk>; + clock-names = "counter"; + }; From patchwork Tue Jul 16 10:30:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00997C3DA49 for ; Tue, 16 Jul 2024 10:33:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0HOKcV/Z2YZ7f+EBCnNFDDOgx9RWroDiEAZsH3IZav4=; b=BS2jcv89lSRJgBEaxAOfqEitk+ SD3clLnu/18PYRWt8p+bp0iqHHpzADa3AnMM7TRdiOm2ELBjgHSq0UiA//N/O0hMJbjGTDhDcCWoP RWo9NiEmOU9Ty9NFRHRiXA464Qp7hsPMn4NSs++mbuSpq51f16ODQv3cD/MC7MVdLrtzVm9F++53a KdHQaXrhtniqo01kMedmhT+hZw4AiqPnzGjC7pXJpaC8VHCgcBE2e5R5q3AozlwKcw8pQNiZulIZl J56Rg9TliUFDo9UB1vq/V691qDnsLM/Pu3zoX3tvROq2HPoCqV9PuMg2AYRggrh6XhMdyU7mwhDDM TbjNVIFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfUI-0000000A3MV-0Nnm; Tue, 16 Jul 2024 10:32:50 +0000 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSI-0000000A2Sn-1Ubj for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:50 +0000 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-52e9f788e7bso6344640e87.0 for ; Tue, 16 Jul 2024 03:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125844; x=1721730644; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0HOKcV/Z2YZ7f+EBCnNFDDOgx9RWroDiEAZsH3IZav4=; b=DmlVsam2uW4UoKwmodh0MhW9HjzeRUiCN9qNJHucYItKupkeQzCcbH/+DfS52oz+Iu eYMSdeA7OPhtbsfB29xXWoiTI9INB38yYxj3KzadVESuyFoMs0ofvVCSBuSRD5mSnjfr EU8TAKGxggyyoLQTkgvVXqfNFGxO2X3BCUuxZg+D/O0LQLHqd573Ud/3x9mo33JYWQSi vNNJT/WAiLsxDYFI4MbHxkD66KWA+kYeNWsmt2j2ABFhVyeWRCTa7f0xfYQUT3mMgQ+S 4YHEnhqfgRBecq3mwj4aON7tp2PAuH8mxziVaVOD6GQsjW02zCG78jsin9CoolbgcSux 6b2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125844; x=1721730644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0HOKcV/Z2YZ7f+EBCnNFDDOgx9RWroDiEAZsH3IZav4=; b=VuY6dpaR4SzT/5NHrELpSlpf5n37hxugTSoLPHT6CMPPCZlmiRsIERZjbJegxEZO0l tqisemyrw0I/YvgczNuhlqy0Hb0VD52AUrEeMmTJt4acfGp6q3md79v4CRBPdbXk2aE2 jz47TX96g+LMGy9y6r7mkoEhLjrZJZlfAKDZAKH41eCbwEr/ag/uXfGAoBqQ3eRVru8h nmjC6ZxQ9JCL33RrGrGmHrH7WsPaTyTNjEHDSlosIaBdggXuiNbT0xpXj2bpEwhgi2HI W/31Uka+N/5NQXWfYkB0xw/OdhKQ5chm+/OYR2B5McnfgTISW02e7XjsANY8L7EZAjIJ wIuw== X-Forwarded-Encrypted: i=1; AJvYcCXtZI5aXqPkU8QtqfkA1dg70EcTxzzzd5/pWAquaAU7DHEGuxLaD76YTl2GazVhUNPQZbd0LIf8uMF4+Sh6FtVRtGI3x10ITOwRDH9GA3fM30D/hrY= X-Gm-Message-State: AOJu0YyRUjh8w1TXIHuR29X/eNv7slMuX5RmKoLm071OAunJ4ETTzHIS +Hc0LB3CF3fEe5Q+OMJpZd3bRwj0i0WrhoWKTWLnELG93u7owsjz19bFFf6MmmfN4s+TCDsDcVH S X-Google-Smtp-Source: AGHT+IG9p9/JtC69MxtsVTEzr3oD5qW1EPa+bGHXVUfje/Ash2rk1UQbdfAT20r/bDPhi06R0zci1Q== X-Received: by 2002:a05:6512:2342:b0:52c:90aa:444c with SMTP id 2adb3069b0e04-52edf0182d9mr1180175e87.28.1721125844138; Tue, 16 Jul 2024 03:30:44 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 05/11] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Tue, 16 Jul 2024 13:30:19 +0300 Message-Id: <20240716103025.1198495-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033046_457963_0364D2E0 X-CRM114-Status: GOOD ( 32.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea --- Changes in v2: - used cleanup.h helpers for locking - updated the MAINTAINERS entry with the new name for RTCA-3 documentation file and a new title (from "RENESAS RZ/G3S RTC DRIVER" to "RENESAS RTCA-3 RTC DRIVER") - used 24 hours mode - changed startup sequence (rtca3_initial_setup()) to avoid stopping the RTC if it's already configured - updated the RTC range to 2000-2099 - updated the compatible with the generic one (renesas,rz-rtca3) in the idea the driver will be also used by the RZ/V2H w/o the necessity to add a new compatible MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 853 ++++++++++++++++++++++++++++++++ 4 files changed, 872 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 3c9cc609cdfd..067f080a4d30 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19419,6 +19419,14 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RENESAS RZ/N1 A5PSW SWITCH DRIVER M: Clément Léger L: linux-renesas-soc@vger.kernel.org diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..3b29b35e48e0 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1978,6 +1978,16 @@ config RTC_DRV_MA35D1 This driver can also be built as a module, if so, the module will be called "rtc-ma35d1". +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..52844f13b247 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -157,6 +157,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644 index 000000000000..c25971ff847e --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE = 0, + RTCA3_ALRM_SSTEP_IRQ = 1, + RTCA3_ALRM_SSTEP_INIT = 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @clk: RTC clock + * @rtc_dev: RTC device + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct clk *clk; + struct rtc_device *rtc_dev; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) +{ + u8 tmp; + + tmp = readb(priv->base + off); + tmp &= ~mask; + tmp |= (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 pending; + + guard(spinlock)(&priv->lock); + + pending = rtca3_alarm_handler_helper(priv); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 val, pending; + + guard(spinlock)(&priv->lock); + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset = cnt ? 0 : 0xe; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (u8 i = 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + u8 trials = 0; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EINVAL; + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec = readb(priv->base + RTCA3_RSECCNT); + min = readb(priv->base + RTCA3_RMINCNT); + hour = readb(priv->base + RTCA3_RHRCNT); + wday = readb(priv->base + RTCA3_RWKCNT); + mday = readb(priv->base + RTCA3_RDAYCNT); + month = readb(priv->base + RTCA3_RMONCNT); + year = readw(priv->base + RTCA3_RYRCNT); + + tmp = readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >= 5) + return -ETIMEDOUT; + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year = FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + return 0; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 rcr2, tmp; + int ret; + + guard(spinlock_irqsave)(&priv->lock); + + /* Stop the RTC. */ + rcr2 = readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable_helper(struct rtca3_priv *priv, + unsigned int enabled) +{ + u8 tmp, mask; + + if (enabled) { + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_AF, 0); + mask = RTCA3_RCR1_AIE; + } else { + mask = 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_AIE, mask); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & RTCA3_RCR1_AIE) == mask), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + guard(spinlock_irqsave)(&priv->lock); + + return rtca3_alarm_irq_enable_helper(priv, enabled); +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm = &wkalrm->time; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + sec = readb(priv->base + RTCA3_RSECAR); + min = readb(priv->base + RTCA3_RMINAR); + hour = readb(priv->base + RTCA3_RHRAR); + wday = readb(priv->base + RTCA3_RWKAR); + mday = readb(priv->base + RTCA3_RDAYAR); + month = readb(priv->base + RTCA3_RMONAR); + year = readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year = FIELD_GET(RTCA3_RYRAR_YR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + struct rtc_time *tm = &wkalrm->time; + u8 rcr1, tmp; + int ret; + + scoped_guard(spinlock_irqsave, &priv->lock) { + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EPERM; + + /* Disable AIE to prevent false interrupts. */ + rcr1 = readb(priv->base + RTCA3_RCR1); + rcr1 &= ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |= RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + } + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, + msecs_to_jiffies(500)); + if (ret <= 0) { + ret = -ETIMEDOUT; + goto setup_failed; + } + + guard(spinlock_irqsave)(&priv->lock); + + ret = rtca3_alarm_irq_enable_helper(priv, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + + return ret; + +setup_failed: + scoped_guard(spinlock_irqsave, &priv->lock) { + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 val, radj, cycles; + u32 ppb_per_cycle; + + scoped_guard(spinlock_irqsave, &priv->lock) { + radj = readb(priv->base + RTCA3_RADJ); + val = readb(priv->base + RTCA3_RCR2); + } + + cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset = 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle = priv->ppb.ten_sec; + else + ppb_per_cycle = priv->ppb.sixty_sec; + + *offset = cycles * ppb_per_cycle; + val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val == RTCA3_RADJ_PMADJ_SUB) + *offset = -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && + cycles60 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles60; + adjp = 0; + } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && + cycles10 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles10; + adjp = RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + guard(spinlock_irqsave)(&priv->lock); + + tmp = readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) != adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) == adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + } + + writeb(radj, priv->base + RTCA3_RADJ); + return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static const struct rtc_class_ops rtca3_ops = { + .read_time = rtca3_read_time, + .set_time = rtca3_set_time, + .read_alarm = rtca3_read_alarm, + .set_alarm = rtca3_set_alarm, + .alarm_irq_enable = rtca3_alarm_irq_enable, + .set_offset = rtca3_set_offset, + .read_offset = rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate = clk_get_rate(priv->clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); + priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting procedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable alarm and carry interrupts. */ + mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE; + rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0); + ret = readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val = readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. */ + if ((val & mask) == mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask = RTCA3_RCR2_HR24; + val = RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask = RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is operating + * (RCR2.START bit = 1) to be able to read the counters after a return from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ + val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) +{ + struct device *dev = &pdev->dev; + int ret, irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq = irq; + + irq = platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq = platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtca3_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + platform_set_drvdata(pdev, priv); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret = rtca3_initial_setup(priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret = rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops = &rtca3_ops; + priv->rtc_dev->max_user_freq = 256; + priv->rtc_dev->range_min = mktime64(2000, 1, 1, 0, 0, 0); + priv->rtc_dev->range_max = mktime64(2099, 12, 31, 23, 59, 59); + + return devm_rtc_register_device(priv->rtc_dev); +} + +static void rtca3_remove(struct platform_device *pdev) +{ + struct rtca3_priv *priv = platform_get_drvdata(pdev); + u8 tmp, mask = RTCA3_RCR1_AIE | RTCA3_RCR1_PIE; + + guard(spinlock_irqsave)(&priv->lock); + + /* Disable alarm, periodic interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & mask), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int __maybe_unused rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev = priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + struct rtc_time tm; + u8 pending; + int ret; + + ret = rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret = rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + if (alarm_time >= now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + guard(spinlock_irqsave)(&priv->lock); + + pending = rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return 0; +} + +static int __maybe_unused rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START = 1 to be able to read the counters after a return from low + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] = { + { .compatible = "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver = { + .driver = { + .name = "rtc-rtca3", + .pm = &rtca3_pm_ops, + .of_match_table = rtca3_of_match, + }, + .probe = rtca3_probe, + .remove_new = rtca3_remove, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Tue Jul 16 10:30:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FB42C3DA59 for ; Tue, 16 Jul 2024 10:32:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Lfsm6nSG5J99n7fBjSEyZBKTrg1AsoRf03PyuQSS78k=; b=o7p4ZAyaexfB9DCbY8XBkEySS6 QMkrJEdpIj7pkTzHVl6j7kLrWxF+d/IHHbAwd36ZAbKKimBEg022DRAafexjeLVjOsLoeYCdxEXY/ j+tDediAjQAoaA1+BvXfcRzDCMGuUNLWE9b1IS5h/FpkYLmkO3neL/wh+qSalRlngVTsVZBS6yqNK cjdwJsZon//OoBKSxcdihxDVGlVUxXpPbK8QEZOwGWPkglOqgzWdBEcw7TCCzT0x9Q4JZlhvYPss+ Ff/w7c4jspTHdPaZbuUhqSvq/kZRJQYooyXuMSX7baesn7LHWRrQQu8+Sadooyvs2tnWkmPdPb2na bHvJSy6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfTz-0000000A3Dg-3MF2; Tue, 16 Jul 2024 10:32:31 +0000 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSJ-0000000A2TN-2j8q for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:49 +0000 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-427b9dcbb09so4800215e9.3 for ; Tue, 16 Jul 2024 03:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125846; x=1721730646; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lfsm6nSG5J99n7fBjSEyZBKTrg1AsoRf03PyuQSS78k=; b=AmffDTTJPbOy0dOIEDe+A1B7N7wEOD+W+0dWTSKxO5BElCyQJ272tiQ7O6+hXnIIKr OmfwDjykikAtd6E+xjaZj2d+Cj7zSiPgX0q8WH6G2vK0tdQwOBlIvAyWVJx23ZsQoU0V I9jshBUBx5Y1gSErOzE0MmhSdkshEM6Rl990wQ+BCadVHnx2nW4Yz8PXBhrHInGi6se9 upTLi9IEBb8jGeApcEc6AkScomWO+SE4oGQp7itE7fhDNL6mjpllmJ6Uxhs1AtXplwKu 1koL2DmJp1Ctp5akZGU6z5oU/JXND80j5w6XXZa6/osr5jI4Fp5g349VLtIzqEgP5F5w Xm4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125846; x=1721730646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lfsm6nSG5J99n7fBjSEyZBKTrg1AsoRf03PyuQSS78k=; b=NQ8XKNmZ3ug7MxrbUE3qMktn7TjcdOIr4UVLCZ5AtwqLjVrnMcD3WJZEVamtQAw+PR K0KtxZWrJIzFlGqYGBM9e6uP5L8Z73IT7WrEooDcaRfBpzJ+gfNKetd3Y47xBFwp5xN8 32b21WkslUkKZtW4Xnlzoxu350FNunmMkO4xf3ocLVaxUOANgKnV+cEkiv/aFIp8IFMz nhtQwyjwLL3Jk2HceZgGKkxTZKy7DyQ39vmOsTTl1eKLT9AVgiaMRpO2M8FKagPqWtFa p23vbLN7kS6fZyZjMQjfwfeB7mF+xZmuSNE0oT2JrGUBydnR1W5tNTIXd33MXV/lR5wZ gmMw== X-Forwarded-Encrypted: i=1; AJvYcCVnWRUhbSOeYNtBimz6SijsUoo1lPyfv8/OkaFlGvtIJ+k4cMirRZuiBey7RxdjAAI40NmfPFj6AO5mvkdPbmlQpmDenqfCfVU68Vfwlj8qeFmxfRc= X-Gm-Message-State: AOJu0YyblG3jfDZcpkNX0FrLZeSNLx6jxcIiUj/AJ9mjPAwTD+lur6eW 44+6OvxbOHLnePE/faLxjDduQ8RWL/DZj56F+5QVbkTwJSE8M/5WPLns4YSr1w0= X-Google-Smtp-Source: AGHT+IGdDT8jIaqfwHSd4jCsuylmV/YWlg71WG2lfw6K9e3FV4X+drTEDU0GFqSOCs5IcXpk4rI+eQ== X-Received: by 2002:a05:600c:35c5:b0:426:61af:e1d6 with SMTP id 5b1f17b1804b1-427ba6fa0d1mr12677545e9.29.1721125845829; Tue, 16 Jul 2024 03:30:45 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 06/11] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Tue, 16 Jul 2024 13:30:20 +0300 Message-Id: <20240716103025.1198495-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033047_755109_5E2A0457 X-CRM114-Status: GOOD ( 11.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Signed-off-by: Claudiu Beznea --- Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0d5c47a65e46..78b4e088a3a5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,30 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: vbattb@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + ranges = <0 0 0 0x1005c000 0 0x1000>; + interrupts = ; + interrupt-names = "tampdi"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names = "bclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + vbattclk: clock-controller@1c { + compatible = "renesas,r9a08g045-vbattb-clk"; + reg = <0 0x1c 0 0x10>; + clocks = <&vbattb_xtal>; + clock-names = "xin"; + #clock-cells = <0>; + status = "disabled"; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -299,4 +323,11 @@ timer { interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Tue Jul 16 10:30:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F222EC3DA59 for ; Tue, 16 Jul 2024 10:33:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=havjViSFqkpX2ZEw/deHEcNpYtCxaTiY0eUvmPFnuY4=; b=Ao36a4Z3T5XnUFOLZicNRCxO/F xO8YjRlJmD1LSxNVXmFrgWYpODkHzt+5I9bLc9qTGWZX0Uu3XklP8g/j5MD2UR12BX4xfe0NWpcOQ 30+8nnJPHkV62mknjBfM8eqMtwTO/2XpC0DngzdNCTFXbQzLfYoTD2vCKNSBZAPhMi/Kz6yiotBLO nbm9rayAjLxsyUiIdeh2p0YJpZoE2G3i5orrE1eSFBxNH/IcOcuCzDlToau2ud8uL8hxiexQcEukI t5NEJPtCBbuZ1Mzw7B8LtWM4AKopLIPVyZDBtJQqfTY6y50YXSbW5DD4Nby1qZdGjnpBMvys+AZhv bPTCn2Gg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfUa-0000000A3Tl-2bFF; Tue, 16 Jul 2024 10:33:08 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSK-0000000A2U9-4BcV for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:52 +0000 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3678aa359b7so3844258f8f.1 for ; Tue, 16 Jul 2024 03:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125847; x=1721730647; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=havjViSFqkpX2ZEw/deHEcNpYtCxaTiY0eUvmPFnuY4=; b=JEuBI+rBMm9GA16lwCA9h9rvUjfobRNB9bMSTwIopZXBXBCOBIHDDQYjJZYQR1zr50 /x0F0+6eN7k1Cm+9Kq1R952vVFMkf2OBYSwkE7ppdhMEIc1sSE8g8sz4Hg56xM+x9Jrx UAD6QBWqVkT0NmCPiGgHGjq6s9hBGlZSyN8CTFZJtJW1Co5gcV95O27MWFMrX7B+9LsI x9enmu5L6acbp3tcBXDFjW2r44z4OJLKFnfx2jmSv0d0p0kZp9VUG/GSB4xYgUjn5XjO fjtkX4rxCj3P9boIb6m/VRds/mByEIxMHpqHcrJgaOIFuBJGyapNrIMkt0/qGb+Oay5y 428g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125847; x=1721730647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=havjViSFqkpX2ZEw/deHEcNpYtCxaTiY0eUvmPFnuY4=; b=YKPR5OF1eG9eQoYXwpy4fpSbo4ljNKXuuD1i43GlAoyZYlXElnxoAWPnZrkBoL5aCX 7BVHhChesQqQ9I9ZFdTLRHhqmNqX+h6yjvtjrZmb9H4gtqNBKCCyxyc5SLeyMNZ8CDmm 8I7d5THKsqKdaT/QQ+tDj9nWitm2jNpW4f75DzSt4CmwPlFC5l8HPVNNqfB2mAhAwlyS Kq6RqrktQ79Q5dr3AdqJOS5o5oxQqdswC4+RNZp05ppYhx+s+ENx5ESl5WbonNMDWtIr V7+VI3gp217AA6beraTdlAVH3JL1Mzm6Zuq+J1ycme/tgjh5WSxnJ1ZM2vaYuu/gexMX uCrQ== X-Forwarded-Encrypted: i=1; AJvYcCWMylMMAmkdxryRztQVaqre/dt3wXxPZzjwjO3R6RYJSClFLpusw0y/BMNw2bs2Qcta7z5Qve1S5xEoHfrHpMkLUfz8CL93HIOBayva5BvIj1xuy/I= X-Gm-Message-State: AOJu0Yxr1S4L6uVBNezJwbFWOd48uO+rrfvAy5CCw9g7s7WiMDK8OIJy 88HsICAcSsFR8oEuf5XU1H5kOXofFhVJ+A4DxpKVbhIma2GKSFbVAZEhMQZhU7k= X-Google-Smtp-Source: AGHT+IG5nj05P3SaIbAeAjYYqU7ltlxGNASeUqz3/IbArKcpEVPxuAGunWSshG97PaegXbchwypLPA== X-Received: by 2002:a5d:6d0f:0:b0:362:ff95:5697 with SMTP id ffacd0b85a97d-36827591cafmr1044592f8f.28.1721125847401; Tue, 16 Jul 2024 03:30:47 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 07/11] arm64: dts: renesas: r9a08g045: Add RTC node Date: Tue, 16 Jul 2024 13:30:21 +0300 Message-Id: <20240716103025.1198495-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033049_534791_B63B8DD3 X-CRM114-Status: UNSURE ( 9.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v2: - updated compatibles arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 78b4e088a3a5..22008407848c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&vbattclk>; + clock-names = "counter"; + status = "disabled"; + }; + vbattb: vbattb@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From patchwork Tue Jul 16 10:30:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F6A1C3DA59 for ; Tue, 16 Jul 2024 10:33:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SgEFJU9TqEeEi7v4UfFzMf6SUYm8BDlnIzCjSGdepnE=; b=CJ2poXPZnTzQsyCdd2RwQ6enzz ot487k9xh6eNCsTP58t2v/xESk62s7xphO5C6ZFmJ3LDmKwOQtflmiQZZqct79LSDJGLPGwxZwYm2 fA+9XM6pV4IRYfpLvPtT4vgoXRm7m494h5ReFkvKUSLJ/WVARYHTiKwo6M/s/T04l4iuRRi2HitE7 zhWI/HEeGDahnwTq88YXBElRdc0V+32b+TUSKrM6kD1KDk35OKy6nUIjszMybHa2RSOIRl5aQqWqo Ka45hctGigKniOmHftGy5ZAgIQemTzc6FQ1iuKizZfQ7MmnraisnqSivETxGxH+Oz+hVPjCbZDO0T GhTmn8dQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfUs-0000000A3bH-23rV; Tue, 16 Jul 2024 10:33:26 +0000 Received: from mail-lj1-x235.google.com ([2a00:1450:4864:20::235]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSM-0000000A2VJ-3Jw0 for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:52 +0000 Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2ee91d9cb71so54860201fa.0 for ; Tue, 16 Jul 2024 03:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125849; x=1721730649; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SgEFJU9TqEeEi7v4UfFzMf6SUYm8BDlnIzCjSGdepnE=; b=o1q7qg+lRNb8yMhGP/JB6FWjuvE6rz9MOsUiW9mtyJueqh5kJZ9nBM97EmBoLX0wmi bundtaGY+DXDAkN35b3zRQqmACL0Lra1uDzvimi1WqK+eKgoc5vR0mYsyhdm+7oQK6yE Amwcf3Fg0mb6VoVb7tCeDJ5YhAM1MSLUh10IY5NFsEYBgVq/HTe+57iYg25iqs3oJj+M v3/qmzs74nXCyhvmSKBt/FfMYT7Yrefv0O0E8m2znrMCiiUGAPj6zwoX/Vzg1XIFq4De 33+oaatZOw03202eZo/UJ7aG6HA1a9jGV0ySE53QIXKCFf//7R8zeqhb1+PjKNtKlEh4 ToAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125849; x=1721730649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SgEFJU9TqEeEi7v4UfFzMf6SUYm8BDlnIzCjSGdepnE=; b=g8KtwW+YpXVavmZany34dBuSwjPvY056daIuvX7b0FrO0uvypJArCyymq8paeaECv2 TwJgau1YBOUqmgvswc/maPEGz7pKnlxYV/sf0BVl7L6HLhjCHZnTJn0I/AI/D53vgIat mNm98ulwT1Zi00kbZiyxj0iS6uhATL3iYIRzeUAbaqiUctL7yWRENBOs9dYYWdKjIN1u RGrTTiTJvWwijIC0zcIf9Sz3byvK6e7zonXHotJcSiInBMpjacyESkAEbZQiCbvjbQPP Pt8E/7ELOT1Z6l0M3PTYQNsxGjVzLkmKZ3aCIZNeFeTxextZZLuxjglx/MzBAzaqI7oL AOVw== X-Forwarded-Encrypted: i=1; AJvYcCWxlBLAT1z32ghfC5shwCxoDfMsCzPZl8eY6GQfL6OUQ/pdFypEGfn7Rcfz91nlNG7DDZhvO16UzLTCpQvrTDy4Oku6dQ8FqLGrvKfHwJWc8auYDH0= X-Gm-Message-State: AOJu0Yw5m6EvW0ZutljJqrihAx5mab9auNm7Q6zhCGmI1xMiGFDCQR64 f/r0seJBGEhkPQRl5N27HCl5WFracBuHl7T1jJXIxYPbFh+Sl/XnMj2MoejYkkI= X-Google-Smtp-Source: AGHT+IE4UrP8ocZy8DYCRi6ljSVc7gUaTDEwV0MlfP0Wt1LcKXTzKRIXgiUNL8wbFViSdsnBD2NBxA== X-Received: by 2002:a2e:9ed9:0:b0:2ec:5699:5e6 with SMTP id 38308e7fff4ca-2eef4190aedmr11234431fa.26.1721125848934; Tue, 16 Jul 2024 03:30:48 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:48 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 08/11] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB clock Date: Tue, 16 Jul 2024 13:30:22 +0300 Message-Id: <20240716103025.1198495-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033050_996687_57996EFC X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable the VBATTB clock controller. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 8a3d302f1535..517ce275916a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -341,6 +341,19 @@ mux { }; }; +&vbattb_xtal { + clock-frequency = <32768>; +}; + +&vbattb { + status = "okay"; +}; + +&vbattclk { + renesas,vbattb-load-nanofarads = <12500>; + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Tue Jul 16 10:30:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77585C41513 for ; Tue, 16 Jul 2024 10:33:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/G5+44h167VOsiaOPrdd9U616TrltprIHsWsocA1F5A=; b=oEUNeOTVo5gWTAW4k52mvIoSPn k8fS4PpXCv8T5du/+ah+krlHzREzQHYgJkBlQA6HSAVOUiqmSOj+e4Etk3dLh/Sug3COpW9fY/E4p FXJY4UAjA+9aghPyvfkcWj6wXDQJTkYP+Pnxr/SZBcrPQC2RQEYQoVxOQSeNZ1Y1us+KSELOWU2Pi wEeigpR5eRTJhdBr9o3FeTwBq+OE6v26Y1C3HkQO6t54E0IKiulQ0nZYBwnP1Q9g5xQneYBvJVbY8 amVHFvE6hn4Rhs2rQ24h7p0lQCd+5F2+tvAP9PGqXpIbUU26v4eB5TZJynHf5VaHe5Yj5OXNaxHSx 8hX2XCzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfVA-0000000A3ki-3t0x; Tue, 16 Jul 2024 10:33:44 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSN-0000000A2Vx-3umo for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:53 +0000 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-42793fc0a6dso35911575e9.0 for ; Tue, 16 Jul 2024 03:30:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125850; x=1721730650; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/G5+44h167VOsiaOPrdd9U616TrltprIHsWsocA1F5A=; b=OxREFr1CIIwuOe9mYPGpdWfaA5vhIF4A5+xmLOah8zRGoUohRHTlVJAuD+20e9+N4n mXWaEFJ2X+6i3AMFrxvWDVqzlFCE0DVk14ddEX2AUuUXg+CdaABp3FFPDaLry4sc97ic gjvo1k/k+Epuy4HRa5EfoLZ49VlJva4cthWPlWtvVuh6ZfWAbO+/HM5iPsj+UDOTPATv Oqx9XKFBphz6mHIczBLjS93z1yOanq/JDlz6u+3cy/YZn3YGO0mt2dfRl9DYgS2+Y7+q vOvoj3eEKS+2CUp5/RyaWYxfDMRZ5BIktjSEsbvJU4dy3ip3lLy73XgOwng8UVIDoaVy vdSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125850; x=1721730650; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/G5+44h167VOsiaOPrdd9U616TrltprIHsWsocA1F5A=; b=c7qTKgI6wzWGf8nP4vli50HQWgpZToJBJurdwfXZHXcQqr0XntpzHOi2AZjxiYN6XU EN+jfAyzN8MqOl53fjGCkD2ZAZSdv5wgc0A6zcCeUyckgbrT/21ByEPaRUhOQgPPBct7 O/vPuGgLTKsJZ5KoiZIScMhOI1V+v4bD5imUUi5i4HFgksxjEbxZ9EJ8scFygXn92zmb jDcyaos+HIHX8eokfvyxCqdRL07H4KeKpqEu+d6XkLEGnsxgUt/dxj+2vo+oDTmf5con Ob7eCfCXlEd/ATBrnvM7JKAKtJ0NiVPrQRzrGLkwqHIATYSwLxPvm+J9pFXxr932efDm RxJQ== X-Forwarded-Encrypted: i=1; AJvYcCVsoF6kwo97goQXRWRLq+H0XCfHTJOztVi2+IThMxPzT8iXyPfGgZV40uUWc9DAsjVgFKDqiDyzmcUzYOk3qxOfJzem+Pk9fmlyF3Xqv8IYuhlomqM= X-Gm-Message-State: AOJu0Ywr//cOqrtjrfvKOHZVH/aAedK+77vKtP+R+9j1Fc9l/OoL63X5 WtLdoOeW31aMdKj6z3qnabAsOtrsa9BjHFwy3D4USTjWxnB0cnSAgsMvGEb8ALI= X-Google-Smtp-Source: AGHT+IF+j4vpd59rXfwJJpale0+2M2xjNcq85fj7Hc313ckK0UPmDoi685v/0yv7e97UdhOY9yZPEA== X-Received: by 2002:a05:600c:1547:b0:426:6f5f:9da6 with SMTP id 5b1f17b1804b1-427ba697bd1mr9207585e9.27.1721125850521; Tue, 16 Jul 2024 03:30:50 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 09/11] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Tue, 16 Jul 2024 13:30:23 +0300 Message-Id: <20240716103025.1198495-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033052_044702_3F696A8D X-CRM114-Status: UNSURE ( 9.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable RTC. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 517ce275916a..82a80fd8e7ec 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -341,6 +341,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb_xtal { clock-frequency = <32768>; }; From patchwork Tue Jul 16 10:30:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BC1DC3DA49 for ; Tue, 16 Jul 2024 10:34:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1Lc/uNU85i9gb0+79NrAcdA+6hL4Qt2Dc7/pD8w1sdo=; b=z2mW5Hh9SIcBO1+6YUGNMitiDv tdf1C9CLtx0ecCKX5fqh19tkpRrxPYjyGDJDGxALzG2ZboYkGyzSAGWU2HBmRpsJ1dNMheQLlF2PI HjP6bglEHf93R6kjBY3f1gT+HO9GpeCAjUtOKt79UnHFfxykXffCLESkLuYMizJt+Oe8EKhWeGQdD QYRiR1DjF/kTy8peTC50EJ48iuaewyYRVA+dE/tWAHMRCHieHTjEq348+D0KA5DMIsa4n0E1rrUZN DF8/Guhtphiyp6+WCK0YNxAXpDwomG9xU4KsFtxzNfwZlw9+LZGAXH1/EsEiUaIlSN7EfLmjoEiMW tKcKv8aA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfVT-0000000A3uP-1OPF; Tue, 16 Jul 2024 10:34:03 +0000 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSQ-0000000A2Wo-25tR for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:55 +0000 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2eeb2d60efbso64901341fa.1 for ; Tue, 16 Jul 2024 03:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125852; x=1721730652; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Lc/uNU85i9gb0+79NrAcdA+6hL4Qt2Dc7/pD8w1sdo=; b=NoWMUz7rIByJezuHpoZhLZLvnUywtLt8y3gyE7tky1ms+M99RLP2hIaeueylExFRtA UCqRJnKraaANiOfm/RaPm7nVTatX/aymA4/YdVNDlwQ5V/YN0JpWvYtksds16aW1qNFF I4gma0THtDMT5SUyFRCt+qQ/4AydU1zJmHbgXWaDs+5FYiPBXjeBMkzhQW7ZJu/+78mm 4xKIJ+PtJITEOywDgvBfSWACQjB7LYP0kchT/TN0zJuUrOENis0eghyuZJTJVnLBUK9T K7VCnewuqWM7A2q3mgp7ps1ZVlPj7mY+zFFdDotKo6G7/snIkvHZvmGaJWs/DGwvaa8Z eUtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125852; x=1721730652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Lc/uNU85i9gb0+79NrAcdA+6hL4Qt2Dc7/pD8w1sdo=; b=XNi16rTOLHJPdf12/SdgsfsZdVW/1yeENC25t8JQbPEoXM5U10Wpcb/NPZJugslv02 n+OaWiRlHMqXdQ6Imy9FGOugNFv9IU+4idobRnJJyMXxKtBrwIOsbZYrTRaTediDLEtX ohKAKY3t4HlB/nJQgZ5+L2Xhwg+UuJymp0HDLofGZSd+QtHs6JX0OSKUnFt1ie115BFd 319njINKKXGNqzBEgw8cgnrRVYyT5T9QeIWLKdofZhXDuON09b2KeHO9FkUGiuHp58T9 diry3Ub8oGtHanp1AT65jkogPIEQOiUQ4rA9ZeysakiIPNSOrvtXxJBQvroJ0FMe4ohZ EGfQ== X-Forwarded-Encrypted: i=1; AJvYcCWPY9+wLNcuIrd8QJyXmOPDUXo0aQTzSCfvryNaNyDknzv3gBpvXdDtzb+NfJE9RtabLc6iUwK30iHjZZPchIvCfvOg+5vKpTNfLfMHXdaDhnqcOaA= X-Gm-Message-State: AOJu0YywVz7LcQ2ktPxfiSUdeGY787YNhZc7kq9dkYHKuGOPWhFUldFf nov8kewAXU5RUahWX4nwDiP6VozPZhbzAOKbPEi/gEBvij78K0hmEkGtVCUaHbQ= X-Google-Smtp-Source: AGHT+IF1Lb+nVjAsf8fHP0AS1wIPQKQn9s1ZCjD3vT5CusZmhAU+Uik6JLX9tgQRYjTy6nqzNxi6bQ== X-Received: by 2002:a2e:9981:0:b0:2ec:f68:51de with SMTP id 38308e7fff4ca-2eef41e29femr10746011fa.47.1721125852148; Tue, 16 Jul 2024 03:30:52 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 10/11] arm64: defconfig: Enable VBATTB Date: Tue, 16 Jul 2024 13:30:24 +0300 Message-Id: <20240716103025.1198495-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033054_598598_66BC13E4 X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable VBATTB MFD and clock driver flags. Signed-off-by: Claudiu Beznea --- Changes in v2: - added CONFIG_MFD_RENESAS_VBATTB - added vendor name in the VBATTB clock flag arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c9fcf9ad395..f35fd006bbbc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -750,6 +750,7 @@ CONFIG_MFD_MAX77620=y CONFIG_MFD_MT6360=y CONFIG_MFD_MT6397=y CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_RENESAS_VBATTB=y CONFIG_MFD_RK8XX_I2C=y CONFIG_MFD_RK8XX_SPI=y CONFIG_MFD_SEC_CORE=y @@ -1358,6 +1359,7 @@ CONFIG_SM_VIDEOCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_RENESAS_VBATTB=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_TEGRA186_TIMER=y From patchwork Tue Jul 16 10:30:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13734300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92FF6C3DA49 for ; Tue, 16 Jul 2024 10:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DAXdKc5Z+02xSdGxMpcMXF7UJmX+WtkbTbyJ/hK50W0=; b=RMqFWFhzUNlvvr5tedvuO3xCAh cg+jam2zbETTrQrMWl8+8+9w2zQoWYfpUeIkW7s3pHfj8wxVqEbuz5Bh0gu7R7tZpoIQcAVn4MOIC TgDzu6/maJvlaZNODNrcRMt1GIjkPrEuMvkOswBsDL5P8e7Ki+WzuYYn6HJtD5JchhqJc2msUvlMR DzvaPrZpv4nDZPYDWh40KO6AEQQ5xHY2CgW6ojWEC+i309XUbpkAaJxX4/nVRcetbnaz/wU4kkwQ0 dGawPUqjy62F5ypN8lJXtAiBUrE9Ho5MipTUkVPvOGfw8X7DjI37694H56nIcf2ZlA/qmXkJCNCQT u6wCKLLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfVl-0000000A3zR-1htd; Tue, 16 Jul 2024 10:34:21 +0000 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTfSR-0000000A2Xd-3KUN for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 10:30:57 +0000 Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-52eafa1717bso5488162e87.2 for ; Tue, 16 Jul 2024 03:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125854; x=1721730654; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DAXdKc5Z+02xSdGxMpcMXF7UJmX+WtkbTbyJ/hK50W0=; b=SuX/x97/FGBX3sXn7/YHGsagz3v8Cu/ARmmE3qWq7DjJiQIdv8h4JRUs0qhGuznOWt C5e6NvTdcrMavtovQXKrOg2dAhXW/KaEaw2bCCzFHt31Ol1WLsoUsD0c8iiORr8SMenO cGgaqq1BvHSfrDO158WSSIiotmLuc9pJKJRPPnNj7m7v3DojAz/QSqUUHTGaQ4V71JrG Yqirplmc3gJkrxjrgNucg5kMlmk/GiNXbnzQMcMxioBEy0itmZhCqmDOL0XjEwMu68ot +JKPxNlfQqbrZNTUrNf1JX0Nxqs3QDqTOc6OjNtB6UbZbCMl5XTyuMWuIi3rSL9DKzjD 7/fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125854; x=1721730654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DAXdKc5Z+02xSdGxMpcMXF7UJmX+WtkbTbyJ/hK50W0=; b=K31dcQ48Nbo00W6SryBNU1oN8XmNd8mgJfWhtv0N21F4bf4nEPzYOVYSPnbLZCKzya 87ktxISxK9fASslhQnHZWuR7HX3Rf726ZOMCH5j5wYaqE83/9YWkLwm6O26WWAL7Z4SW YG4nNCO3aEwGauTsNpkzs3OheGuEATQJSMX2/ZkH3Jro/5UvTc0ohaVShghJEj1LwX23 PFyoDEszHffxEyvlWmcbgxDwpjJ/c4wefPrQnzc67caHPNfaKemZhGak3tGHCvIkkhY8 AHd0H8CS9xB/u70zooHPM6WUnhnI49CrNUoSmU3CXbetKQa8KYKhf10TB3sJOtTUR/Xb BG+w== X-Forwarded-Encrypted: i=1; AJvYcCVL/2dgQY2tLPYHF09mAQxS88vYgNOY8JRAxhfF3efa6Gt7GV8/e/FFj5rpGyTL8Y87Uzmhn4mXhzZHVNP7lf69VL9JDbi5zj+btIWQ31iPOenOYo0= X-Gm-Message-State: AOJu0YwI3piqEPXNLuT1rXEaXOElorGqBXp+sfEwKQsUMza1xnPkxTDJ amjP7jghNkkob3Bv9WDsRtNYP7gi4Ii1fTu4/wUBAbZk8XXT2a/KOzvNubMPDKY= X-Google-Smtp-Source: AGHT+IFbkiHtNVlSjCVJf3cVxZfgoUXWPkU+uRJ0BzsW0f977HEVh4lCus0KUh+9d9jKXgqmMYtbgA== X-Received: by 2002:a05:6512:3c8c:b0:52b:c025:859a with SMTP id 2adb3069b0e04-52edef1cc52mr1084908e87.2.1721125853907; Tue, 16 Jul 2024 03:30:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 11/11] arm64: defconfig: Enable Renesas RTCA-3 flag Date: Tue, 16 Jul 2024 13:30:25 +0300 Message-Id: <20240716103025.1198495-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_033055_863682_3543A8D1 X-CRM114-Status: UNSURE ( 8.51 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable Renesas RTCA-3 flag for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f35fd006bbbc..e90578659447 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1213,6 +1213,7 @@ CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_TI_K3=m +CONFIG_RTC_DRV_RENESAS_RTCA3=y CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m