From patchwork Tue Jul 16 12:50:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13734522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76144C3DA49 for ; Tue, 16 Jul 2024 12:52:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sThds-0002TU-Cs; Tue, 16 Jul 2024 08:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sThdr-0002Oz-4t for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:50:51 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sThdp-0004sv-K8 for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:50:50 -0400 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3d94293f12fso3129854b6e.3 for ; Tue, 16 Jul 2024 05:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721134248; x=1721739048; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YbyfiuQZejtjAK0lLgqdILt7MjxfEZc/Ti/4KzdWWdc=; b=RHO79leX3Azp63E15nDK6xVj6H670ZiJbeZhDnQUAGZJ2i+2GYRlDwqTfrUuYAuq+h F8eqZeClU+zfNLtZG8J1sf0bayyoQ3pRBl/VuxLZH3hO97kUtX6hpsqt7iqpAP8HvXK6 97znEFuajaBrYteHemgGD5NGYl65I4JcYFYDQFiPCc+ksVh3b2yowQTT1pvfeO03Xzw7 YMjKexrirrdZK57MdMdot/5sLWqP8/5pjFihwhE6/dPgGNDbxXkmMQ8TfPrN9t0ZF3Ll ARTgteJl3iTvaRSydEXijImQov4f8EZr51RknOZxoEsOWK35l8c+uXp+mZNooRtd/6EI fkhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721134248; x=1721739048; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YbyfiuQZejtjAK0lLgqdILt7MjxfEZc/Ti/4KzdWWdc=; b=MZuRjopV9yy6+p5AtDAQQgBOyAdpEklAGO7ZI6JYAI6afVn8fGKsyCwb2YZQh6d21k XMsA5WyxdkiM6Ice3t5oIzSyNOk/kcNYPYJPmm50ygf4nbc8ycLT4fcINVmDAfiCtNVv PvA5yNl/duW0PhxoJ66iSshN7s6sukyy1EkbI9916pzs7riTtYwbaIzdo+IsVyJ6Ac7J eBxub/170nYgQ5BUCFGu9YHOedZ47oT6cYJjU+ruqfT4/PJWsvhLMKED9p7YarHEWYsb 4LhPqOLKlflKZ1thtMyeqOzkxoeDjPnXGCXCia+HUAP4QSaLs4ZPu59RvhHoaZKkgJr3 6Otw== X-Forwarded-Encrypted: i=1; AJvYcCV0RTIH3R3IQMFrNDaHwVeq/i+lekCheRT+DpNcsYm0Wff/J1lmOvrSI5fm/00SHDae5xdzN3lE/LXyHonwoVoOTnRzc3A= X-Gm-Message-State: AOJu0YwwcLBE9JwvLreV22CfMfitquO/m+VYQZt4B3gedrE4rmy3Mt8b y3Kfkti0Rv86gn95kPpADaX0HDyUgPucEODHpEvfBGyMSPHqcJsxuLWK1LBPeK4= X-Google-Smtp-Source: AGHT+IGFBBm3xGktf8NTZcTnM8+UpM0LHi+BQkpIUqXaBQ9UZUEQ6ylj8rrem6a9LAOE3XQbO9WocA== X-Received: by 2002:a05:6871:29d:b0:260:3bdb:93a6 with SMTP id 586e51a60fabf-260ba823174mr1786700fac.46.1721134248404; Tue, 16 Jul 2024 05:50:48 -0700 (PDT) Received: from localhost ([157.82.202.230]) by smtp.gmail.com with UTF8SMTPSA id 41be03b00d2f7-78e32b6bbb7sm4683985a12.17.2024.07.16.05.50.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jul 2024 05:50:48 -0700 (PDT) From: Akihiko Odaki Date: Tue, 16 Jul 2024 21:50:30 +0900 Subject: [PATCH v3 1/5] tests/arm-cpu-features: Do not assume PMU availability MIME-Version: 1.0 Message-Id: <20240716-pmu-v3-1-8c7c1858a227@daynix.com> References: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> In-Reply-To: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: none client-ip=2607:f8b0:4864:20::22e; envelope-from=akihiko.odaki@daynix.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Asahi Linux supports KVM but lacks PMU support. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/arm-cpu-features.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 966c65d5c3e4..cfd6f7735354 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -509,6 +509,7 @@ static void test_query_cpu_model_expansion_kvm(const void *data) assert_set_feature(qts, "host", "kvm-no-adjvtime", false); if (g_str_equal(qtest_get_arch(), "aarch64")) { + bool kvm_supports_pmu; bool kvm_supports_steal_time; bool kvm_supports_sve; char max_name[8], name[8]; @@ -537,11 +538,6 @@ static void test_query_cpu_model_expansion_kvm(const void *data) assert_has_feature_enabled(qts, "host", "aarch64"); - /* Enabling and disabling pmu should always work. */ - assert_has_feature_enabled(qts, "host", "pmu"); - assert_set_feature(qts, "host", "pmu", false); - assert_set_feature(qts, "host", "pmu", true); - /* * Some features would be enabled by default, but they're disabled * because this instance of KVM doesn't support them. Test that the @@ -551,11 +547,18 @@ static void test_query_cpu_model_expansion_kvm(const void *data) assert_has_feature(qts, "host", "sve"); resp = do_query_no_props(qts, "host"); + kvm_supports_pmu = resp_get_feature(resp, "pmu"); kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time"); kvm_supports_sve = resp_get_feature(resp, "sve"); vls = resp_get_sve_vls(resp); qobject_unref(resp); + if (kvm_supports_pmu) { + /* If we have pmu then we should be able to toggle it. */ + assert_set_feature(qts, "host", "pmu", false); + assert_set_feature(qts, "host", "pmu", true); + } + if (kvm_supports_steal_time) { /* If we have steal-time then we should be able to toggle it. */ assert_set_feature(qts, "host", "kvm-steal-time", false); From patchwork Tue Jul 16 12:50:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13734517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E1E6C3DA59 for ; Tue, 16 Jul 2024 12:51:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sThdy-0002io-P5; Tue, 16 Jul 2024 08:50:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sThdv-0002fm-Qh for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:50:55 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sThdu-0004tQ-3F for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:50:55 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1fbc3a9d23bso38729145ad.1 for ; Tue, 16 Jul 2024 05:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721134252; x=1721739052; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JQOKrG52Y2enmmfF+L80VMku0KsDSGPKvaWKbQs8/U8=; b=m2yrH7AToaaQYMk4fmqkPFq51mJZG4TbSXdbUnpVZWxlY5zPP6+YkQDwyaTOnbl6mJ Opdp+BBEuvkHivyh3fDlotFK72DvTwpbxfataVrQQH7K7cNB4A/fOu9lqHAwQGkfpIW2 /Tld4BsOgtPB81djnErmb1Gt9OOqEFQwpFW4hKjcbjTydv+uSH3h8B2VpNvICPmfBQRf eDcIs/2z/EJjlaDy8qFiczbZXhEEDrQLCLI4gjsZc5PdYaaM/MWHN7MreFXj1OQ2/b6h IZcVpYo5edovVSKNo/g0wZc6Hs9xt1ObZ+sIGmEtnruOZBMP8vmeRni+xc5GQ0L99ouL Zs/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721134252; x=1721739052; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JQOKrG52Y2enmmfF+L80VMku0KsDSGPKvaWKbQs8/U8=; b=eFAovTuzR/CFm1/2l375ZkNmi3c14+U/i7NeS+H6PQELM0poGDMwNieCOfz/anw+AU cu0RHejQ1WGlh41R1Cc0OXjcLV2MRl4gbuMIipNhiBLZ+Tq0KMgU26fFL/pDwStfZqD8 QNlyZTMl3qNUgSxkMIyJoW8HHB+wyxrY7gUFc1oNI6tCH1fZaUBh4+gkZOF6TioEO3Jz 8nSFNCWEAEsAMPa3T2XUIfoAFO71zQB5Z04mxIPrDVt+p+e5jOeXIGH9Kdm4YWZP+LLg BXbm7uikyS13Iqv4DfqjMnsWsSekDdzeenxtKTNcdNNAC6duHWexUgcB41YNcVHQeWPc JTqQ== X-Forwarded-Encrypted: i=1; AJvYcCVxNVS+Y6T6xffxjuQdzsLMERoacSYt0DGJDXKmjRxGGoS51tIUl/Dmpx7JU3Wp7JCp/Q3m4W5mdrxf/DepeLbEbeDr1sw= X-Gm-Message-State: AOJu0Yw4fYe6fH2LR1aYW/UFXfGqVGlWSkoIaT4c1ZI0Gk3dU9poTVAE mEOXmOKG00nH8tyH3IEQZa5tSsCrms9pnOybk3jWmfHA66CV5hF+ECKaCOoZQlU= X-Google-Smtp-Source: AGHT+IEMWtqXVNzll+cDTZQ2V/r1p60YjN5JuNoyF806T14A3/IAKFSdJwa9M9vuTjedOixfKkqgIg== X-Received: by 2002:a17:903:1c9:b0:1fb:6794:b47d with SMTP id d9443c01a7336-1fc3cc6a2b5mr19748855ad.52.1721134252576; Tue, 16 Jul 2024 05:50:52 -0700 (PDT) Received: from localhost ([157.82.202.230]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-1fc0bc270f0sm57678555ad.131.2024.07.16.05.50.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jul 2024 05:50:52 -0700 (PDT) From: Akihiko Odaki Date: Tue, 16 Jul 2024 21:50:31 +0900 Subject: [PATCH v3 2/5] target/arm/kvm: Fix PMU feature bit early MIME-Version: 1.0 Message-Id: <20240716-pmu-v3-2-8c7c1858a227@daynix.com> References: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> In-Reply-To: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: none client-ip=2607:f8b0:4864:20::635; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org kvm_arm_get_host_cpu_features() used to add the PMU feature unconditionally, and kvm_arch_init_vcpu() removed it when it is actually not available. Conditionally add the PMU feature in kvm_arm_get_host_cpu_features() to save code. Signed-off-by: Akihiko Odaki --- target/arm/kvm.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 70f79eda33cd..849e2e21b304 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -280,6 +280,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) if (kvm_arm_pmu_supported()) { init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; pmu_supported = true; + features |= 1ULL << ARM_FEATURE_PMU; } if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { @@ -448,7 +449,6 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) features |= 1ULL << ARM_FEATURE_V8; features |= 1ULL << ARM_FEATURE_NEON; features |= 1ULL << ARM_FEATURE_AARCH64; - features |= 1ULL << ARM_FEATURE_PMU; features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; ahcf->features = features; @@ -1888,13 +1888,8 @@ int kvm_arch_init_vcpu(CPUState *cs) if (!arm_feature(env, ARM_FEATURE_AARCH64)) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; } - if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { - cpu->has_pmu = false; - } if (cpu->has_pmu) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; - } else { - env->features &= ~(1ULL << ARM_FEATURE_PMU); } if (cpu_isar_feature(aa64_sve, cpu)) { assert(kvm_arm_sve_supported()); From patchwork Tue Jul 16 12:50:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13734519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A01E2C3DA5E for ; Tue, 16 Jul 2024 12:51:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sThe1-0002pf-Px; Tue, 16 Jul 2024 08:51:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sThdz-0002kA-22 for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:50:59 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sThdx-0004uC-EC for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:50:58 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-76cb5b6b3e4so3355836a12.1 for ; Tue, 16 Jul 2024 05:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721134256; x=1721739056; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VPi5Z5Dqnhv2/CUnyN+zY6OWPqGpJunZ/ZxJTeOyVqc=; b=fmNMP+gcf/eMlha1aZVA31QPnCCrZDZRdDE7TZvV9XFRmrCK8SZjfmwr/p9lWSCN+D aenNoci9yMNsxLkf9b2ByqTrC3BBy0e+E4uaFZVdMmllwdKr2mxvbzTBHyIUt3Mvjt6q p7quNEAGih8qAKILQxPCkwFna4Gt8GUw0UKTK6x53gsAqPSrsr0APUofiA5IJIRbcJXt aNmMZWiKMQfO6vHmjYCdOD3s7oXENy0GHooLcGYPtPwwjnP3DEHOkPMVnMcKxxhJjGkl fVVwr/KpHz++7iorTPOFIOhB6Trpuqvwdps4GmLFuPEP25Gv1jCYS9hoigZfTwUI3CNS J2IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721134256; x=1721739056; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VPi5Z5Dqnhv2/CUnyN+zY6OWPqGpJunZ/ZxJTeOyVqc=; b=YvK4p1/FEw90JUHngAA86fhfgpAiE7PlGThGSxZmkwhHfutPLwGy0ZwM+/PDQ318WX HA6TvRw3yK6wFn73OwZVAF7eWhQb58jV6l1U5y5Crad93fpdeV/r7MANoTWqle8tn7Ok FPLayui3r8X0jf4KaXRNPIzAX472GhbctyU2yOGuL+522ykyahLVpkY/AJDjfrTg31Mv JiOQdJAXoyl6INQ2IrnaqLAo7PriMHe1ChUwJMaZFCT1xl01laY3vYYWvcIR8H+KvQpt BZHajLmg/AED2J2PcDcFLnxxZuxkQpOR03/g48DJhnmKl3eSsblc5iHGIHPdiKJgbJlV Tp8w== X-Forwarded-Encrypted: i=1; AJvYcCUXrg7coFMW78eVQvc58tQtqSuLxm6nJd/b1TUUuQawrAAbAjocBMs+EELuncx83pQp5uOGq8ijGOaMwVXOL8gfEAoeavE= X-Gm-Message-State: AOJu0Ywer35ETwnjh9AMLRcvqEbDBuypkzOeL5I0Oz9l9ycZIv/1FFej rycsF8g8Z37OCc5dcs79tmkYRdleK+6PjP47VXCzbHqv/z9YxznNcwivxNilN9k= X-Google-Smtp-Source: AGHT+IGiq7H1/utXn4jDP5eSrc47l3uUiIjjIuyDBP7855yWUI6xcCAqvptjtIWknKwAKTVj3TUcJA== X-Received: by 2002:a05:6a21:10b:b0:1c0:bf35:ef42 with SMTP id adf61e73a8af0-1c3f11feb77mr1915725637.3.1721134256139; Tue, 16 Jul 2024 05:50:56 -0700 (PDT) Received: from localhost ([157.82.202.230]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-1fc0bba7080sm57618265ad.89.2024.07.16.05.50.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jul 2024 05:50:55 -0700 (PDT) From: Akihiko Odaki Date: Tue, 16 Jul 2024 21:50:32 +0900 Subject: [PATCH v3 3/5] target/arm: Always add pmu property for Armv8 MIME-Version: 1.0 Message-Id: <20240716-pmu-v3-3-8c7c1858a227@daynix.com> References: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> In-Reply-To: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: none client-ip=2607:f8b0:4864:20::534; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org kvm-steal-time and sve properties are added for KVM even if the corresponding features are not available. Always add pmu property for Armv8. Note that the property is added only for Armv8 as QEMU emulates PMUv3, which is part of Armv8. Signed-off-by: Akihiko Odaki --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 14d4eca12740..64038e26b2a9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1744,6 +1744,8 @@ void arm_cpu_post_init(Object *obj) } if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); + object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); @@ -1770,7 +1772,6 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { cpu->has_pmu = true; - object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); } /* From patchwork Tue Jul 16 12:50:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13734520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4551FC3DA59 for ; Tue, 16 Jul 2024 12:52:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sThe6-00039H-Dp; Tue, 16 Jul 2024 08:51:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sThe4-00036p-DQ for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:51:04 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sThe2-0004vz-Ak for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:51:04 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1fb457b53c8so44813145ad.0 for ; Tue, 16 Jul 2024 05:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721134260; x=1721739060; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OjSJhOxndUTwoLpjqK0yxNqbOlPYxQqUKSKd9L15YsQ=; b=oYWGXCHQ6zkEOZJBd51NcS369+pgn1v0HK3zuyu2wIBtfFITVeraZ2Si4DPD/UO+aA 0DxDIyXE3bSyl8qS2po2OueJofOsgCVnrZzmmQURHwiSIarzwL+fK3QtKhAx0eJEMICE kMny+7PRT827Pw0OBqpaVq3QZSndsX8u4koxSGS1B46UmnjcPfOxZFhjcTL12Clj1h9p lmISQ17UUPAkhaKLJd+BLN9yeJrM4rpeGGSgniR1JfiG+grFn0bKukPplQzG63slhnVO CvIlMWe3u69yS6+zyd/zAPzOVxLAjfpUSHAQbHSfUNhl85/wTFy+RDqcZLER3HgnQdBB DYHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721134260; x=1721739060; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OjSJhOxndUTwoLpjqK0yxNqbOlPYxQqUKSKd9L15YsQ=; b=O7iKXZQ3gaJOVIEVYJlnczmlABNx56dR+O9i75fF0Rq3xFl3MyKBP9/32PGyKawI/s B2YSbHd2xnmsd9/OEIcpsA23/i8LDHFnwWwuRxljFv+fiVTJ4tjCy1HV2pVN3A37V5Ly kcNrchDjs83UrX4wunfsYK1jjQ0EM28KesY3kPGwyewNPWdb4HHx6RcmwmYyrcpNGEst HNEMz/M+/SzYJzw2QAqrbH10umQzOeS7MiB4uT8vfAenxEuyOIXexbpSavrfPpAV1UyV dcE3eCvc4UQM/+Lf+jwEYx8kkdqHXrF68xUseeQCXBxirFdQB/CIC3JLT5/Kl4nQBUfK R++A== X-Forwarded-Encrypted: i=1; AJvYcCUUh0gf/wlOMqSDXJy03OBa+RW4ctkNAnxHtcszg4bnG7N6Ue5JLtqMu16Ke9sHYfPHRK7xjXfdkTZQz0DUsUY9T1bDq7c= X-Gm-Message-State: AOJu0YwA2rxDEgR4+bPlXqGMcSkntaN60swLjOUrIVDQFXydAoZi/LcL zpKgXUkyAa34iJr5qCDaM68XYMv4uTnmaU2HYExmYeuGo7EtYSBo3fViTtUaUIV9LaTMCp+/QBo 4 X-Google-Smtp-Source: AGHT+IGgcKegqUs568FNJ+2uzBaWczfapraF6MVhNCtN2VRAYUITEj5Hc21cmEbXS/e5G1SoNrN+kA== X-Received: by 2002:a17:902:d2ce:b0:1fb:67f4:1b72 with SMTP id d9443c01a7336-1fc3d9c526fmr13149915ad.54.1721134259665; Tue, 16 Jul 2024 05:50:59 -0700 (PDT) Received: from localhost ([157.82.202.230]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-1fc0bc273b3sm57465755ad.130.2024.07.16.05.50.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jul 2024 05:50:59 -0700 (PDT) From: Akihiko Odaki Date: Tue, 16 Jul 2024 21:50:33 +0900 Subject: [PATCH v3 4/5] hvf: arm: Do not advance PC when raising an exception MIME-Version: 1.0 Message-Id: <20240716-pmu-v3-4-8c7c1858a227@daynix.com> References: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> In-Reply-To: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: none client-ip=2607:f8b0:4864:20::635; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org hvf did not advance PC when raising an exception for most unhandled system registers, but it mistakenly advanced PC when raising an exception for GICv3 registers. Fixes: a2260983c655 ("hvf: arm: Add support for GICv3") Signed-off-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index ef9bc42738d0..eb090e67a2f8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1278,6 +1278,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ if (!hvf_sysreg_read_cp(cpu, reg, &val)) { hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } break; case SYSREG_DBGBVR0_EL1: From patchwork Tue Jul 16 12:50:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13734518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DF7FC41513 for ; Tue, 16 Jul 2024 12:51:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sThe9-0003Kg-BL; Tue, 16 Jul 2024 08:51:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sThe7-0003Df-M4 for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:51:07 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sThe5-0004wO-G9 for qemu-devel@nongnu.org; Tue, 16 Jul 2024 08:51:07 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1fb4a807708so48533575ad.2 for ; Tue, 16 Jul 2024 05:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721134264; x=1721739064; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WEJblyW6Ds1TMF7KFQ+gDmurIfGkUROkVQ8nHbOWOsc=; b=wIBIlEE6zIuVsLG300I0vs8UpN3cKwfhFvkNTc7E7pu4P1Th5wvButz6VOlyYuQlI7 7xTezJfOFQT7FyAgF7WZeXGJ9p7J3IlerZFLHcVBw9rj0cCo0ZjwUl5mtrQHe2ADnClO 5rJsjUQzEyxMkYUH1JNAN5lo0v0oN2r+HRfHbHR/QiBi0Ttec9Ihry4u7CduJ1F7lIRx 4pnhOpKX4dkkfkXd6ESbJmSk6Y5pCQj8YvpY+1wQ9fNQgvgixK2gjh3+dQhLtiGoLiP7 1ZBbZn4hb14xNuWhvWHgxWMJEMGzh3Jl22WKAOLC0zWr+yG/pSGJX5U51Du0AgBo41jD pl7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721134264; x=1721739064; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WEJblyW6Ds1TMF7KFQ+gDmurIfGkUROkVQ8nHbOWOsc=; b=h5U9/TvbpF+oSL9ijrd5d2HiHqxf3HkR8bMRGOKpMwixPVp68aLW/kJlcwA1IpQN0m y6Ji/+VrOZMVYHOUYFnJuO7TeledF7iV3eW9Qg3/Fe+KX0hrFGs7jOVKjXQCvUBVltvm zExdauMjg0vj1OSmc9fLD7p7a90EyvLfbBZIyCWoqB/XoEWwkLrODc/tI1V4FUIGbR+0 v7ke2pEh+Q5115uni/0cJCwCmTsiNBdISuHN1/xmX5D1htiUu6h2TTCrbN9597qtG3UX BMQHNiu9CiFt1PCRfjdsOJSUb55XVVNcbgomt9cEQO/W+sYEp4QlZ2nrF3oEmbqaewwN Gc2A== X-Forwarded-Encrypted: i=1; AJvYcCUEfSkfr7KceRs2vAq41cIqgUenWXEAscvMWFcKjBhjSCnU6+Whx6Orug02t1fN5vldRXs/z9MuSkQWcXzl+Hjuj9en230= X-Gm-Message-State: AOJu0YzGquljI9NnmUVF5I+jl+OjutPKzqr5hUkokExU2bzAvraYCgPc 5mliOoCGUGbxHDKYI6AuOOKyzoen1VE8rknDMRQBccoOHnNNmruzzsG9V+gt3uDFNQngo0ttYDW P X-Google-Smtp-Source: AGHT+IHLl6OhxYtFa4Hu9G+eXwmzB422zbJLkf8LJk3FIsLRsVJ+05Y25EPMKfYbsu8hkTzkg2XY7A== X-Received: by 2002:a17:902:fc8d:b0:1fc:2c53:80a0 with SMTP id d9443c01a7336-1fc3d93959cmr16756835ad.14.1721134263928; Tue, 16 Jul 2024 05:51:03 -0700 (PDT) Received: from localhost ([157.82.202.230]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-1fc0bc2634fsm57640325ad.127.2024.07.16.05.51.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jul 2024 05:51:03 -0700 (PDT) From: Akihiko Odaki Date: Tue, 16 Jul 2024 21:50:34 +0900 Subject: [PATCH v3 5/5] hvf: arm: Properly disable PMU MIME-Version: 1.0 Message-Id: <20240716-pmu-v3-5-8c7c1858a227@daynix.com> References: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> In-Reply-To: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: none client-ip=2607:f8b0:4864:20::62f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Setting pmu property used to have no effect for hvf so fix it. Signed-off-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 317 ++++++++++++++++++++++++++------------------------- 1 file changed, 163 insertions(+), 154 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index eb090e67a2f8..7c593c2d93de 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1199,57 +1199,23 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) return false; } -static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) +static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt, + uint64_t *val) { ARMCPU *arm_cpu = ARM_CPU(cpu); CPUARMState *env = &arm_cpu->env; - uint64_t val = 0; switch (reg) { case SYSREG_CNTPCT_EL0: - val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / - gt_cntfrq_period_ns(arm_cpu); - break; - case SYSREG_PMCR_EL0: - val = env->cp15.c9_pmcr; - break; - case SYSREG_PMCCNTR_EL0: - pmu_op_start(env); - val = env->cp15.c15_ccnt; - pmu_op_finish(env); - break; - case SYSREG_PMCNTENCLR_EL0: - val = env->cp15.c9_pmcnten; - break; - case SYSREG_PMOVSCLR_EL0: - val = env->cp15.c9_pmovsr; - break; - case SYSREG_PMSELR_EL0: - val = env->cp15.c9_pmselr; - break; - case SYSREG_PMINTENCLR_EL1: - val = env->cp15.c9_pminten; - break; - case SYSREG_PMCCFILTR_EL0: - val = env->cp15.pmccfiltr_el0; - break; - case SYSREG_PMCNTENSET_EL0: - val = env->cp15.c9_pmcnten; - break; - case SYSREG_PMUSERENR_EL0: - val = env->cp15.c9_pmuserenr; - break; - case SYSREG_PMCEID0_EL0: - case SYSREG_PMCEID1_EL0: - /* We can't really count anything yet, declare all events invalid */ - val = 0; - break; + *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + gt_cntfrq_period_ns(arm_cpu); + return 0; case SYSREG_OSLSR_EL1: - val = env->cp15.oslsr_el1; - break; + *val = env->cp15.oslsr_el1; + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ - break; + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1276,11 +1242,11 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ - if (!hvf_sysreg_read_cp(cpu, reg, &val)) { + if (!hvf_sysreg_read_cp(cpu, reg, val)) { hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); return 1; } - break; + return 0; case SYSREG_DBGBVR0_EL1: case SYSREG_DBGBVR1_EL1: case SYSREG_DBGBVR2_EL1: @@ -1297,8 +1263,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGBVR13_EL1: case SYSREG_DBGBVR14_EL1: case SYSREG_DBGBVR15_EL1: - val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGBCR0_EL1: case SYSREG_DBGBCR1_EL1: case SYSREG_DBGBCR2_EL1: @@ -1315,8 +1281,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGBCR13_EL1: case SYSREG_DBGBCR14_EL1: case SYSREG_DBGBCR15_EL1: - val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGWVR0_EL1: case SYSREG_DBGWVR1_EL1: case SYSREG_DBGWVR2_EL1: @@ -1333,8 +1299,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGWVR13_EL1: case SYSREG_DBGWVR14_EL1: case SYSREG_DBGWVR15_EL1: - val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGWCR0_EL1: case SYSREG_DBGWCR1_EL1: case SYSREG_DBGWCR2_EL1: @@ -1351,35 +1317,64 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGWCR13_EL1: case SYSREG_DBGWCR14_EL1: case SYSREG_DBGWCR15_EL1: - val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; - break; - default: - if (is_id_sysreg(reg)) { - /* ID system registers read as RES0 */ - val = 0; - break; + *val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; + return 0; + } + + if (arm_feature(env, ARM_FEATURE_PMU)) { + switch (reg) { + case SYSREG_PMCR_EL0: + *val = env->cp15.c9_pmcr; + return 0; + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + *val = env->cp15.c15_ccnt; + pmu_op_finish(env); + return 0; + case SYSREG_PMCNTENCLR_EL0: + *val = env->cp15.c9_pmcnten; + return 0; + case SYSREG_PMOVSCLR_EL0: + *val = env->cp15.c9_pmovsr; + return 0; + case SYSREG_PMSELR_EL0: + *val = env->cp15.c9_pmselr; + return 0; + case SYSREG_PMINTENCLR_EL1: + *val = env->cp15.c9_pminten; + return 0; + case SYSREG_PMCCFILTR_EL0: + *val = env->cp15.pmccfiltr_el0; + return 0; + case SYSREG_PMCNTENSET_EL0: + *val = env->cp15.c9_pmcnten; + return 0; + case SYSREG_PMUSERENR_EL0: + *val = env->cp15.c9_pmuserenr; + return 0; + case SYSREG_PMCEID0_EL0: + case SYSREG_PMCEID1_EL0: + /* We can't really count anything yet, declare all events invalid */ + *val = 0; + return 0; } - cpu_synchronize_state(cpu); - trace_hvf_unhandled_sysreg_read(env->pc, reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; - } - - trace_hvf_sysreg_read(reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg), - val); - hvf_set_reg(cpu, rt, val); + } - return 0; + if (is_id_sysreg(reg)) { + /* ID system registers read as RES0 */ + *val = 0; + return 0; + } + + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_read(env->pc, reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } static void pmu_update_irq(CPUARMState *env) @@ -1499,69 +1494,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) val); switch (reg) { - case SYSREG_PMCCNTR_EL0: - pmu_op_start(env); - env->cp15.c15_ccnt = val; - pmu_op_finish(env); - break; - case SYSREG_PMCR_EL0: - pmu_op_start(env); - - if (val & PMCRC) { - /* The counter has been reset */ - env->cp15.c15_ccnt = 0; - } - - if (val & PMCRP) { - unsigned int i; - for (i = 0; i < pmu_num_counters(env); i++) { - env->cp15.c14_pmevcntr[i] = 0; - } - } - - env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; - env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); - - pmu_op_finish(env); - break; - case SYSREG_PMUSERENR_EL0: - env->cp15.c9_pmuserenr = val & 0xf; - break; - case SYSREG_PMCNTENSET_EL0: - env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); - break; - case SYSREG_PMCNTENCLR_EL0: - env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); - break; - case SYSREG_PMINTENCLR_EL1: - pmu_op_start(env); - env->cp15.c9_pminten |= val; - pmu_op_finish(env); - break; - case SYSREG_PMOVSCLR_EL0: - pmu_op_start(env); - env->cp15.c9_pmovsr &= ~val; - pmu_op_finish(env); - break; - case SYSREG_PMSWINC_EL0: - pmu_op_start(env); - pmswinc_write(env, val); - pmu_op_finish(env); - break; - case SYSREG_PMSELR_EL0: - env->cp15.c9_pmselr = val & 0x1f; - break; - case SYSREG_PMCCFILTR_EL0: - pmu_op_start(env); - env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; - pmu_op_finish(env); - break; case SYSREG_OSLAR_EL1: env->cp15.oslsr_el1 = val & 1; - break; + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ - break; + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1591,10 +1529,10 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) if (!hvf_sysreg_write_cp(cpu, reg, val)) { hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); } - break; + return 0; case SYSREG_MDSCR_EL1: env->cp15.mdscr_el1 = val; - break; + return 0; case SYSREG_DBGBVR0_EL1: case SYSREG_DBGBVR1_EL1: case SYSREG_DBGBVR2_EL1: @@ -1612,7 +1550,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGBVR14_EL1: case SYSREG_DBGBVR15_EL1: env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; - break; + return 0; case SYSREG_DBGBCR0_EL1: case SYSREG_DBGBCR1_EL1: case SYSREG_DBGBCR2_EL1: @@ -1630,7 +1568,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGBCR14_EL1: case SYSREG_DBGBCR15_EL1: env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; - break; + return 0; case SYSREG_DBGWVR0_EL1: case SYSREG_DBGWVR1_EL1: case SYSREG_DBGWVR2_EL1: @@ -1648,7 +1586,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGWVR14_EL1: case SYSREG_DBGWVR15_EL1: env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; - break; + return 0; case SYSREG_DBGWCR0_EL1: case SYSREG_DBGWCR1_EL1: case SYSREG_DBGWCR2_EL1: @@ -1666,20 +1604,80 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGWCR14_EL1: case SYSREG_DBGWCR15_EL1: env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; - break; - default: - cpu_synchronize_state(cpu); - trace_hvf_unhandled_sysreg_write(env->pc, reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; + return 0; } - return 0; + if (arm_feature(env, ARM_FEATURE_PMU)) { + switch (reg) { + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + env->cp15.c15_ccnt = val; + pmu_op_finish(env); + return 0; + case SYSREG_PMCR_EL0: + pmu_op_start(env); + + if (val & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } + + if (val & PMCRP) { + unsigned int i; + for (i = 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] = 0; + } + } + + env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; + env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); + + pmu_op_finish(env); + return 0; + case SYSREG_PMUSERENR_EL0: + env->cp15.c9_pmuserenr = val & 0xf; + return 0; + case SYSREG_PMCNTENSET_EL0: + env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); + return 0; + case SYSREG_PMCNTENCLR_EL0: + env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); + return 0; + case SYSREG_PMINTENCLR_EL1: + pmu_op_start(env); + env->cp15.c9_pminten |= val; + pmu_op_finish(env); + return 0; + case SYSREG_PMOVSCLR_EL0: + pmu_op_start(env); + env->cp15.c9_pmovsr &= ~val; + pmu_op_finish(env); + return 0; + case SYSREG_PMSWINC_EL0: + pmu_op_start(env); + pmswinc_write(env, val); + pmu_op_finish(env); + return 0; + case SYSREG_PMSELR_EL0: + env->cp15.c9_pmselr = val & 0x1f; + return 0; + case SYSREG_PMCCFILTR_EL0: + pmu_op_start(env); + env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; + pmu_op_finish(env); + return 0; + } + } + + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_write(env->pc, reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } static int hvf_inject_interrupts(CPUState *cpu) @@ -1944,7 +1942,18 @@ int hvf_vcpu_exec(CPUState *cpu) int sysreg_ret = 0; if (isread) { - sysreg_ret = hvf_sysreg_read(cpu, reg, rt); + sysreg_ret = hvf_sysreg_read(cpu, reg, rt, &val); + + if (!sysreg_ret) { + trace_hvf_sysreg_read(reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg), + val); + hvf_set_reg(cpu, rt, val); + } } else { val = hvf_get_reg(cpu, rt); sysreg_ret = hvf_sysreg_write(cpu, reg, val);