From patchwork Tue Jul 16 14:29:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAF11C3DA59 for ; Tue, 16 Jul 2024 14:30:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uQ1b5ZNVV7dyvfB5jDf3fxY+RP+yC49dWe1D0LXWhDY=; b=zl3PCDE/A+V+7UpCzmNPXX/pdk tzHCR/32fyA1ZQ8x7dm7OB5HwX6ZTVizRKzALddBsr4qCuF4YKt9eQ2hdblhgdSlWdXhNKM72cuPp /uvaUgCFem96GtA3/s7KQt5a39TmgpRWr6AJS9+xWWEzdfVXEehGL22+7M1+roFnPExsnwfUxjSAc /mu2dFJnhGO3FVuwinuwC7R1Sn6PO+dD7MmGu5ezosq+4wDHmWMvdD0euPb75IynZ5CI6zECzChsG 8Zee0P5WBUrfK10lQXprLrFv4YZaPPxjNXghQgRub/AVNHN/GhXz7X8mfP2Vt48c5jw/7CGm9HrIc g/ZdRZRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBi-0000000Aid4-2wAB; Tue, 16 Jul 2024 14:29:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBF-0000000AiGK-2uO4 for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AACE1106F; Tue, 16 Jul 2024 07:29:48 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B5D2D3F762; Tue, 16 Jul 2024 07:29:22 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/6] aarch64: Rename labels and prepare for lower EL booting Date: Tue, 16 Jul 2024 15:29:01 +0100 Message-Id: <20240716142906.1502802-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072925_804872_EA4A8536 X-CRM114-Status: UNSURE ( 9.01 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current code can boot from a lower EL than EL3, but the flag 'flag_no_el3' have the meaning of "Don't drop to a lower EL", so rename the flag to flag_keep_el. This is a preparation work to boot on Armv8-R AArch64 which has no EL3. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- v2 changes: - Add Andre R-by --- arch/aarch64/boot.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index da5fa6548b65..7727475925c1 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -92,7 +92,7 @@ reset_no_el3: bl setup_stack mov w0, #1 - ldr x1, =flag_no_el3 + ldr x1, =flag_keep_el str w0, [x1] bl cpu_init_bootwrapper @@ -124,7 +124,7 @@ ASM_FUNC(jump_kernel) bl find_logical_id bl setup_stack // Reset stack pointer - ldr w0, flag_no_el3 + ldr w0, flag_keep_el cmp w0, #0 // Prepare Z flag mov x0, x20 @@ -133,7 +133,7 @@ ASM_FUNC(jump_kernel) mov x3, x23 b.eq 1f - br x19 // No EL3 + br x19 // Keep EL 1: mov x4, #SPSR_KERNEL @@ -151,5 +151,5 @@ ASM_FUNC(jump_kernel) .data .align 3 -flag_no_el3: +flag_keep_el: .long 0 From patchwork Tue Jul 16 14:29:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B851FC3DA59 for ; Tue, 16 Jul 2024 14:31:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=v8rt4fhWn42ohnYeBXL6kztKpuwchh0tV1oAQagJcyM=; b=kZMYngmBrmbtzKWWOc3EDlMJRa 5M1ernxERywv88qeW83r/F4jz07cj0w4uNSzOurYpI4tH2YPbKPKYLHFkHwbKM7ZBjhBIH5d99/Jl 8OUNEPg66kS6H0jMOsq7DEjqgdGp/OoYXEoNSXov0NiVMrzstBs03JmHHKG8IJn2k8EX4tWSAOT0o AW2f8dg4h3+wx+RcT+VxoFJhyEELrwN5iDfh83c36LMLxyrO0+90prHqCqSb5TnEP6sCyJY07R0BA tQFhFReQ6dgDDJOr+a27EnevTQDDlTqPmqhakX5dws3q5Lar022j4vY6vkN9TirhOjMZ8RgxoK3Zg x6c0ALKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjDJ-0000000AjRV-1UVA; Tue, 16 Jul 2024 14:31:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBI-0000000AiIb-12Ry for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 998E1113E; Tue, 16 Jul 2024 07:29:49 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A48933F762; Tue, 16 Jul 2024 07:29:23 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/6] aarch64: Prepare for lower EL booting Date: Tue, 16 Jul 2024 15:29:02 +0100 Message-Id: <20240716142906.1502802-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072928_369644_1DEEB8A9 X-CRM114-Status: GOOD ( 10.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Store the value of the initial SPSR into a variable during EL3 initialization and load it from the variable before dropping EL, this is done as preparation work to be able to boot from a different exception level. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- v2 changes: - add Andre R-by --- arch/aarch64/boot.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 7727475925c1..211077af17c8 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -51,6 +51,10 @@ reset_at_el3: b.eq err_invalid_id bl setup_stack + mov w0, #SPSR_KERNEL + ldr x1, =spsr_to_elx + str w0, [x1] + bl cpu_init_bootwrapper bl cpu_init_el3 @@ -135,7 +139,7 @@ ASM_FUNC(jump_kernel) b.eq 1f br x19 // Keep EL -1: mov x4, #SPSR_KERNEL +1: ldr w4, spsr_to_elx /* * If bit 0 of the kernel address is set, we're entering in AArch32 @@ -153,3 +157,5 @@ ASM_FUNC(jump_kernel) .align 3 flag_keep_el: .long 0 +spsr_to_elx: + .long 0 From patchwork Tue Jul 16 14:29:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2699C3DA49 for ; Tue, 16 Jul 2024 14:30:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=T1xZGu6MS1yliSzf7O6/Qq6uaYC7vNsgG3icJd6mri0=; b=AyZIo67n/8Pt7MOM6xtCRudX2I 3w1pinR82olRoTs6IQAQWy6elZlOGwfs59oFYB3WySuSfhfUbZe2fSSwqpX+9jrvq03z8eHbdQxkK xlsbA9FvQ5bt3fb+jBvmOy43UiPDvYLRkZzNsf8nAGsOrm7zDSrsJNMBKKc+Etha48OpeA8ZSXiwi tVOdHCOqTkJLRPhxnWqNYkWGRIwWqTuB0GsLWJqcP7hBXSTUG0yYg9eX0VNBtLDUZsP+YElzyLYU2 OFkgT9Q58YaubWRy6o72wIwLNeUAwhlFu/DETG9bdpWxYYveIV4C0yUAtUAQwOyTaCE35zSL2pdvz p8/RhOZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjCL-0000000AivK-1iyd; Tue, 16 Jul 2024 14:30:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBH-0000000AiI2-1F77 for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8879A11FB; Tue, 16 Jul 2024 07:29:50 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 936B53F762; Tue, 16 Jul 2024 07:29:24 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/6] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET Date: Tue, 16 Jul 2024 15:29:03 +0100 Message-Id: <20240716142906.1502802-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072927_408931_7FA0DD20 X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From the specification SCTLR_EL2.TSCXT is RES1 only "When FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so given that HCR_EL2.E2H is set by bootwrapper before to a value of zero, the condition above can't happen and from the specification the bit is RES0. Fix the macro removing the bit. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- v2 changes: - Add Andre R-by --- arch/aarch64/include/asm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 124ef916ddfc..846b89f8405d 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -30,8 +30,8 @@ BIT(11) | BIT(5) | BIT(4)) #define SCTLR_EL2_RES1 \ - (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) | \ - BIT(16) | BIT(11) | BIT(5) | BIT(4)) + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) | \ + BIT(11) | BIT(5) | BIT(4)) #define SCTLR_EL1_RES1 \ (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \ From patchwork Tue Jul 16 14:29:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4307BC3DA49 for ; Tue, 16 Jul 2024 14:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Kpy89/lavawsezo2CzABsDYSHtYDVKIQvBf62rU6e0k=; b=pL+A+Dfs3EB61rXKDkSzkb1KqN EpphWEvCad9hZ2Zpx81mdb6c4c2b/kCLXfJ79Tunn7BW1i0nHWPnu7di/F/hNV5s61gIlmEVfFkie yRiRt9G/XoEMCMym67jgrwEPNux4Js2zgTxVb6DOYXcXAUz5JPl0wB2keI6qoRBe8CGFgTfBKyajl H1eVUip2CanLxFAMrWLukV7OFctPNWACXYSpVBRk88VzPaCJoz/HzCPJCKP3NFx96VDemTVbuhupg 0qrJi2lkcqsF2/1/Locj9iG7V4+fdHh5wFptcMcoYaGTOnegDSt4ERI2bJzrkzYcVSKyOcHiup9Wn 9Xm1grFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjDb-0000000AjZ5-07x2; Tue, 16 Jul 2024 14:31:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBI-0000000AiJo-3hUV for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7754C12FC; Tue, 16 Jul 2024 07:29:51 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 827863F762; Tue, 16 Jul 2024 07:29:25 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/6] aarch64: Introduce EL2 boot code for Armv8-R AArch64 Date: Tue, 16 Jul 2024 15:29:04 +0100 Message-Id: <20240716142906.1502802-5-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072929_165335_EB8B4ADD X-CRM114-Status: GOOD ( 21.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Armv8-R AArch64 profile does not support the EL3 exception level. The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU at EL1, which allows to run off-the-shelf Linux. However EL2 only supports a PMSA, which is not supported by Linux, so we need to drop into EL1 before entering the kernel. We add a new err_invalid_arch symbol as a dead loop. If we detect the current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot Linux anymore, then we jump to err_invalid_arch. During Armv8-R aarch64 init, to make sure nothing unexpected traps into EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2. The boot sequence is: If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL before entering the kernel. If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64), if id_aa64mmfr0_el1.MSA_frac == 0x2, then goto Armv8-R AArch64 initialisation and drop to EL1 before entering the kernel. else, which means VMSA unsupported and cannot boot Linux, goto err_invalid_arch (dead loop). Else, no initialisation and keep the current EL before entering the kernel. Signed-off-by: Luca Fancellu --- v2 changes: - when booting from aarch64 armv8-r EL2, jump to reset_no_el3 to avoid code duplication. - codestyle fixes - write into HCR_EL2.ENSCXT unconditionally inside cpu_init_armv8r_el2 --- arch/aarch64/boot.S | 57 ++++++++++++++++++++++++++++++++-- arch/aarch64/include/asm/cpu.h | 11 +++++++ arch/aarch64/init.c | 29 +++++++++++++++++ 3 files changed, 95 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 211077af17c8..2a8234f7a17d 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -22,7 +22,8 @@ * EL2 must be implemented. * * - EL2 (Non-secure) - * Entering at EL2 is partially supported. + * Entering at EL2 is partially supported for Armv8-A. + * Entering at EL2 is supported for Armv8-R. * PSCI is not supported when entered in this exception level. */ ASM_FUNC(_start) @@ -76,6 +77,39 @@ reset_at_el2: msr sctlr_el2, x0 isb + /* Detect Armv8-R AArch64 */ + mrs x1, id_aa64mmfr0_el1 + /* + * Check MSA, bits [51:48]: + * 0xf means Armv8-R AArch64. + * If not 0xf, proceed in Armv8-A EL2. + */ + ubfx x0, x1, #48, #4 // MSA + cmp x0, 0xf + bne reset_no_el3 + + /* + * Armv8-R AArch64 is found, check if Linux can be booted. + * Check MSA_frac, bits [55:52]: + * 0x2 means EL1&0 translation regime also supports VMSAv8-64. + */ + ubfx x0, x1, #52, #4 // MSA_frac + cmp x0, 0x2 + /* + * If not 0x2, no VMSA, so cannot boot Linux and dead loop. + * Also, since the architecture guarantees that those CPUID + * fields never lose features when the value in a field + * increases, we use blt to cover it. + */ + blt err_invalid_arch + + /* Start Armv8-R Linux at EL1 */ + mov w0, #SPSR_KERNEL_EL1 + ldr x1, =spsr_to_elx + str w0, [x1] + + bl cpu_init_armv8r_el2 + b reset_no_el3 /* @@ -95,15 +129,22 @@ reset_no_el3: b.eq err_invalid_id bl setup_stack + ldr w1, spsr_to_elx + and w0, w1, 0xf + cmp w0, #SPSR_EL1H + b.eq drop_el + mov w0, #1 ldr x1, =flag_keep_el str w0, [x1] +drop_el: bl cpu_init_bootwrapper b start_bootmethod err_invalid_id: +err_invalid_arch: b . /* @@ -121,10 +162,14 @@ ASM_FUNC(jump_kernel) ldr x0, =SCTLR_EL1_KERNEL msr sctlr_el1, x0 + mrs x5, CurrentEL + cmp x5, #CURRENTEL_EL2 + b.eq 1f + ldr x0, =SCTLR_EL2_KERNEL msr sctlr_el2, x0 - cpuid x0, x1 +1: cpuid x0, x1 bl find_logical_id bl setup_stack // Reset stack pointer @@ -147,10 +192,18 @@ ASM_FUNC(jump_kernel) */ bfi x4, x19, #5, #1 + mrs x5, CurrentEL + cmp x5, #CURRENTEL_EL2 + b.eq 1f + msr elr_el3, x19 msr spsr_el3, x4 eret +1: msr elr_el2, x19 + msr spsr_el2, x4 + eret + .ltorg .data diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 846b89f8405d..280f488f267d 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -58,7 +58,13 @@ #define SCR_EL3_TCR2EN BIT(43) #define SCR_EL3_PIEN BIT(45) +#define VTCR_EL2_MSA BIT(31) + #define HCR_EL2_RES1 BIT(1) +#define HCR_EL2_APK_NOTRAP BIT(40) +#define HCR_EL2_API_NOTRAP BIT(41) +#define HCR_EL2_FIEN_NOTRAP BIT(47) +#define HCR_EL2_ENSCXT_NOTRAP BIT(53) #define ID_AA64DFR0_EL1_PMSVER BITS(35, 32) #define ID_AA64DFR0_EL1_TRACEBUFFER BITS(47, 44) @@ -88,7 +94,10 @@ #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) +#define ID_AA64PFR1_EL1_CSV2_frac BITS(35, 32) +#define ID_AA64PFR0_EL1_RAS BITS(31, 28) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) +#define ID_AA64PFR0_EL1_CSV2 BITS(59, 56) #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 #define ID_AA64SMFR0_EL1_FA64 BIT(63) @@ -114,6 +123,7 @@ #define SPSR_I (1 << 7) /* IRQ masked */ #define SPSR_F (1 << 6) /* FIQ masked */ #define SPSR_T (1 << 5) /* Thumb */ +#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */ #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */ @@ -153,6 +163,7 @@ #else #define SCTLR_EL1_KERNEL SCTLR_EL1_RES1 #define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) +#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H) #endif #ifndef __ASSEMBLY__ diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 37cb45fde446..9402a01b9dca 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -145,6 +145,35 @@ void cpu_init_el3(void) msr(CNTFRQ_EL0, COUNTER_FREQ); } +void cpu_init_armv8r_el2(void) +{ + unsigned long hcr = mrs(hcr_el2); + + msr(vpidr_el2, mrs(midr_el1)); + msr(vmpidr_el2, mrs(mpidr_el1)); + + /* VTCR_MSA: VMSAv8-64 support */ + msr(vtcr_el2, VTCR_EL2_MSA); + + /* + * HCR_EL2.ENSCXT is written unconditionally even if in some cases it's + * RES0 (when FEAT_CSV2_2 or FEAT_CSV2_1p2 are not implemented) in order + * to simplify the code, but it's safe in this case as the write would be + * ignored when not implemented and would remove the trap otherwise. + */ + hcr |= HCR_EL2_ENSCXT_NOTRAP; + + if (mrs_field(ID_AA64PFR0_EL1, RAS) >= 2) + hcr |= HCR_EL2_FIEN_NOTRAP; + + if (cpu_has_pauth()) + hcr |= HCR_EL2_APK_NOTRAP | HCR_EL2_API_NOTRAP; + + msr(hcr_el2, hcr); + isb(); + msr(CNTFRQ_EL0, COUNTER_FREQ); +} + #ifdef PSCI extern char psci_vectors[]; From patchwork Tue Jul 16 14:29:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C28D0C3DA59 for ; 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Tue, 16 Jul 2024 14:30:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBH-0000000AiIS-2N7c for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 66652139F; Tue, 16 Jul 2024 07:29:52 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 717743F762; Tue, 16 Jul 2024 07:29:26 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/6] aarch64: Support PSCI for Armv8-R AArch64 Date: Tue, 16 Jul 2024 15:29:05 +0100 Message-Id: <20240716142906.1502802-6-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072928_331363_33D56226 X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for PSCI when booting Linux on Armv8-R AArch64, allow the autoconf parameter --enable-psci to take an argument which is the conduit to be used, it can be empty or 'smc' to select the smc conduit, it can be 'hvc' for the hvc conduit. Depending on the selected conduit, the vector table will be installed on the VBAR_EL3 or VBAR_EL2 register. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- v2 changes: - Add Andre R-by --- Makefile.am | 5 ++++- arch/aarch64/init.c | 15 ++++++++++++--- configure.ac | 16 +++++++++++----- 3 files changed, 27 insertions(+), 9 deletions(-) diff --git a/Makefile.am b/Makefile.am index 6ebece25b230..34fbfb1f4ff8 100644 --- a/Makefile.am +++ b/Makefile.am @@ -49,11 +49,14 @@ endif if PSCI DEFINES += -DPSCI +if PSCI_HVC +DEFINES += -DPSCI_HVC +endif ARCH_OBJ += psci.o COMMON_OBJ += psci.o PSCI_NODE := psci { \ compatible = \"arm,psci\"; \ - method = \"smc\"; \ + method = \"$(PSCI_METHOD)\"; \ cpu_on = <$(PSCI_CPU_ON)>; \ cpu_off = <$(PSCI_CPU_OFF)>; \ }; diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 9402a01b9dca..9b8bd8723dba 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -179,10 +179,19 @@ extern char psci_vectors[]; bool cpu_init_psci_arch(void) { - if (mrs(CurrentEL) != CURRENTEL_EL3) + switch (mrs(CurrentEL)) { +#if !defined(PSCI_HVC) + case CURRENTEL_EL3: + msr(VBAR_EL3, (unsigned long)psci_vectors); + break; +#else + case CURRENTEL_EL2: + msr(VBAR_EL2, (unsigned long)psci_vectors); + break; +#endif + default: return false; - - msr(VBAR_EL3, (unsigned long)psci_vectors); + } isb(); return true; diff --git a/configure.ac b/configure.ac index 9e3b7226cd69..44459a4c849e 100644 --- a/configure.ac +++ b/configure.ac @@ -83,13 +83,19 @@ AS_IF([test "x$X_IMAGE" != "x"], # Allow a user to pass --enable-psci AC_ARG_ENABLE([psci], AS_HELP_STRING([--disable-psci], [disable the psci boot method]), - [USE_PSCI=$enableval], [USE_PSCI="yes"]) -AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes"]) -AS_IF([test "x$USE_PSCI" = "xyes"], [], [USE_PSCI=no]) - -AS_IF([test "x$USE_PSCI" != "xyes" -a "x$KERNEL_ES" = "x32"], + [case "${enableval}" in + yes|smc) USE_PSCI=smc ;; + hvc) USE_PSCI=hvc ;; + no) ;; + *) AC_MSG_ERROR([Bad value "${enableval}" for --enable-psci. Use "smc" or "hvc"]) ;; + esac]) +AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes" -o "x$USE_PSCI" = "xsmc" -o "x$USE_PSCI" = "xhvc"]) +AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"]) + +AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"], [AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])] ) +AC_SUBST([PSCI_METHOD], [$USE_PSCI]) # Allow a user to pass --with-initrd AC_ARG_WITH([initrd], From patchwork Tue Jul 16 14:29:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 360BDC3DA59 for ; Tue, 16 Jul 2024 14:31:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Eqxzabz0wwYTrZF5TJC5vlM43CBhbgHRKDk/6mspQFs=; b=uHiNDWxkxQ6pWPRmYNfvn7gqpM esNadVf68Gn8hU9ifNhJBoY1aiQkJGDa0Yzz87a/axSzqAMAQCxElZFBr7hEtACo00H69mdLd3ZGg RxVVqfvz7cRAVI2g5v4EVox7fwTMOnNjZj4JnPn53QFfQ3r/VH9X/7N1NGQTfcNlH0ddGDshr8yUU wZvjnuBxs6UsNt3OKxE78up46/1RYp6e8TPjpeDXvM2OLJthqJM/aCsgbcJXOvnC1sV3K5mfIRXtQ 7DNR0fKEYkC5F4lpGxduVTM4A6Oc05AeSPY5qZ3p4e52bEOM8Mnddiv4LEI2VWAGK1ji5DV9aIxcZ U4fsG2XQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjCy-0000000AjGT-3Zij; Tue, 16 Jul 2024 14:31:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBI-0000000AiIe-1XcN for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54D761063; Tue, 16 Jul 2024 07:29:53 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 600A03F762; Tue, 16 Jul 2024 07:29:27 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 6/6] aarch64: Start Xen on Armv8-R at EL2 Date: Tue, 16 Jul 2024 15:29:06 +0100 Message-Id: <20240716142906.1502802-7-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072928_475985_4C0A35DC X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When bootwrapper is compiled with Xen support and it is started at EL2 on Armv8-R AArch64, keep the current EL and jump to the Xen image. Signed-off-by: Luca Fancellu --- v2 changes: - Don't write 1 on flag_keep_el since now the logic will jump to reset_no_el3 and write it there. - removed check for smc conduit when Xen is booted, change commit message. --- Makefile.am | 1 + arch/aarch64/boot.S | 2 ++ 2 files changed, 3 insertions(+) diff --git a/Makefile.am b/Makefile.am index 34fbfb1f4ff8..bafce34682c3 100644 --- a/Makefile.am +++ b/Makefile.am @@ -112,6 +112,7 @@ XEN_CHOSEN := xen,xen-bootargs = \"$(XEN_CMDLINE)\"; \ compatible = \"xen,linux-zimage\", \"xen,multiboot-module\"; \ reg = <0x0 $(DOM0_OFFSET) 0x0 $(KERNEL_SIZE)>; \ }; +DEFINES += -DXEN endif if INITRD diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 2a8234f7a17d..38ed4ed48985 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -88,6 +88,7 @@ reset_at_el2: cmp x0, 0xf bne reset_no_el3 +#if !defined(XEN) /* * Armv8-R AArch64 is found, check if Linux can be booted. * Check MSA_frac, bits [55:52]: @@ -107,6 +108,7 @@ reset_at_el2: mov w0, #SPSR_KERNEL_EL1 ldr x1, =spsr_to_elx str w0, [x1] +#endif bl cpu_init_armv8r_el2