From patchwork Tue Jul 16 21:07:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13734930 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D67C11BF47 for ; Tue, 16 Jul 2024 21:08:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164106; cv=none; b=HLiN8PoCMVS9laI6N94xeuuMjan+wOIwxwD88ZR8/q9lmJPktlM1vu3Oqy2Rca6/h84QGjPVxPh0fwHaCPmWwr4lsimz6uRMbvKDRmJpW/urFuNF6upDS6/bHFpdv7eo+XwR6aJuZ4PzyEqYHmGZap+eScnk/wuXptLzSRKgBOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164106; c=relaxed/simple; bh=5m2v0RhXDU0qZYj3pY16Sl54Bc1zY+wL5a5p+Z7mkzg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hTilBAPoG3CIcuKfH6V0XnD5jUbehfUKHLtAxXy3Aj7mQySS7leSfNofTg/CXcC1gKgjyb6oJLo91WRstCp8YARGHjJ+d6RcaJOHdmtBxpVrRk1zZReNU2BCXKmNvKOL4fD7fg3On6Js+sgGfurC0tL2X2FD9PfOJeT/ep7UBXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kZIyOVAF; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kZIyOVAF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721164103; x=1752700103; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5m2v0RhXDU0qZYj3pY16Sl54Bc1zY+wL5a5p+Z7mkzg=; b=kZIyOVAFUEugRhLFx/OSlRtJYtA8xYDtoRQmn6Pak54sGc9V6THRlv10 LJ0W4pUTFPBgzAVD0C7nhSylpQdOpT19/kcHLf1PBaPIbtT2v20Q0Vgzl W1WfPPI3+O96+pQLNWEfGwuEcdFuvQH1d38ajz7dE/8vg+AV9CaUvwkI0 tH2dVRGYybIRiFAH3S0Hzt6RqnX1+Ho8MKjxcch1HutsuJGNAM33JijM9 HFyOleoiFVh7Jj4htpsGoZJxwNw37xCvK7ujoe+kjc2cQxwoZPwMkvNAS EytY469jYBHwVIrszEhLlOmYXQwfR09nNrpcftKEK8A7BeeGmTbXZYSbQ A==; X-CSE-ConnectionGUID: 1LgcYSi/QRSEOrdV5YgL0Q== X-CSE-MsgGUID: ifCpkP7NQxihVYSq7zp40Q== X-IronPort-AV: E=McAfee;i="6700,10204,11135"; a="18772994" X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="18772994" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:15 -0700 X-CSE-ConnectionGUID: t4wOvlRDSj66qfKHEAfFag== X-CSE-MsgGUID: xHLFwFLpRD2Lbs4oqtE+lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="87638687" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:15 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, andriy.shevchenko@linux.intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v8 1/6] platform/x86/intel/vsec.h: Move to include/linux Date: Tue, 16 Jul 2024 17:07:58 -0400 Message-ID: <20240716210805.4012517-2-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240716210805.4012517-1-michael.j.ruhl@intel.com> References: <20240716210805.4012517-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "David E. Box" Some drivers outside of PDX86 need access to the vsec header. Move it to include/linux to make it easier to include. Reviewed-by: Ilpo Järvinen Reviewed-by: Michael J. Ruhl Signed-off-by: David E. Box --- MAINTAINERS | 3 +- drivers/platform/x86/intel/pmc/core_ssram.c | 2 +- drivers/platform/x86/intel/pmt/class.c | 2 +- drivers/platform/x86/intel/pmt/class.h | 2 +- drivers/platform/x86/intel/pmt/crashlog.c | 2 +- drivers/platform/x86/intel/pmt/telemetry.c | 2 +- drivers/platform/x86/intel/sdsi.c | 3 +- drivers/platform/x86/intel/tpmi.c | 3 +- drivers/platform/x86/intel/vsec.c | 7 ++-- .../vsec.h => include/linux/intel_vsec.h | 32 +++++++++++++++++-- 10 files changed, 41 insertions(+), 17 deletions(-) rename drivers/platform/x86/intel/vsec.h => include/linux/intel_vsec.h (71%) diff --git a/MAINTAINERS b/MAINTAINERS index 782fb49059e7..131b6cd12f1e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11425,7 +11425,8 @@ F: drivers/platform/x86/intel/uncore-frequency/ INTEL VENDOR SPECIFIC EXTENDED CAPABILITIES DRIVER M: David E. Box S: Supported -F: drivers/platform/x86/intel/vsec.* +F: drivers/platform/x86/intel/vsec.c +F: include/linux/intel_vsec.h INTEL VIRTUAL BUTTON DRIVER M: AceLan Kao diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index 1bde86c54eb9..baddaaec25ee 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -9,11 +9,11 @@ */ #include +#include #include #include #include "core.h" -#include "../vsec.h" #include "../pmt/telemetry.h" #define SSRAM_HDR_SIZE 0x100 diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index 4b53940a64e2..d7939b28e937 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -9,12 +9,12 @@ */ #include +#include #include #include #include #include -#include "../vsec.h" #include "class.h" #define PMT_XA_START 1 diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index d23c63b73ab7..d6f9ccaf28c8 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -2,13 +2,13 @@ #ifndef _INTEL_PMT_CLASS_H #define _INTEL_PMT_CLASS_H +#include #include #include #include #include #include -#include "../vsec.h" #include "telemetry.h" /* PMT access types */ diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x86/intel/pmt/crashlog.c index 4014c02cafdb..9079d5dffc03 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include -#include "../vsec.h" #include "class.h" /* Crashlog discovery header types */ diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index 09258564dfc4..3478f891ea0b 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include -#include "../vsec.h" #include "class.h" #define TELEM_SIZE_OFFSET 0x0 diff --git a/drivers/platform/x86/intel/sdsi.c b/drivers/platform/x86/intel/sdsi.c index 277e4f4b20ac..9d137621f0e6 100644 --- a/drivers/platform/x86/intel/sdsi.c +++ b/drivers/platform/x86/intel/sdsi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,8 +23,6 @@ #include #include -#include "vsec.h" - #define ACCESS_TYPE_BARID 2 #define ACCESS_TYPE_LOCAL 3 diff --git a/drivers/platform/x86/intel/tpmi.c b/drivers/platform/x86/intel/tpmi.c index 6c0cbccd80bb..b9fa1cbfdcf7 100644 --- a/drivers/platform/x86/intel/tpmi.c +++ b/drivers/platform/x86/intel/tpmi.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -59,8 +60,6 @@ #include #include -#include "vsec.h" - /** * struct intel_tpmi_pfs_entry - TPMI PM Feature Structure (PFS) entry * @tpmi_id: TPMI feature identifier (what the feature is and its data format). diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 0fdfaf3a4f5c..2b46807f868b 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -17,14 +17,13 @@ #include #include #include -#include #include +#include +#include #include #include #include -#include "vsec.h" - #define PMT_XA_START 0 #define PMT_XA_MAX INT_MAX #define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX) @@ -341,7 +340,7 @@ static bool intel_vsec_walk_vsec(struct pci_dev *pdev, void intel_vsec_register(struct pci_dev *pdev, struct intel_vsec_platform_info *info) { - if (!pdev || !info) + if (!pdev || !info || !info->headers) return; intel_vsec_walk_header(pdev, info); diff --git a/drivers/platform/x86/intel/vsec.h b/include/linux/intel_vsec.h similarity index 71% rename from drivers/platform/x86/intel/vsec.h rename to include/linux/intel_vsec.h index e23e76129691..6495e37c9079 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/include/linux/intel_vsec.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _VSEC_H -#define _VSEC_H +#ifndef _INTEL_VSEC_H +#define _INTEL_VSEC_H #include #include @@ -67,7 +67,14 @@ enum intel_vsec_quirks { VSEC_QUIRK_EARLY_HW = BIT(4), }; -/* Platform specific data */ +/** + * struct intel_vsec_platform_info - Platform specific data + * @parent: parent device in the auxbus chain + * @headers: list of headers to define the PMT client devices to create + * @caps: bitmask of PMT capabilities for the given headers + * @quirks: bitmask of VSEC device quirks + * @base_addr: allow a base address to be specified (rather than derived) + */ struct intel_vsec_platform_info { struct device *parent; struct intel_vsec_header **headers; @@ -76,6 +83,18 @@ struct intel_vsec_platform_info { u64 base_addr; }; +/** + * struct intel_sec_device - Auxbus specific device information + * @auxdev: auxbus device struct for auxbus access + * @pcidev: pci device associated with the device + * @resource: any resources shared by the parent + * @ida: id reference + * @num_resources: number of resources + * @id: xarray id + * @priv_data: any private data needed + * @quirks: specified quirks + * @base_addr: base address of entries (if specified) + */ struct intel_vsec_device { struct auxiliary_device auxdev; struct pci_dev *pcidev; @@ -103,6 +122,13 @@ static inline struct intel_vsec_device *auxdev_to_ivdev(struct auxiliary_device return container_of(auxdev, struct intel_vsec_device, auxdev); } +#if IS_ENABLED(CONFIG_INTEL_VSEC) void intel_vsec_register(struct pci_dev *pdev, struct intel_vsec_platform_info *info); +#else +static inline void intel_vsec_register(struct pci_dev *pdev, + struct intel_vsec_platform_info *info) +{ +} +#endif #endif From patchwork Tue Jul 16 21:07:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13734931 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A603E5337F for ; Tue, 16 Jul 2024 21:08:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164107; cv=none; b=cEgqBjGe1P7XbfuNFfKn+3eg/vPP92j0p5rJB2aTlS9F4cErHbtp4awym8KhqqUJp2BxA413zmD+f12yXTGitordKYDkLAJRBe6Oc5QKimqJFocc11Zmat4XI+EiMjV6DxMlJxvGuU8otOe2jcc0ZJeR6zhoOyKCBn0J5+C1dj0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164107; c=relaxed/simple; bh=1FyhjEujvcHbnTpXOjI5J/XRQNsLRqw6RVYF/BcYzR4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aa4KySraL7zlRDMRz9DPMSTyGhlUB1Cga1IIAPfDChMd2wAt2LgpBbSSGL0rblmVgAYJaVrKlGKWSofgQbCzCitpa43cmEmBQnJt8NSd5bM+ftqwnPex8Oml6CFOrovzCfg9f/KfOCVXgFYmEvVUcFfyS5V7VdC0BbpItaBJUF8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gcsSSMvj; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gcsSSMvj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721164105; x=1752700105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1FyhjEujvcHbnTpXOjI5J/XRQNsLRqw6RVYF/BcYzR4=; b=gcsSSMvj9Z/s3QiMzYjJt4QkomuaxTdj4+RHLZzcZTztjzQdGqHV10N7 spTXtJfJf0irc5P19SjgmQ7E/nktp+R2ZSJEW42otQI8T6sfsHOouYI9n Y43mncgf056oS3mGHGiWk2WD6TimEaV5GH9FHqTvDuA55LZnzB5GiL4P1 sTrxd9fqDmlWW4TAy0rCDArVyLy7hkwJPV4+WvXueZd0Ar04NmXlXO2Ca xsUy7Pc/nXNroxUpqoKUWfSbM/AuPm/i85TI9B1KS1xmJ5wSiAE3BUu1X yBwBy8JD3Rri1croX5mREJA5C//SiIp7D2jrgyWAh0gAVu6eiKd+w/V6q A==; X-CSE-ConnectionGUID: d4hxadOiQvOPTKjJu0dAyA== X-CSE-MsgGUID: vDf3Wv5xS5eqQdNICUamvg== X-IronPort-AV: E=McAfee;i="6700,10204,11135"; a="18773001" X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="18773001" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:17 -0700 X-CSE-ConnectionGUID: fBogam7oSZirqG7nf1r2mA== X-CSE-MsgGUID: GgcQfZZjRm6mwkiWmhSuEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="87638718" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:17 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, andriy.shevchenko@linux.intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v8 2/6] platform/x86/intel/vsec: Add PMT read callbacks Date: Tue, 16 Jul 2024 17:07:59 -0400 Message-ID: <20240716210805.4012517-3-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240716210805.4012517-1-michael.j.ruhl@intel.com> References: <20240716210805.4012517-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "David E. Box" Some PMT providers require device specific actions before their telemetry can be read. Provide assignable PMT read callbacks to allow providers to perform those actions. Reviewed-by: Ilpo Järvinen Reviewed-by: Michael J. Ruhl Signed-off-by: David E. Box --- drivers/platform/x86/intel/vsec.c | 1 + include/linux/intel_vsec.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 2b46807f868b..7b5cc9993974 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -212,6 +212,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; intel_vsec_dev->base_addr = info->base_addr; + intel_vsec_dev->priv_data = info->priv_data; if (header->id == VSEC_ID_SDSI) intel_vsec_dev->ida = &intel_vsec_sdsi_ida; diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 6495e37c9079..11ee185566c3 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -67,10 +67,24 @@ enum intel_vsec_quirks { VSEC_QUIRK_EARLY_HW = BIT(4), }; +/** + * struct pmt_callbacks - Callback infrastructure for PMT devices + * ->read_telem() when specified, called by client driver to access PMT data (instead + * of direct copy). + * @pdev: PCI device reference for the callback's use + * @guid: ID of data to acccss + * @data: buffer for the data to be copied + * @count: size of buffer + */ +struct pmt_callbacks { + int (*read_telem)(struct pci_dev *pdev, u32 guid, u64 *data, u32 count); +}; + /** * struct intel_vsec_platform_info - Platform specific data * @parent: parent device in the auxbus chain * @headers: list of headers to define the PMT client devices to create + * @priv_data: private data, usable by parent devices, currently a callback * @caps: bitmask of PMT capabilities for the given headers * @quirks: bitmask of VSEC device quirks * @base_addr: allow a base address to be specified (rather than derived) @@ -78,6 +92,7 @@ enum intel_vsec_quirks { struct intel_vsec_platform_info { struct device *parent; struct intel_vsec_header **headers; + void *priv_data; unsigned long caps; unsigned long quirks; u64 base_addr; From patchwork Tue Jul 16 21:08:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13734932 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57BC161FCE for ; Tue, 16 Jul 2024 21:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164108; cv=none; b=K6+p2PTkramZmYsGfQqPMYGiwJ3DRnksbmhceYZyiOSAS8Fo5tpBjkHgFtOfdsY2ByoxjxiECD7GuLYa3lSuQpmLl3n7YbwU+LJeI6PbGaiOfb4UM5gMWoIvBeT2croHeVccG90L+4lRWcsZmgI716DkSndfofZP1+kel3BERqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164108; c=relaxed/simple; bh=WVKJz9jLuWJhZRq4+rVOokluWUkOLW9xPm97MZoSW8Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N1fPLoXgdzo1sS+WnN7zF24SOp9GsjF+jWVJDyaHmcgGO3lElxhDn4abcOzxYZIbk0xrV3Nlt6VSXMF1UGbSP+2Sdtggb5fpwCc2DvzuLO80xjpeuyZRyLwGNUkRlmMbVsk9EV3dlyQCHqETF6HyVaIijQZAJMhSrQTa00Bd5Lc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZF4WieVx; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZF4WieVx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721164106; x=1752700106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WVKJz9jLuWJhZRq4+rVOokluWUkOLW9xPm97MZoSW8Y=; b=ZF4WieVx+IIWuqC4rWx3+K+sVtP7kK7v7B1klOnbJ4aiY0qR8DW9lXux qumP4XYmxv4+2sV2h7fBdDDCBUTfRHMclVg7ypEwT8vNrwm7CV0gnWHLz FURhlOY7ExaE6/pVzcnJvvEd78whU/uQ2hOuIH8ps71vtPqxeEioVm9aF 8zkY8ZUnPQSSgL8keOWCbFoNrJp0HDBnzEeToXsvhsrTTlcSK0Y2NG9mj HM6afTEXsnPpgyEQhoZgnpXXARLvfPgyremMuhZfn9H9HuH9wxBvz5SJK rsJyAatNLs/XuzHBiQe76LO6iRjS6m2vBQi7UFe6rnSHY+bhlwPATxku4 g==; X-CSE-ConnectionGUID: wq0e0kybSP++Hd1mO8n9gA== X-CSE-MsgGUID: tqWZ5rpsR3a7FFi6ngEDmw== X-IronPort-AV: E=McAfee;i="6700,10204,11135"; a="18773010" X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="18773010" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:19 -0700 X-CSE-ConnectionGUID: RVY6K0ZkT2OkSqSvp97YBA== X-CSE-MsgGUID: q37yhuQBRbS5pqJ2zp1oig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="87638754" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:19 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, andriy.shevchenko@linux.intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v8 3/6] platform/x86/intel/pmt: Use PMT callbacks Date: Tue, 16 Jul 2024 17:08:00 -0400 Message-ID: <20240716210805.4012517-4-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240716210805.4012517-1-michael.j.ruhl@intel.com> References: <20240716210805.4012517-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "David E. Box" PMT providers may require device specific actions before their telemetry may be read. If the read_telem() is assigned, call it instead of memcpy_fromio() and return. Since this needs to be done in multiple locations, add pmt_telem_read_mmio() as a wrapper function to perform this and any other needed checks. Reviewed-by: Ilpo Järvinen Reviewed-by: Michael J. Ruhl Signed-off-by: David E. Box --- drivers/platform/x86/intel/pmt/class.c | 26 +++++++++++++++++----- drivers/platform/x86/intel/pmt/class.h | 8 +++++-- drivers/platform/x86/intel/pmt/telemetry.c | 10 +++++---- 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index d7939b28e937..c04bb7f97a4d 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -58,6 +58,22 @@ pmt_memcpy64_fromio(void *to, const u64 __iomem *from, size_t count) return count; } +int pmt_telem_read_mmio(struct pci_dev *pdev, struct pmt_callbacks *cb, u32 guid, void *buf, + void __iomem *addr, u32 count) +{ + if (cb && cb->read_telem) + return cb->read_telem(pdev, guid, buf, count); + + if (guid == GUID_SPR_PUNIT) + /* PUNIT on SPR only supports aligned 64-bit read */ + return pmt_memcpy64_fromio(buf, addr, count); + + memcpy_fromio(buf, addr, count); + + return count; +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_read_mmio, INTEL_PMT); + /* * sysfs */ @@ -79,11 +95,8 @@ intel_pmt_read(struct file *filp, struct kobject *kobj, if (count > entry->size - off) count = entry->size - off; - if (entry->guid == GUID_SPR_PUNIT) - /* PUNIT on SPR only supports aligned 64-bit read */ - count = pmt_memcpy64_fromio(buf, entry->base + off, count); - else - memcpy_fromio(buf, entry->base + off, count); + count = pmt_telem_read_mmio(entry->ep->pcidev, entry->cb, entry->header.guid, buf, + entry->base + off, count); return count; } @@ -239,6 +252,7 @@ static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, entry->guid = header->guid; entry->size = header->size; + entry->cb = ivdev->priv_data; return 0; } @@ -300,7 +314,7 @@ static int intel_pmt_dev_register(struct intel_pmt_entry *entry, goto fail_ioremap; if (ns->pmt_add_endpoint) { - ret = ns->pmt_add_endpoint(entry, ivdev->pcidev); + ret = ns->pmt_add_endpoint(ivdev, entry); if (ret) goto fail_add_endpoint; } diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index d6f9ccaf28c8..a267ac964423 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -24,6 +24,7 @@ struct pci_dev; struct telem_endpoint { struct pci_dev *pcidev; struct telem_header header; + struct pmt_callbacks *cb; void __iomem *base; bool present; struct kref kref; @@ -43,6 +44,7 @@ struct intel_pmt_entry { struct kobject *kobj; void __iomem *disc_table; void __iomem *base; + struct pmt_callbacks *cb; unsigned long base_addr; size_t size; u32 guid; @@ -55,10 +57,12 @@ struct intel_pmt_namespace { const struct attribute_group *attr_grp; int (*pmt_header_decode)(struct intel_pmt_entry *entry, struct device *dev); - int (*pmt_add_endpoint)(struct intel_pmt_entry *entry, - struct pci_dev *pdev); + int (*pmt_add_endpoint)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); }; +int pmt_telem_read_mmio(struct pci_dev *pdev, struct pmt_callbacks *cb, u32 guid, void *buf, + void __iomem *addr, u32 count); bool intel_pmt_is_early_client_hw(struct device *dev); int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_namespace *ns, diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index 3478f891ea0b..c9feac859e57 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -93,8 +93,8 @@ static int pmt_telem_header_decode(struct intel_pmt_entry *entry, return 0; } -static int pmt_telem_add_endpoint(struct intel_pmt_entry *entry, - struct pci_dev *pdev) +static int pmt_telem_add_endpoint(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) { struct telem_endpoint *ep; @@ -104,13 +104,14 @@ static int pmt_telem_add_endpoint(struct intel_pmt_entry *entry, return -ENOMEM; ep = entry->ep; - ep->pcidev = pdev; + ep->pcidev = ivdev->pcidev; ep->header.access_type = entry->header.access_type; ep->header.guid = entry->header.guid; ep->header.base_offset = entry->header.base_offset; ep->header.size = entry->header.size; ep->base = entry->base; ep->present = true; + ep->cb = ivdev->priv_data; kref_init(&ep->kref); @@ -218,7 +219,8 @@ int pmt_telem_read(struct telem_endpoint *ep, u32 id, u64 *data, u32 count) if (offset + NUM_BYTES_QWORD(count) > size) return -EINVAL; - memcpy_fromio(data, ep->base + offset, NUM_BYTES_QWORD(count)); + pmt_telem_read_mmio(ep->pcidev, ep->cb, ep->header.guid, data, ep->base + offset, + NUM_BYTES_QWORD(count)); return ep->present ? 0 : -EPIPE; } From patchwork Tue Jul 16 21:08:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13734933 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A181BF47 for ; Tue, 16 Jul 2024 21:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164109; cv=none; b=PYGxBO0vMaoekt20m6QSwLfZ/ucChgG69IbXAoSuT2swYg/9GBCn6xkF04ZTpQTM4Ijv9HqFzNKWtuF90VstdrXvRzuBws15GNbl89rpoz5qfo48kZZV8VuD5qbNRkM/VHGZYoQv0baGCImZH9BM7L7yK5Q7qIdwGUmRqeJoasI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164109; c=relaxed/simple; bh=TTaKdpn/Q4waoP0eUwM3Kmzrho9BezkqSXFbbpn4K8M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OD7VjpsEYhhiOgwQ6UN1jDyKnPtTNveoxthiigTqq96wshHnEtymeSUvS3Hh5GbEG5nOHSwaNHePztPpRCQeIYwlZv1vXP7a7qGM98GE5hcx3qFqznlO22RJ3+YRdzZHBXSo8i5ePsYdinr8COSpu4DurbE42jblNwSFEoeK+5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UiWCHit5; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UiWCHit5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721164107; x=1752700107; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TTaKdpn/Q4waoP0eUwM3Kmzrho9BezkqSXFbbpn4K8M=; b=UiWCHit5rD4V2rJ6fdjqxQ9DK/B8yWFUAc4edYkCtHfNrxUQKfsfH3RK LF6CIDI+4tmHSE9X5XDrm7JxofYQTl0rC2EJGdKOMsd6bx7LsXZuC8mvn 1YMclLOcNxMmatvyMzg7DDhGZYmM7mi2nI9ZyBelokzXq4aOgPTh4I1mf CqWTasgZNkVRkDS+2hpNRCgCG3BlTJDHE/Hg7X1VbHQWRfb6GW4bwKzMs cnUjYQPmWg+qTwEH5p9aNHpGzhOoj0PCKdj+oUSD76NVrJm0c85FZVMrO JgEgBMB1pl4QxU9NtuW+4Mr6eR3H0pJ+Imfx8QOo6ZwibWxsPB5cx9oAb A==; X-CSE-ConnectionGUID: aODkl4t/ThGZoP71SWQ0Fg== X-CSE-MsgGUID: gm08y14sR8GmGjVrWL/Iug== X-IronPort-AV: E=McAfee;i="6700,10204,11135"; a="18773020" X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="18773020" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:20 -0700 X-CSE-ConnectionGUID: 2kPMsabNRoqEI1QLihF2yA== X-CSE-MsgGUID: 1+W/vDHwTEmrcLN+KlOl4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="87638800" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:21 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, andriy.shevchenko@linux.intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v8 4/6] drm/xe/vsec: Support BMG devices Date: Tue, 16 Jul 2024 17:08:01 -0400 Message-ID: <20240716210805.4012517-5-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240716210805.4012517-1-michael.j.ruhl@intel.com> References: <20240716210805.4012517-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Utilize the PMT callback API to add support for the BMG devices. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 + drivers/gpu/drm/xe/xe_device_types.h | 6 + drivers/gpu/drm/xe/xe_vsec.c | 222 +++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_vsec.h | 13 ++ 5 files changed, 247 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_vsec.c create mode 100644 drivers/gpu/drm/xe/xe_vsec.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 1ff9602a52f6..a3c044b46fed 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -112,6 +112,7 @@ xe-y += xe_bb.o \ xe_vm.o \ xe_vram.o \ xe_vram_freq.o \ + xe_vsec.o \ xe_wait_user_fence.o \ xe_wa.o \ xe_wopcm.o diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 06cebaffb451..419539a65012 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -53,6 +53,7 @@ #include "xe_ttm_sys_mgr.h" #include "xe_vm.h" #include "xe_vram.h" +#include "xe_vsec.h" #include "xe_wait_user_fence.h" #include "xe_wa.h" @@ -320,6 +321,8 @@ struct xe_device *xe_device_create(struct pci_dev *pdev, goto err; } + drmm_mutex_init(&xe->drm, &xe->pmt.lock); + err = xe_display_create(xe); if (WARN_ON(err)) goto err; @@ -695,6 +698,8 @@ int xe_device_probe(struct xe_device *xe) for_each_gt(gt, xe, id) xe_gt_sanitize_freq(gt); + xe_vsec_init(xe); + return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe); err_fini_display: diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index f0cf9020e463..f443af2cf0b2 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -455,6 +455,12 @@ struct xe_device { struct mutex lock; } d3cold; + /** @pmt: Support the PMT driver callback interface */ + struct { + /** @pmt.lock: protect access for telemetry data */ + struct mutex lock; + } pmt; + /** * @pm_callback_task: Track the active task that is running in either * the runtime_suspend or runtime_resume callbacks. diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c new file mode 100644 index 000000000000..2fb71257aa02 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2022 - 2024 Intel Corporation + */ +#include +#include +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_device_types.h" +#include "xe_drv.h" +#include "xe_mmio.h" +#include "xe_platform_types.h" +#include "xe_pm.h" +#include "xe_vsec.h" + +#define SOC_BASE 0x280000 + +#define BMG_PMT_BASE 0xDB000 +#define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE) + +#define BMG_TELEMETRY_BASE 0xE0000 +#define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE) + +#define BMG_DEVICE_ID 0xE2F8 + +#define GFX_BAR 0 + +#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08) +#define SG_REMAP_BITS GENMASK(31, 24) + +static struct intel_vsec_header bmg_telemetry = { + .length = 0x10, + .id = VSEC_ID_TELEMETRY, + .num_entries = 2, + .entry_size = 4, + .tbir = GFX_BAR, + .offset = BMG_DISCOVERY_OFFSET, +}; + +static struct intel_vsec_header *bmg_capabilities[] = { + &bmg_telemetry, + NULL +}; + +enum xe_vsec { + XE_VSEC_UNKNOWN = 0, + XE_VSEC_BMG, +}; + +static struct intel_vsec_platform_info xe_vsec_info[] = { + [XE_VSEC_BMG] = { + .caps = VSEC_CAP_TELEMETRY, + .headers = bmg_capabilities, + }, + { } +}; + +/* + * The GUID will have the following bits to decode: + * + * X(4bits) - {Telemetry space iteration number (0,1,..)} + * X(4bits) - Segment (SEGMENT_INDEPENDENT-0, Client-1, Server-2) + * X(4bits) - SOC_SKU (SKU_INDEPENDENT-0, X3-1, X2-2, G31-3), + * XXXX(16bits)– Device ID – changes for each down bin SKU’s (0xE2F8 for BMG) + * X(2bits) - Capability Type (Crashlog-0, Telemetry Aggregator-1, Watcher-2) + * X(2bits) - Record-ID (0-PUNIT, 1-OOBMSM_0, 2-OOBMSM_1) + */ +#define GUID_TELEM_ITERATION GENMASK(3, 0) +#define GUID_SEGMENT GENMASK(7, 4) +#define GUID_SOC_SKU GENMASK(11, 8) +#define GUID_DEVICE_ID GENMASK(27, 12) +#define GUID_CAP_TYPE GENMASK(29, 28) +#define GUID_RECORD_ID GENMASK(31, 30) + +#define PUNIT_TELEMETRY_OFFSET 0x0200 +#define PUNIT_WATCHER_OFFSET 0x14A0 +#define OOBMSM_0_WATCHER_OFFSET 0x18D8 +#define OOBMSM_1_TELEMETRY_OFFSET 0x1000 + +enum record_id { + PUNIT, + OOBMSM_0, + OOBMSM_1 +}; + +enum capability { + CRASHLOG, + TELEMETRY, + WATCHER +}; + +static int guid_decode(u32 guid, int *index, u32 *offset) +{ + u32 record_id = FIELD_GET(GUID_RECORD_ID, guid); + u32 cap_type = FIELD_GET(GUID_CAP_TYPE, guid); + u32 device_id = FIELD_GET(GUID_DEVICE_ID, guid); + + if (device_id != BMG_DEVICE_ID) + return -ENODEV; + + if (record_id > OOBMSM_1 || cap_type > WATCHER) + return -EINVAL; + + *offset = 0; + + if (cap_type == CRASHLOG) { + *index = record_id == PUNIT ? 2 : 4; + return 0; + } + + switch (record_id) { + case PUNIT: + *index = 0; + if (cap_type == TELEMETRY) + *offset = PUNIT_TELEMETRY_OFFSET; + else + *offset = PUNIT_WATCHER_OFFSET; + break; + + case OOBMSM_0: + *index = 1; + if (cap_type == WATCHER) + *offset = OOBMSM_0_WATCHER_OFFSET; + break; + + case OOBMSM_1: + *index = 1; + if (cap_type == TELEMETRY) + *offset = OOBMSM_1_TELEMETRY_OFFSET; + break; + } + + return 0; +} + +static int xe_pmt_telem_read(struct pci_dev *pdev, u32 guid, u64 *data, u32 count) +{ + struct xe_device *xe = pdev_to_xe_device(pdev); + void __iomem *telem_addr = xe->mmio.regs + BMG_TELEMETRY_OFFSET; + u32 mem_region; + u32 offset; + int ret; + + ret = guid_decode(guid, &mem_region, &offset); + if (ret) + return ret; + + telem_addr += offset; + + mutex_lock(&xe->pmt.lock); + + /* indicate that we are not at an appropriate power level */ + ret = -ENODATA; + if (xe_pm_runtime_get_if_active(xe) > 0) { + /* set SoC re-mapper index register based on GUID memory region */ + xe_mmio_rmw32(xe->tiles[0].primary_gt, SG_REMAP_INDEX1, SG_REMAP_BITS, + FIELD_PREP(SG_REMAP_BITS, mem_region)); + + memcpy_fromio(data, telem_addr, count); + ret = count; + xe_pm_runtime_put(xe); + } + mutex_unlock(&xe->pmt.lock); + + return ret; +} + +struct pmt_callbacks xe_pmt_cb = { + .read_telem = xe_pmt_telem_read, +}; + +static const int vsec_platforms[] = { + [XE_BATTLEMAGE] = XE_VSEC_BMG, +}; + +static enum xe_vsec get_platform_info(struct xe_device *xe) +{ + if (xe->info.platform > XE_BATTLEMAGE) + return XE_VSEC_UNKNOWN; + + return vsec_platforms[xe->info.platform]; +} + +/** + * xe_vsec_init - Initialize resources and add intel_vsec auxiliary + * interface + * @xe: valid xe instance + */ +void xe_vsec_init(struct xe_device *xe) +{ + struct intel_vsec_platform_info *info; + struct device *dev = xe->drm.dev; + struct pci_dev *pdev = to_pci_dev(dev); + enum xe_vsec platform; + + platform = get_platform_info(xe); + if (platform == XE_VSEC_UNKNOWN) + return; + + info = &xe_vsec_info[platform]; + if (!info->headers) + return; + + switch (platform) { + case XE_VSEC_BMG: + info->priv_data = &xe_pmt_cb; + break; + default: + break; + } + + /* + * Register a VSEC. Cleanup is handled using device managed + * resources. + */ + intel_vsec_register(pdev, info); +} +MODULE_IMPORT_NS(INTEL_VSEC); diff --git a/drivers/gpu/drm/xe/xe_vsec.h b/drivers/gpu/drm/xe/xe_vsec.h new file mode 100644 index 000000000000..3fd29a21cad6 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_vsec.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright © 2022 - 2024 Intel Corporation + */ + +#ifndef _XE_VSEC_H_ +#define _XE_VSEC_H_ + +struct xe_device; + +void xe_vsec_init(struct xe_device *xe); + +#endif From patchwork Tue Jul 16 21:08:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13734934 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05CE4757E5 for ; Tue, 16 Jul 2024 21:08:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164109; cv=none; b=HiLcFwJtymB6jgRM2v2IOdKeFhDRqStQYjbt8JW+4QnGwgFZgC4vLJ002HEBRh+ocTbYxwZcyD9N+FJ/iDo7R28N9oZdynFegBrCzLuW51aXab7K/x0mEmh3/FTYtYyh7WsKsco82Wr82dB+YDDm/yLiIAQDlsVl4tzTREVM4T4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721164109; c=relaxed/simple; bh=wyN+6vlgHGDP8X6HQQjWIl85e1yzHPrW2QH2cE5m7Yo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eH/yKbZWUC5vmqySlPMJ+QLr0BOGSxSrbJ8TLhPI5gcxxPCJ7woWwRnI1iU+C7tH8QqeiJq3mOe+rdWKU1ADOE+NlN8ziw1EdukMvr2dzMyXOZBUq6dxXcrJgmPKZGYUPwgx931hURmo0sBxNvMqkB9zTh8a/JLJE9EGdD/WYHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L5nejIF8; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L5nejIF8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721164108; x=1752700108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wyN+6vlgHGDP8X6HQQjWIl85e1yzHPrW2QH2cE5m7Yo=; b=L5nejIF8sogRPpUFMPZXW2VbivoKPG7+B83J08f+7EYoEwUW82FpLOjJ UOpG59u88zCscMlRE2NMdF4oQgiGYbjrqSkGJAT4I6bctuJn873PIIDAn FgG8A4DHKeCbdOTX44y7Xw7GLJeuFmsCecoGKYVXYbFD2g/KS28QoDj1R uaUJ6A/e9/3trKDTQ2KeV26VBMrR8DBajDkw00Oj6VJRo3gy4WU9BfJuQ 2ZV732jooH0I1KXlvkJpvYnHyQDYwxHsG97YLA2ht1Ua5OXFUD05DxAE9 nj3EzyOy/V28wt8OvIBGeiBtGbyIdMkjxNIN7K3cXHWfh6Lg9d5SH3HLz A==; X-CSE-ConnectionGUID: 6Zwgcn9mQWaMlwrlZ91o9w== X-CSE-MsgGUID: CoLpN9hqQNaQcxfaLmIByw== X-IronPort-AV: E=McAfee;i="6700,10204,11135"; a="18773032" X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="18773032" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:23 -0700 X-CSE-ConnectionGUID: d1LZDtYyR1uc61lSEKmnug== X-CSE-MsgGUID: MVWwrSVJSYGo1WVz2RUFhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,212,1716274800"; d="scan'208";a="87638825" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2024 14:08:22 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, andriy.shevchenko@linux.intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v8 5/6] platform/x86/intel/pmt: Add support for PMT base adjust Date: Tue, 16 Jul 2024 17:08:02 -0400 Message-ID: <20240716210805.4012517-6-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240716210805.4012517-1-michael.j.ruhl@intel.com> References: <20240716210805.4012517-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 DVSEC offsets are based on the endpoint BAR. If an endpoint is not available allow the offset information to be adjusted by the parent driver. Signed-off-by: Michael J. Ruhl --- drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 9 +++++++++ drivers/platform/x86/intel/vsec.c | 1 + include/linux/intel_vsec.h | 3 +++ 4 files changed, 14 insertions(+) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index a267ac964423..984cd40ee814 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -46,6 +46,7 @@ struct intel_pmt_entry { void __iomem *base; struct pmt_callbacks *cb; unsigned long base_addr; + s32 base_adjust; size_t size; u32 guid; int devid; diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index c9feac859e57..88e4f1315097 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -78,6 +78,13 @@ static int pmt_telem_header_decode(struct intel_pmt_entry *entry, header->access_type = TELEM_ACCESS(readl(disc_table)); header->guid = readl(disc_table + TELEM_GUID_OFFSET); header->base_offset = readl(disc_table + TELEM_BASE_OFFSET); + if (entry->base_adjust) { + u32 new_base = header->base_offset + entry->base_adjust; + + dev_dbg(dev, "Adjusting base offset from 0x%x to 0x%x\n", + header->base_offset, new_base); + header->base_offset = new_base; + } /* Size is measured in DWORDS, but accessor returns bytes */ header->size = TELEM_SIZE(readl(disc_table)); @@ -302,6 +309,8 @@ static int pmt_telem_probe(struct auxiliary_device *auxdev, const struct auxilia for (i = 0; i < intel_vsec_dev->num_resources; i++) { struct intel_pmt_entry *entry = &priv->entry[priv->num_entries]; + entry->base_adjust = intel_vsec_dev->base_adjust; + mutex_lock(&ep_lock); ret = intel_pmt_dev_create(entry, &pmt_telem_ns, intel_vsec_dev, i); mutex_unlock(&ep_lock); diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 7b5cc9993974..be079d62a7bc 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -212,6 +212,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; intel_vsec_dev->base_addr = info->base_addr; + intel_vsec_dev->base_adjust = info->base_adjust; intel_vsec_dev->priv_data = info->priv_data; if (header->id == VSEC_ID_SDSI) diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 11ee185566c3..75d17fa10d05 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -88,6 +88,7 @@ struct pmt_callbacks { * @caps: bitmask of PMT capabilities for the given headers * @quirks: bitmask of VSEC device quirks * @base_addr: allow a base address to be specified (rather than derived) + * @base_adjust: allow adjustment to base offset information */ struct intel_vsec_platform_info { struct device *parent; @@ -96,6 +97,7 @@ struct intel_vsec_platform_info { unsigned long caps; unsigned long quirks; u64 base_addr; + s32 base_adjust; }; /** @@ -121,6 +123,7 @@ struct intel_vsec_device { size_t priv_data_size; unsigned long quirks; u64 base_addr; + s32 base_adjust; }; int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, From patchwork Tue Jul 16 21:08:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. 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Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, andriy.shevchenko@linux.intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v8 6/6] drm/xe/vsec: Add support for DG2 Date: Tue, 16 Jul 2024 17:08:03 -0400 Message-ID: <20240716210805.4012517-7-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240716210805.4012517-1-michael.j.ruhl@intel.com> References: <20240716210805.4012517-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PMT (DVSEC) offset information is based on the PCI BAR for the telemetry (PCI) endpoint (also known as the P2SB). However the DG2 endpoint is not completely functional, and is disabled. In order to allow access to the DG2 PMT features it is necessary to inform the VSEC driver of the correct offset via the base_adjust value. This odjustment is the difference between the telemetry offset (read from the PMT register) and the fixed offset in the Xe SOC space. Calculate the offset, and pass it to the VSEC driver on header registration. Update xe_vsec.c to include DG2 header information. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/xe_vsec.c | 78 ++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c index 2fb71257aa02..b1c870cec879 100644 --- a/drivers/gpu/drm/xe/xe_vsec.c +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -19,6 +19,16 @@ #define SOC_BASE 0x280000 +/* from drivers/platform/x86/intel/pmt/telemetry.c */ +#define TELEM_BASE_OFFSET 0x8 + +#define DG2_PMT_BASE 0xE8000 +#define DG2_DISCOVERY_START 0x6000 +#define DG2_TELEM_START 0x4000 + +#define DG2_DISCOVERY_OFFSET (SOC_BASE + DG2_PMT_BASE + DG2_DISCOVERY_START) +#define DG2_TELEM_OFFSET (SOC_BASE + DG2_PMT_BASE + DG2_TELEM_START) + #define BMG_PMT_BASE 0xDB000 #define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE) @@ -32,6 +42,20 @@ #define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08) #define SG_REMAP_BITS GENMASK(31, 24) +static struct intel_vsec_header dg2_telemetry = { + .length = 0x10, + .id = VSEC_ID_TELEMETRY, + .num_entries = 1, + .entry_size = 3, + .tbir = GFX_BAR, + .offset = DG2_DISCOVERY_OFFSET, +}; + +static struct intel_vsec_header *dg2_capabilities[] = { + &dg2_telemetry, + NULL +}; + static struct intel_vsec_header bmg_telemetry = { .length = 0x10, .id = VSEC_ID_TELEMETRY, @@ -48,10 +72,16 @@ static struct intel_vsec_header *bmg_capabilities[] = { enum xe_vsec { XE_VSEC_UNKNOWN = 0, + XE_VSEC_DG2, XE_VSEC_BMG, }; static struct intel_vsec_platform_info xe_vsec_info[] = { + [XE_VSEC_DG2] = { + .caps = VSEC_CAP_TELEMETRY, + .headers = dg2_capabilities, + .quirks = VSEC_QUIRK_EARLY_HW, + }, [XE_VSEC_BMG] = { .caps = VSEC_CAP_TELEMETRY, .headers = bmg_capabilities, @@ -174,6 +204,7 @@ struct pmt_callbacks xe_pmt_cb = { }; static const int vsec_platforms[] = { + [XE_DG2] = XE_VSEC_DG2, [XE_BATTLEMAGE] = XE_VSEC_BMG, }; @@ -185,6 +216,46 @@ static enum xe_vsec get_platform_info(struct xe_device *xe) return vsec_platforms[xe->info.platform]; } +/* + * Access the DG2 PMT MMIO discovery table + * + * The intel_vsec driver does not typically access the discovery table. + * Instead, it creates a memory resource for the table and passes it + * to the PMT telemetry driver. Each discovery table contains 3 items, + * - GUID + * - Telemetry size + * - Telemetry offset (offset from P2SB BAR, not GT) + * + * For DG2 we know what the telemetry offset is, but we still need to + * use the discovery table to pass the GUID and the size. So figure + * out the difference between the P2SB offset and the GT offset and + * save this so that the telemetry driver can use it to adjust the + * value. + */ +static int dg2_adjust_offset(struct pci_dev *pdev, struct device *dev, + struct intel_vsec_platform_info *info) +{ + void __iomem *base; + u32 telem_offset; + u64 addr; + + addr = pci_resource_start(pdev, GFX_BAR) + info->headers[0]->offset; + base = ioremap_wc(addr, 16); + if (!base) + return -ENOMEM; + + telem_offset = readl(base + TELEM_BASE_OFFSET); + + if (telem_offset < DG2_TELEM_OFFSET) + info->base_adjust = -(DG2_TELEM_OFFSET - telem_offset); + else + info->base_adjust = -(telem_offset - DG2_TELEM_OFFSET); + + iounmap(base); + + return 0; +} + /** * xe_vsec_init - Initialize resources and add intel_vsec auxiliary * interface @@ -196,6 +267,7 @@ void xe_vsec_init(struct xe_device *xe) struct device *dev = xe->drm.dev; struct pci_dev *pdev = to_pci_dev(dev); enum xe_vsec platform; + u32 ret; platform = get_platform_info(xe); if (platform == XE_VSEC_UNKNOWN) @@ -206,6 +278,12 @@ void xe_vsec_init(struct xe_device *xe) return; switch (platform) { + case XE_VSEC_DG2: + ret = dg2_adjust_offset(pdev, dev, info); + if (ret) + return; + break; + case XE_VSEC_BMG: info->priv_data = &xe_pmt_cb; break;