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Wed, 17 Jul 2024 00:21:54 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH] iommu: arm-smmu: Fix Tegra workaround for PAGE_SIZE mappings Date: Wed, 17 Jul 2024 07:21:45 +0000 Message-ID: <20240717072145.107412-1-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|IA1PR12MB6281:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b52c4cd-ad5e-4a0c-135d-08dca63128a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: yxrxKiR7psD86A9GElHpMiBHHtJwAr6YQShujKc6U6YOjYonfPVnqztzzQ5dSDp5faLDkmrn0Y/AxAum6YlZOCU5/ztMnCI6ZruIRFu5WVtg1icmgD9PKmLJk0L5ef6tmzhWRdVofKIGzY1hzk8zki0/YNiYEvReWj5KCuXlMF3ObTgmDcXVW1XLXYSh3xVdrvnfDfq6WFqJZaLd6AHQpZBrBQqt2fMETsyrZWkk0rziXhf6ohS7qUaGKqoWnj+M5OV1BVXpW0mogg+X8prTGxvoemtPlyz5hJekzeIWkRub4RRRumXo+tBJ6KT0MxRP+/WJwYXNyES4dltrbnIbjzyFL+8Rxo2nlmQVZbZrtmVrM3DqdJg9pId6oIWLBCcPPYAX68EIvDdrjrv0b9fqPzCrNJHILTbvca8rvuoIQaN/vqgzX9NUd1o8RYmUHNgpvQAGKuYDC9+zX3gTfxPcEBalK6DS79CqADUVxF3Kaka8tMjTiqM9kdFffj59Ezp3c38nxtnR6JDucj5GGYLW7jCGxW7W7LGDwAmSWkHj9KbKovqxTue+PhvzdCo3xWEMQ+AhUuEhVzmdBRUWcWuufjijI3WGV3M9E7bHjTzSvJ4ekAhM+xCVsBphonwXuKBri3HORvo7iQdHyuNvB8LyCVk9Fhxb0p8NTZv0FZdm2RvDNJm8Vkq6d5MPuTrxsUS3XB/WFkBZSm0vOozHX0JPIq/ZbDhYaL8vG6rtqatUIzruQrXH83FNQ8SaRYub4/j1W8ymrXlq0o5Na3wjSWtur/2FxcQJ7fvcBvpcSE6e4kGgdYJOwwKPKxs/mE5AHiIUQ1o1kA/XbNeO5j/dB+FNtwnqE601dMWntxedb5crksTAaNufszsbIZjpS1dJ7lBcC5JqDhutox/ZMDH6SD00XJgQNyUT+R51XU9db7mZ6stZL04SPnYHnjbKE8BBpv++ZyVk7YqKlrSBG0ZH5UVWLGeHgd1WD5QjVRYAuyD0YW8TqERkhAnstHJnJe+1pcvOI5tvVf5PHhUGc79FL2ICSR3KD1FFGVCtWb3Z8eXq8pfzT26GVBeehDBuStaS+OLImpAt5v62cLOeJ6k6lyxfdQr/jgaz5/BNjX+/Vujrv8tdIsP3FUHovUumYbjxDyfmcZRa/lKvH1ZSHEwChiImD3toH/sp23gGYXBhMXoxKvh0Y3NYQxq75sp/rQc8it9odJsQLNjKlGBQqa6l8X90NfxT467mdBwEEf/9ryqCSPmweYiDtHe66wsn7zyZUbcNpJbX7sWtrPpFKukVFQuMugCJRIudnc9i6x/UcGcYbL5z1dmlFqLngUoAKU9cFBYcna9e3TfCepkl1qjO9pxSlwnHb1N3udutEEA82hpC7qjBj19/ApI+PX+9/E5q9VZHR7lW0h+CLXQgDCvGBnyoHibKT6y6KYhW9qMAH15sN/ufmB6KT2C4aD+GRDgXX03W X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 07:22:04.3539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b52c4cd-ad5e-4a0c-135d-08dca63128a7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6281 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240717_002213_786477_A5AFB26A X-CRM114-Status: GOOD ( 10.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PAGE_SIZE can be 16KB for Tegra which is not supported by MMU-500 on both Tegra194 and Tegra234. So, use 4KB mappings when PAGE_SIZE is 16KB. Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c index 4b2994b6126d..bb621a94f6fe 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c @@ -273,11 +273,12 @@ static int nvidia_smmu_init_context(struct arm_smmu_domain *smmu_domain, * release of PMD entry and avoid translations seeing stale PMD entry in * walk cache. * Fix this by limiting the page mappings to PAGE_SIZE on Tegra194 and - * Tegra234. + * Tegra234. Use 4K page mappings if PAGE_SIZE is 16K as MMU500 doesn't + * support it. */ if (of_device_is_compatible(np, "nvidia,tegra234-smmu") || of_device_is_compatible(np, "nvidia,tegra194-smmu")) { - smmu->pgsize_bitmap = PAGE_SIZE; + smmu->pgsize_bitmap = (PAGE_SIZE == SZ_16K) ? SZ_4K : PAGE_SIZE; pgtbl_cfg->pgsize_bitmap = smmu->pgsize_bitmap; }