From patchwork Wed Jul 17 09:08:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Willi X-Patchwork-Id: 13735243 X-Patchwork-Delegate: kuba@kernel.org Received: from mail.codelabs.ch (mail.codelabs.ch [109.202.192.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC5BE37160 for ; Wed, 17 Jul 2024 09:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.202.192.35 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721207330; cv=none; b=GWOJDXk2xlg8ZDy1Hzkp/bhb6ofIxUb4tQMfF/VIt0/9dpEiEVgjKDXmiyBZFN42yfJh5Std911P5YmV0HvwOl+5PWZhMSSxAHGhg0UvrdHG77qNESUz6XE8gdNyAOTFLVcDQqXHnS0rFGXf/KzpmgmLuG2BR/hHijHpfLpKVTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721207330; c=relaxed/simple; bh=sJFPH4SzOIchPvnOtl0r8sDlfrqVfDvjgzlzSpGuHPM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WbUUxnb3LNT/MHJMqckVlGZkpmZOmIO2/eU/tfPIIZL9eGJy8ehgKZT70FVrJfcNdU3e7NuSZZDZNJwub0S9h7H4NEuC/a794gnOpKpVKADMO9YI64+9Ffn8eECKtpN8djtTQk7gvdx2HUyOgzm9jTtIGXuWdeT9E8As/86huPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=strongswan.org; spf=pass smtp.mailfrom=strongswan.org; dkim=pass (2048-bit key) header.d=strongswan.org header.i=@strongswan.org header.b=aCHD06fC; arc=none smtp.client-ip=109.202.192.35 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=strongswan.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=strongswan.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=strongswan.org header.i=@strongswan.org header.b="aCHD06fC" Received: from localhost (localhost [127.0.0.1]) by mail.codelabs.ch (Postfix) with ESMTP id 5E3905A0004; Wed, 17 Jul 2024 11:08:44 +0200 (CEST) Received: from mail.codelabs.ch ([127.0.0.1]) by localhost (fenrir.codelabs.ch [127.0.0.1]) (amavis, port 10024) with ESMTP id ZyNmjALlk2IG; Wed, 17 Jul 2024 11:08:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=strongswan.org; s=default; t=1721207323; bh=sJFPH4SzOIchPvnOtl0r8sDlfrqVfDvjgzlzSpGuHPM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aCHD06fCJ1iEwQbDglyY26AcgmfVTNXymAMN+Xkz3KrU/ykV7uh17tMv6tlon9GlL iOtiEKTAJzqyDKnbb+3GF7xFzYVHNCxcXvMXJE1NVXfueba82/BCPO5gydkgfAcwbr +LUosaazM+5tmzHl7oX2i6/ZuL1S+G2yyjAaWac3BPd8C6NV2TaEaeSh/Er2hR9k8F scLZDR/5u7zHC/aXHJ2NeSovl3DgIryqwcHgGZUV+/W50b+RudfBqy4Wk6IM3ukwBG dYnrsAF83u280wCqHNntnKB5IexWASd0IXeM+BiBGtzM/axYrBxjQHu3I2a2QovB1Q gjR3wQ822m7qg== Received: from think.home (unknown [185.12.128.224]) by mail.codelabs.ch (Postfix) with ESMTPSA id 3DD105A0002; Wed, 17 Jul 2024 11:08:43 +0200 (CEST) From: Martin Willi To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , Chris Packham , Murali Krishna Policharla Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: [PATCH net v2 1/2] net: dsa: mv88e6xxx: Limit chip-wide frame size config to CPU ports Date: Wed, 17 Jul 2024 11:08:19 +0200 Message-ID: <20240717090820.894234-2-martin@strongswan.org> In-Reply-To: <20240717090820.894234-1-martin@strongswan.org> References: <20240717090820.894234-1-martin@strongswan.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Marvell chips not supporting per-port jumbo frame size configurations use a chip-wide frame size configuration. In the commit referenced with the Fixes tag, the setting is applied just for the last port changing its MTU. While configuring CPU ports accounts for tagger overhead, user ports do not. When setting the MTU for a user port, the chip-wide setting is reduced to not include the tagger overhead, resulting in an potentially insufficient maximum frame size for the CPU port. Specifically, sending full-size frames from the CPU port on a MV88E6097 having a user port MTU of 1500 bytes results in dropped frames. As, by design, the CPU port MTU is adjusted for any user port change, apply the chip-wide setting only for CPU ports. Fixes: 1baf0fac10fb ("net: dsa: mv88e6xxx: Use chip-wide max frame size for MTU") Suggested-by: Vladimir Oltean Signed-off-by: Martin Willi Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mv88e6xxx/chip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 07c897b13de1..5b4e2ce5470d 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3626,7 +3626,8 @@ static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) mv88e6xxx_reg_lock(chip); if (chip->info->ops->port_set_jumbo_size) ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); - else if (chip->info->ops->set_max_frame_size) + else if (chip->info->ops->set_max_frame_size && + dsa_is_cpu_port(ds, port)) ret = chip->info->ops->set_max_frame_size(chip, new_mtu); mv88e6xxx_reg_unlock(chip); From patchwork Wed Jul 17 09:08:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Willi X-Patchwork-Id: 13735242 X-Patchwork-Delegate: kuba@kernel.org Received: from mail.codelabs.ch (mail.codelabs.ch [109.202.192.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E44A38F97 for ; Wed, 17 Jul 2024 09:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.202.192.35 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721207330; cv=none; b=nfvaZm+IJ0BzRy4vsoD94E4cmItA+uItYSsidz5hM2YVAzfHD1mTUZHWMF0+rKZHlvZhYza540g6P/+1PWWDBZ4DYuEGpD4MI4vWk7HIx6PRPB0y3qL89NyhYNd/MMBj+f1a85nk06u3f3NYTNvczsrAk4E71zST5/59XPBjtck= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721207330; c=relaxed/simple; bh=N42cqY0I8yT6ZfvI+LElwDnJf0ppkaP3hiNRDj9hcFY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E9hXnsyNnAMhUSjN5kvJsMjJsYD71doW6RPT+2Lz/92t9MDVIso9GjOrZFzO0/wD6LDy6oCeuwz3ghmDCwT6FXbbXU5qewL4HD1D9bRCeR4E3KV8QjW0rHwBXMPFemJ+o2UjuRrMxiLwI5rvPRoPXzE9l5uwkDGOsuvxn5Kk1Dk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=strongswan.org; spf=pass smtp.mailfrom=strongswan.org; dkim=pass (2048-bit key) header.d=strongswan.org header.i=@strongswan.org header.b=GawDM/DO; arc=none smtp.client-ip=109.202.192.35 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=strongswan.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=strongswan.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=strongswan.org header.i=@strongswan.org header.b="GawDM/DO" Received: from localhost (localhost [127.0.0.1]) by mail.codelabs.ch (Postfix) with ESMTP id 50E4F5A0001; Wed, 17 Jul 2024 11:08:45 +0200 (CEST) Received: from mail.codelabs.ch ([127.0.0.1]) by localhost (fenrir.codelabs.ch [127.0.0.1]) (amavis, port 10024) with ESMTP id dkFK9lWPNmfj; Wed, 17 Jul 2024 11:08:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=strongswan.org; s=default; t=1721207323; bh=N42cqY0I8yT6ZfvI+LElwDnJf0ppkaP3hiNRDj9hcFY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GawDM/DOxjnPF3LkO8t32e2cK+TK5/9P+miE50q22aKXj+/KoOfrr97uXYptYEsXM fMNe5OUBUFdLhs7n5soRaZnEJFdteYpFlTa8OfKpgD76EDQV/kIsaATh+IF8O9jSVM ezXiDbs/8tkIb0hIqer4ydU7xKZQH17VDyFYHS1BeR91WiF0EPe4gZhVem3OcLpL6W eRFh09kjoY0uNF8yc2FK1NfqNx/3fh+lD9fjzZDuMNC8gPhVMSz+4qDCSX7oviDiaI lKa/PWleDLXvV/tmgvOxlKgZnEOBjG1hB9UF5K9zDihBM4/Dy6bzmasT9mjWb4c2nI RGRG2LZqWLMpQ== Received: from think.home (unknown [185.12.128.224]) by mail.codelabs.ch (Postfix) with ESMTPSA id 655075A0003; Wed, 17 Jul 2024 11:08:43 +0200 (CEST) From: Martin Willi To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , Chris Packham , Murali Krishna Policharla Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: [PATCH net v2 2/2] net: dsa: b53: Limit chip-wide jumbo frame config to CPU ports Date: Wed, 17 Jul 2024 11:08:20 +0200 Message-ID: <20240717090820.894234-3-martin@strongswan.org> In-Reply-To: <20240717090820.894234-1-martin@strongswan.org> References: <20240717090820.894234-1-martin@strongswan.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Broadcom switches supported by the b53 driver use a chip-wide jumbo frame configuration. In the commit referenced with the Fixes tag, the setting is applied just for the last port changing its MTU. While configuring CPU ports accounts for tagger overhead, user ports do not. When setting the MTU for a user port, the chip-wide setting is reduced to not include the tagger overhead, resulting in an potentially insufficient chip-wide maximum frame size for the CPU port. As, by design, the CPU port MTU is adjusted for any user port change, apply the chip-wide setting only for CPU ports. This aligns the driver to the behavior of other switch drivers. Fixes: 6ae5834b983a ("net: dsa: b53: add MTU configuration support") Suggested-by: Vladimir Oltean Signed-off-by: Martin Willi Reviewed-by: Vladimir Oltean --- drivers/net/dsa/b53/b53_common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c index 8f50abe739b7..0783fc121bbb 100644 --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c @@ -2256,6 +2256,9 @@ static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) if (is5325(dev) || is5365(dev)) return -EOPNOTSUPP; + if (!dsa_is_cpu_port(ds, port)) + return 0; + enable_jumbo = (mtu >= JMS_MIN_SIZE); allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);