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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:55:32.0321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20a0af0b-7367-4c65-d1c8-08dca6a2cc3f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6758 Implement the framework for PCIe TPH support by introducing tph.c source file, along with CONFIG_PCIE_TPH, to Linux PCIe subsystem. Add tph_cap in pci_dev to cache TPH capability offset. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek Reviewed-by: Jonathan Cameron --- drivers/pci/pci.h | 6 ++++++ drivers/pci/pcie/Kconfig | 11 +++++++++++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/tph.c | 15 +++++++++++++++ drivers/pci/probe.c | 1 + include/linux/pci.h | 4 ++++ 6 files changed, 38 insertions(+) create mode 100644 drivers/pci/pcie/tph.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 79c8398f3938..b80342e6b3e8 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -571,6 +571,12 @@ static inline int pci_iov_bus_range(struct pci_bus *bus) #endif /* CONFIG_PCI_IOV */ +#ifdef CONFIG_PCIE_TPH +void pcie_tph_init(struct pci_dev *dev); +#else +static inline void pcie_tph_init(struct pci_dev *dev) {} +#endif + #ifdef CONFIG_PCIE_PTM void pci_ptm_init(struct pci_dev *dev); void pci_save_ptm_state(struct pci_dev *dev); diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 17919b99fa66..c765016a119a 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -155,3 +155,14 @@ config PCIE_EDR the PCI Firmware Specification r3.2. Enable this if you want to support hybrid DPC model which uses both firmware and OS to implement DPC. + +config PCIE_TPH + bool "TLP Processing Hints" + depends on ACPI + default n + help + This option adds support for PCIe TLP Processing Hints (TPH). + TPH allows endpoint devices to provide optimization hints, such as + desired caching behavior, for requests that target memory space. + These hints, called steering tags, can empower the system hardware + to optimize the utilization of platform resources. diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 6461aa93fe76..3542b42ea0b9 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_PME) += pme.o obj-$(CONFIG_PCIE_DPC) += dpc.o obj-$(CONFIG_PCIE_PTM) += ptm.o obj-$(CONFIG_PCIE_EDR) += edr.o +obj-$(CONFIG_PCIE_TPH) += tph.o diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c new file mode 100644 index 000000000000..e385b871333e --- /dev/null +++ b/drivers/pci/pcie/tph.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TPH (TLP Processing Hints) support + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + * Eric Van Tassell + * Wei Huang + */ + +#include "../pci.h" + +void pcie_tph_init(struct pci_dev *pdev) +{ + pdev->tph_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_TPH); +} diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 20475ca30505..b6bf3559c204 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2498,6 +2498,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_dpc_init(dev); /* Downstream Port Containment */ pci_rcec_init(dev); /* Root Complex Event Collector */ pci_doe_init(dev); /* Data Object Exchange */ + pcie_tph_init(dev); /* TLP Processing Hints */ pcie_report_downtraining(dev); pci_init_reset_methods(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index e83ac93a4dcb..6631ebe80ca9 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -532,6 +532,10 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ + +#ifdef CONFIG_PCIE_TPH + u16 tph_cap; /* TPH capability offset */ +#endif }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev) From patchwork Wed Jul 17 20:55:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 13735758 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2065.outbound.protection.outlook.com [40.107.223.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F22718733B; 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Wed, 17 Jul 2024 15:55:45 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 02/10] PCI: Add TPH related register definition Date: Wed, 17 Jul 2024 15:55:03 -0500 Message-ID: <20240717205511.2541693-3-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240717205511.2541693-1-wei.huang2@amd.com> References: <20240717205511.2541693-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3C:EE_|SN7PR12MB8790:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b4d2603-76ff-492c-aded-08dca6a2d534 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|82310400026|376014; X-Microsoft-Antispam-Message-Info: hB9Z8+O4OzlVOLdFg2Aa7UP96iNG/zMY6fDz+bPrybCwQOaIH0YjA1zG8KPxl76pMtaibPn4tKAd1xeEV9tKQYuRxfXOef2FX8v7WhF5KVE0eh8oftkKoT1kXEIcDKnceZO7Y7kVBk+44UssFHVYHWcMEbL8O35fi0MM032MQ76tZj5P6JWWob1AJeCec0CYMBDptOd21uTZBoJNvzIn919My+1Rd4cVgDp0lrlt5NyjbY5kgvbO39rNhPAHbE5jdYqdVim1OdEBr6/d0nsWrZ9Gjjzh5ACdLvAQYMnCcPKASbbbO+Bs1DWgwdx4HZB7fdiF/RrpTwuhUoES1q6pSUKLDdjOjOmQy6YqMcoOdLLSnI5dxfkQFLwDzkxJwTdCVllGfhI8eP16rP7woCRGgX1K0Oh6sVZrkEJS7QUJhajStwiLlKUihRL1u9b/X3fgQivvEFpKRf8MauY5cYNi8Js1Y5vwS6WDgd8cCVfnQ6PAzTQXLsqrAqOZlBIJ7Xs8T+aoZXepOpq3hfzn/c255Bhp9yBf0uLescn3aF4E/3ZaqKJZeAP2B/EuB+WB5ZWXctLzzO8fmwSIFBrcv/wZe5vkj2Ljqt0dQROqaRbv0lQ+AjUqdtjxMIFRlpUZYxoNO1GFjxgWXeyDKcgdbhwyYZFZe2BrPx8osAj14JFJOMmPhZ4hiqb7kwWC1/8SKy15E3Xu0ZHea3YEdY6rhOh0gheDIIOKAllD+QjsUYn8kwVSs7AVzPmLrviZhwxdDrsB0cpBfZaZVqkBinxjLBvslYNoIAdnzC3FHNCBwg0OS9cDSVDWnBTsNFEij8jeNB+vRkwWRi7elwLGQl1lPk+wmNL/1lWp3wrlQV5ZD96pm8e+Q2JJRjQYpfCCPGAyxFISJGG+o7YQRCm2ZTmflOfsUpSfIDJ5DpiD7g63gCtnlNaBHRiQWGQ4WdcGURuUixZi/zb0VUXJTxoXbbQ20HQ17Uerm3dUgcyfNLyCaeOVrE85ujzDMeM99UK2TLZtit3ovLP4LYMLK649yS5EHmrrZnezuLM6IJyeKoi89ZT9N+us87aU6jGVOEiZwjOhMyGRAl65iQ/I9BxBQdRiBK9FbFEZcVfj5yU+AhyUHBofLYRe2iEKWxRcdvWy00ljj59ZqrFFiO7bYS/xal2wiGvx5z5W/CxczzOXGi1sq7hPEHO8y0V7iRWieAsq7Lb6C8V4GYecBwPUsuQV+XAQrP197XYJZzG7rNsmdd5q6JE8DtUP7aPcnDi6t21sDTFgIHyOaGtvFvjn9xABoKy2ZS9l9E4jeru+zzkw0JqSEU65bI615dtepQD+VJom0wqr3t43xte/HQQ42WuHTydFt7jwZgIbIrTGMlEE0ecv9icFqQOkIi7xzBuZwKG5dJKJ5f4ixihU2kXNMa+FAeCDgHKAi4ju0x2+UIQkVaS/fRzA9qSmndCcAXC1QW3likByNOdE X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(82310400026)(376014);DIR:OUT;SFP:1101; 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Also the control registers of TPH Requester and the TPH Completer are missing. Add all required definitions to support TPH without changing the existing uapi. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- include/uapi/linux/pci_regs.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 94c00996e633..0fb61af6097a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -657,6 +657,7 @@ #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ +#define PCI_EXP_DEVCAP2_TPH_COMP_MASK 0x00003000 /* TPH completer support */ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ @@ -1020,16 +1021,35 @@ #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ +/* TPH Completer Support */ +#define PCI_EXP_DEVCAP2_TPH_COMP_NONE 0x0 /* None */ +#define PCI_EXP_DEVCAP2_TPH_COMP_TPH_ONLY 0x1 /* TPH only */ +#define PCI_EXP_DEVCAP2_TPH_COMP_TPH_AND_EXT 0x3 /* TPH and Extended TPH */ + /* TPH Requester */ #define PCI_TPH_CAP 4 /* capability register */ -#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ -#define PCI_TPH_LOC_NONE 0x000 /* no location */ -#define PCI_TPH_LOC_CAP 0x200 /* in capability */ -#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ +#define PCI_TPH_CAP_NO_ST 0x00000001 /* no ST mode supported */ +#define PCI_TPH_CAP_INT_VEC 0x00000002 /* interrupt vector mode supported */ +#define PCI_TPH_CAP_DS 0x00000004 /* device specific mode supported */ +#define PCI_TPH_CAP_EXT_TPH 0x00000100 /* extended TPH requestor supported */ +#define PCI_TPH_CAP_LOC_MASK 0x00000600 /* location mask */ +#define PCI_TPH_LOC_NONE 0x00000000 /* no location */ +#define PCI_TPH_LOC_CAP 0x00000200 /* in capability */ +#define PCI_TPH_LOC_MSIX 0x00000400 /* in MSI-X */ #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST table mask */ #define PCI_TPH_CAP_ST_SHIFT 16 /* ST table shift */ #define PCI_TPH_BASE_SIZEOF 0xc /* size with no ST table */ +#define PCI_TPH_CTRL 8 /* control register */ +#define PCI_TPH_CTRL_MODE_SEL_MASK 0x00000007 /* ST mode select mask */ +#define PCI_TPH_NO_ST_MODE 0x0 /* no ST mode */ +#define PCI_TPH_INT_VEC_MODE 0x1 /* interrupt vector mode */ +#define PCI_TPH_DEV_SPEC_MODE 0x2 /* device specific mode */ +#define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH requester mask */ +#define PCI_TPH_REQ_DISABLE 0x0 /* no TPH request allowed */ +#define PCI_TPH_REQ_TPH_ONLY 0x1 /* 8-bit TPH tags allowed */ +#define PCI_TPH_REQ_EXT_TPH 0x3 /* 16-bit TPH tags allowed */ + /* Downstream Port Containment */ #define PCI_EXP_DPC_CAP 0x04 /* DPC Capability */ #define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */ From patchwork Wed Jul 17 20:55:04 2024 Content-Type: text/plain; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Wed, 17 Jul 2024 20:55:58 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 17 Jul 2024 15:55:57 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 03/10] PCI/TPH: Add pci=notph to prevent use of TPH Date: Wed, 17 Jul 2024 15:55:04 -0500 Message-ID: <20240717205511.2541693-4-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240717205511.2541693-1-wei.huang2@amd.com> References: <20240717205511.2541693-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|SJ2PR12MB7865:EE_ X-MS-Office365-Filtering-Correlation-Id: db3faf63-9371-4892-425d-08dca6a2dc39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:55:58.8170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db3faf63-9371-4892-425d-08dca6a2dc39 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7865 TLP headers with incorrect steering tags (e.g. caused by buggy driver) can potentially cause issues when the system hardware consumes the tags. Provide a kernel option, with related helper functions, to completely prevent TPH from being enabled. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- .../admin-guide/kernel-parameters.txt | 1 + drivers/pci/pci-driver.c | 7 +++++- drivers/pci/pci.c | 12 +++++++++ drivers/pci/pcie/tph.c | 25 +++++++++++++++++++ include/linux/pci-tph.h | 18 +++++++++++++ include/linux/pci.h | 1 + 6 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 include/linux/pci-tph.h diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index b2057241ea6c..65581ebd9b50 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4655,6 +4655,7 @@ nomio [S390] Do not use MIO instructions. norid [S390] ignore the RID field and force use of one PCI domain per PCI function + notph [PCIE] Do not use PCIe TPH pcie_aspm= [PCIE] Forcibly enable or ignore PCIe Active State Power Management. diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index af2996d0d17f..9722d070c0ca 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "pci.h" #include "pcie/portdrv.h" @@ -322,8 +323,12 @@ static long local_pci_probe(void *_ddi) pm_runtime_get_sync(dev); pci_dev->driver = pci_drv; rc = pci_drv->probe(pci_dev, ddi->id); - if (!rc) + if (!rc) { + if (pci_tph_disabled()) + pcie_tph_disable(pci_dev); + return rc; + } if (rc < 0) { pci_dev->driver = NULL; pm_runtime_put_sync(dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 02b1d81b1419..4cbfd5b53be8 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -157,6 +157,9 @@ static bool pcie_ari_disabled; /* If set, the PCIe ATS capability will not be used. */ static bool pcie_ats_disabled; +/* If set, the PCIe TPH capability will not be used. */ +static bool pcie_tph_disabled; + /* If set, the PCI config space of each device is printed during boot. */ bool pci_early_dump; @@ -166,6 +169,12 @@ bool pci_ats_disabled(void) } EXPORT_SYMBOL_GPL(pci_ats_disabled); +bool pci_tph_disabled(void) +{ + return pcie_tph_disabled; +} +EXPORT_SYMBOL_GPL(pci_tph_disabled); + /* Disable bridge_d3 for all PCIe ports */ static bool pci_bridge_d3_disable; /* Force bridge_d3 for all PCIe ports */ @@ -6869,6 +6878,9 @@ static int __init pci_setup(char *str) pci_no_domains(); } else if (!strncmp(str, "noari", 5)) { pcie_ari_disabled = true; + } else if (!strcmp(str, "notph")) { + pr_info("PCIe: TPH is disabled\n"); + pcie_tph_disabled = true; } else if (!strncmp(str, "cbiosize=", 9)) { pci_cardbus_io_size = memparse(str + 9, &str); } else if (!strncmp(str, "cbmemsize=", 10)) { diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index e385b871333e..ad58a892792c 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -7,8 +7,33 @@ * Wei Huang */ +#include +#include +#include + #include "../pci.h" +/* Update the TPH Requester Enable field of TPH Control Register */ +static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type) +{ + u32 reg_val; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®_val); + + reg_val &= ~PCI_TPH_CTRL_REQ_EN_MASK; + reg_val |= FIELD_PREP(PCI_TPH_CTRL_REQ_EN_MASK, req_type); + + pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg_val); +} + +void pcie_tph_disable(struct pci_dev *pdev) +{ + if (!pdev->tph_cap) + return; + + set_ctrl_reg_req_en(pdev, PCI_TPH_REQ_DISABLE); +} + void pcie_tph_init(struct pci_dev *pdev) { pdev->tph_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_TPH); diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h new file mode 100644 index 000000000000..e0b782bda929 --- /dev/null +++ b/include/linux/pci-tph.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TPH (TLP Processing Hints) + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + * Eric Van Tassell + * Wei Huang + */ +#ifndef LINUX_PCI_TPH_H +#define LINUX_PCI_TPH_H + +#ifdef CONFIG_PCIE_TPH +void pcie_tph_disable(struct pci_dev *dev); +#else +static inline void pcie_tph_disable(struct pci_dev *dev) {} +#endif + +#endif /* LINUX_PCI_TPH_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 6631ebe80ca9..05fbbd9ad6b4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1840,6 +1840,7 @@ static inline bool pci_aer_available(void) { return false; } #endif bool pci_ats_disabled(void); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:56:10.1030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 055d737e-b403-415d-83c6-08dca6a2e2fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9135 When "No ST mode" is enabled, endpoint devices can generate TPH headers but with all steering tags treated as zero. A steering tag of zero is interpreted as "using the default policy" by the root complex. This is essential to quantify the benefit of steering tags for some given workloads. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- .../admin-guide/kernel-parameters.txt | 1 + drivers/pci/pci-driver.c | 7 +++++- drivers/pci/pci.c | 12 ++++++++++ drivers/pci/pcie/tph.c | 22 +++++++++++++++++++ include/linux/pci-tph.h | 2 ++ include/linux/pci.h | 1 + 6 files changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 65581ebd9b50..1b761f062969 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4656,6 +4656,7 @@ norid [S390] ignore the RID field and force use of one PCI domain per PCI function notph [PCIE] Do not use PCIe TPH + nostmode [PCIE] Force TPH to use No ST Mode pcie_aspm= [PCIE] Forcibly enable or ignore PCIe Active State Power Management. diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 9722d070c0ca..abe66541536e 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -324,8 +324,13 @@ static long local_pci_probe(void *_ddi) pci_dev->driver = pci_drv; rc = pci_drv->probe(pci_dev, ddi->id); if (!rc) { - if (pci_tph_disabled()) + if (pci_tph_disabled()) { pcie_tph_disable(pci_dev); + return rc; + } + + if (pci_tph_nostmode()) + pcie_tph_set_nostmode(pci_dev); return rc; } diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4cbfd5b53be8..8745ce1c4a9a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -160,6 +160,9 @@ static bool pcie_ats_disabled; /* If set, the PCIe TPH capability will not be used. */ static bool pcie_tph_disabled; +/* If TPH is enabled, "No ST Mode" will be enforced. */ +static bool pcie_tph_nostmode; + /* If set, the PCI config space of each device is printed during boot. */ bool pci_early_dump; @@ -175,6 +178,12 @@ bool pci_tph_disabled(void) } EXPORT_SYMBOL_GPL(pci_tph_disabled); +bool pci_tph_nostmode(void) +{ + return pcie_tph_nostmode; +} +EXPORT_SYMBOL_GPL(pci_tph_nostmode); + /* Disable bridge_d3 for all PCIe ports */ static bool pci_bridge_d3_disable; /* Force bridge_d3 for all PCIe ports */ @@ -6881,6 +6890,9 @@ static int __init pci_setup(char *str) } else if (!strcmp(str, "notph")) { pr_info("PCIe: TPH is disabled\n"); pcie_tph_disabled = true; + } else if (!strcmp(str, "nostmode")) { + pr_info("PCIe: TPH No ST Mode is enabled\n"); + pcie_tph_nostmode = true; } else if (!strncmp(str, "cbiosize=", 9)) { pci_cardbus_io_size = memparse(str + 9, &str); } else if (!strncmp(str, "cbmemsize=", 10)) { diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index ad58a892792c..fb8e2f920712 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -13,6 +13,19 @@ #include "../pci.h" +/* Update the ST Mode Select field of TPH Control Register */ +static void set_ctrl_reg_mode_sel(struct pci_dev *pdev, u8 st_mode) +{ + u32 reg_val; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®_val); + + reg_val &= ~PCI_TPH_CTRL_MODE_SEL_MASK; + reg_val |= FIELD_PREP(PCI_TPH_CTRL_MODE_SEL_MASK, st_mode); + + pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg_val); +} + /* Update the TPH Requester Enable field of TPH Control Register */ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type) { @@ -26,6 +39,15 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type) pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg_val); } +void pcie_tph_set_nostmode(struct pci_dev *pdev) +{ + if (!pdev->tph_cap) + return; + + set_ctrl_reg_mode_sel(pdev, PCI_TPH_NO_ST_MODE); + set_ctrl_reg_req_en(pdev, PCI_TPH_REQ_TPH_ONLY); +} + void pcie_tph_disable(struct pci_dev *pdev) { if (!pdev->tph_cap) diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index e0b782bda929..8fce3969277c 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -11,8 +11,10 @@ #ifdef CONFIG_PCIE_TPH void pcie_tph_disable(struct pci_dev *dev); +void pcie_tph_set_nostmode(struct pci_dev *dev); #else static inline void pcie_tph_disable(struct pci_dev *dev) {} +static inline void pcie_tph_set_nostmode(struct pci_dev *dev) {} #endif #endif /* LINUX_PCI_TPH_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 05fbbd9ad6b4..ac58f3919993 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1841,6 +1841,7 @@ static inline bool pci_aer_available(void) { return false; } bool pci_ats_disabled(void); bool pci_tph_disabled(void); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:56:21.4646 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be7c329f-4c54-4728-c56e-08dca6a2e9bd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7719 Add an API function to allow endpoint device drivers to check if the interrupt vector mode is allowed. If allowed, drivers can proceed with updating ST tags. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- drivers/pci/pcie/tph.c | 29 +++++++++++++++++++++++++++++ include/linux/pci-tph.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index fb8e2f920712..7183370b0977 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -39,6 +39,17 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type) pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg_val); } +static bool int_vec_mode_supported(struct pci_dev *pdev) +{ + u32 reg_val; + u8 mode; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®_val); + mode = FIELD_GET(PCI_TPH_CAP_INT_VEC, reg_val); + + return !!mode; +} + void pcie_tph_set_nostmode(struct pci_dev *pdev) { if (!pdev->tph_cap) @@ -60,3 +71,21 @@ void pcie_tph_init(struct pci_dev *pdev) { pdev->tph_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_TPH); } + +/** + * pcie_tph_intr_vec_supported() - Check if interrupt vector mode supported for dev + * @pdev: pci device + * + * Return: + * true : intr vector mode supported + * false: intr vector mode not supported + */ +bool pcie_tph_intr_vec_supported(struct pci_dev *pdev) +{ + if (!pdev->tph_cap || pci_tph_disabled() || !pdev->msix_enabled || + !int_vec_mode_supported(pdev)) + return false; + + return true; +} +EXPORT_SYMBOL(pcie_tph_intr_vec_supported); diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index 8fce3969277c..854677651d81 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -12,9 +12,12 @@ #ifdef CONFIG_PCIE_TPH void pcie_tph_disable(struct pci_dev *dev); void pcie_tph_set_nostmode(struct pci_dev *dev); +bool pcie_tph_intr_vec_supported(struct pci_dev *dev); #else static inline void pcie_tph_disable(struct pci_dev *dev) {} static inline void pcie_tph_set_nostmode(struct pci_dev *dev) {} +static inline bool pcie_tph_intr_vec_supported(struct pci_dev *dev) +{ return false; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:56:32.9265 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67aa6001-74b3-4723-f5a8-08dca6a2f08d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4140 Add an API function to allow endpoint device drivers to retrieve steering tags for a specific cpu_uid. This is achieved by invoking ACPI _DSM on device's root port. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- drivers/pci/pcie/tph.c | 162 ++++++++++++++++++++++++++++++++++++++++ include/linux/pci-tph.h | 12 +++ 2 files changed, 174 insertions(+) diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index 7183370b0977..c805c8b1a7d2 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -7,12 +7,133 @@ * Wei Huang */ +#define pr_fmt(fmt) "TPH: " fmt +#define dev_fmt pr_fmt + #include +#include #include #include #include "../pci.h" +/* + * The st_info struct defines the steering tag returned by the firmware _DSM + * method defined in PCI Firmware Spec r3.3, sect 4.6.15 "_DSM to Query Cache + * Locality TPH Features" + * + * @vm_st_valid: 8 bit tag for volatile memory is valid + * @vm_xst_valid: 16 bit tag for volatile memory is valid + * @vm_ignore: 1 => was and will be ignored, 0 => ph should be supplied + * @vm_st: 8 bit steering tag for volatile mem + * @vm_xst: 16 bit steering tag for volatile mem + * @pm_st_valid: 8 bit tag for persistent memory is valid + * @pm_xst_valid: 16 bit tag for persistent memory is valid + * @pm_ph_ignore: 1 => was and will be ignore, 0 => ph should be supplied + * @pm_st: 8 bit steering tag for persistent mem + * @pm_xst: 16 bit steering tag for persistent mem + */ +union st_info { + struct { + u64 vm_st_valid : 1; + u64 vm_xst_valid : 1; + u64 vm_ph_ignore : 1; + u64 rsvd1 : 5; + u64 vm_st : 8; + u64 vm_xst : 16; + u64 pm_st_valid : 1; + u64 pm_xst_valid : 1; + u64 pm_ph_ignore : 1; + u64 rsvd2 : 5; + u64 pm_st : 8; + u64 pm_xst : 16; + }; + u64 value; +}; + +static u16 tph_extract_tag(enum tph_mem_type mem_type, u8 req_type, + union st_info *st_tag) +{ + switch (req_type) { + case PCI_TPH_REQ_TPH_ONLY: /* 8 bit tags */ + switch (mem_type) { + case TPH_MEM_TYPE_VM: + if (st_tag->vm_st_valid) + return st_tag->vm_st; + break; + case TPH_MEM_TYPE_PM: + if (st_tag->pm_st_valid) + return st_tag->pm_st; + break; + } + break; + case PCI_TPH_REQ_EXT_TPH: /* 16 bit tags */ + switch (mem_type) { + case TPH_MEM_TYPE_VM: + if (st_tag->vm_xst_valid) + return st_tag->vm_xst; + break; + case TPH_MEM_TYPE_PM: + if (st_tag->pm_xst_valid) + return st_tag->pm_xst; + break; + } + break; + default: + pr_err("invalid steering tag in ACPI _DSM\n"); + return 0; + } + + return 0; +} + +#define TPH_ST_DSM_FUNC_INDEX 0xF +static acpi_status tph_invoke_dsm(acpi_handle handle, u32 cpu_uid, u8 ph, + u8 target_type, bool cache_ref_valid, + u64 cache_ref, union st_info *st_out) +{ + union acpi_object arg3[3], in_obj, *out_obj; + + if (!acpi_check_dsm(handle, &pci_acpi_dsm_guid, 7, BIT(TPH_ST_DSM_FUNC_INDEX))) + return AE_ERROR; + + /* DWORD: feature ID (0 for processor cache ST query) */ + arg3[0].integer.type = ACPI_TYPE_INTEGER; + arg3[0].integer.value = 0; + + /* DWORD: target UID */ + arg3[1].integer.type = ACPI_TYPE_INTEGER; + arg3[1].integer.value = cpu_uid; + + /* QWORD: properties */ + arg3[2].integer.type = ACPI_TYPE_INTEGER; + arg3[2].integer.value = ph & 3; + arg3[2].integer.value |= (target_type & 1) << 2; + arg3[2].integer.value |= (cache_ref_valid & 1) << 3; + arg3[2].integer.value |= (cache_ref << 32); + + in_obj.type = ACPI_TYPE_PACKAGE; + in_obj.package.count = ARRAY_SIZE(arg3); + in_obj.package.elements = arg3; + + out_obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 7, + TPH_ST_DSM_FUNC_INDEX, &in_obj); + + if (!out_obj) + return AE_ERROR; + + if (out_obj->type != ACPI_TYPE_BUFFER) { + ACPI_FREE(out_obj); + return AE_ERROR; + } + + st_out->value = *((u64 *)(out_obj->buffer.pointer)); + + ACPI_FREE(out_obj); + + return AE_OK; +} + /* Update the ST Mode Select field of TPH Control Register */ static void set_ctrl_reg_mode_sel(struct pci_dev *pdev, u8 st_mode) { @@ -89,3 +210,44 @@ bool pcie_tph_intr_vec_supported(struct pci_dev *pdev) return true; } EXPORT_SYMBOL(pcie_tph_intr_vec_supported); + +/** + * pcie_tph_get_st_from_acpi() - Retrieve steering tag for a specific CPU + * using platform ACPI _DSM + * @pdev: pci device + * @cpu_acpi_uid: the acpi cpu_uid. + * @mem_type: memory type (vram, nvram) + * @req_type: request type (disable, tph, extended tph) + * @tag: steering tag return value + * + * Return: 0 if success, otherwise errno + */ +int pcie_tph_get_st_from_acpi(struct pci_dev *pdev, unsigned int cpu_acpi_uid, + enum tph_mem_type mem_type, u8 req_type, + u16 *tag) +{ + struct pci_dev *rp; + acpi_handle rp_acpi_handle; + union st_info info; + + if (!pdev->tph_cap) + return -ENODEV; + + /* find ACPI handler for device's root port */ + rp = pcie_find_root_port(pdev); + if (!rp || !rp->bus || !rp->bus->bridge) + return -ENODEV; + rp_acpi_handle = ACPI_HANDLE(rp->bus->bridge); + + /* invoke _DSM to extract tag value */ + if (tph_invoke_dsm(rp_acpi_handle, cpu_acpi_uid, 0, 0, false, 0, &info) != AE_OK) { + *tag = 0; + return -EINVAL; + } + + *tag = tph_extract_tag(mem_type, req_type, &info); + pci_dbg(pdev, "%s: cpu=%d tag=%d\n", __func__, cpu_acpi_uid, *tag); + + return 0; +} +EXPORT_SYMBOL(pcie_tph_get_st_from_acpi); diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index 854677651d81..b12a592f3d49 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -9,15 +9,27 @@ #ifndef LINUX_PCI_TPH_H #define LINUX_PCI_TPH_H +enum tph_mem_type { + TPH_MEM_TYPE_VM, /* volatile memory type */ + TPH_MEM_TYPE_PM /* persistent memory type */ +}; + #ifdef CONFIG_PCIE_TPH void pcie_tph_disable(struct pci_dev *dev); void pcie_tph_set_nostmode(struct pci_dev *dev); bool pcie_tph_intr_vec_supported(struct pci_dev *dev); +int pcie_tph_get_st_from_acpi(struct pci_dev *dev, unsigned int cpu_acpi_uid, + enum tph_mem_type tag_type, u8 req_enable, + u16 *tag); #else static inline void pcie_tph_disable(struct pci_dev *dev) {} static inline void pcie_tph_set_nostmode(struct pci_dev *dev) {} static inline bool pcie_tph_intr_vec_supported(struct pci_dev *dev) { return false; } +static inline int pcie_tph_get_st_from_acpi(struct pci_dev *dev, unsigned int cpu_acpi_uid, + enum tph_mem_type tag_type, u8 req_enable, + u16 *tag) +{ return false; } #endif #endif /* LINUX_PCI_TPH_H */ From patchwork Wed Jul 17 20:55:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 13735763 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2084.outbound.protection.outlook.com [40.107.244.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A5CE186E3A; Wed, 17 Jul 2024 20:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 17 Jul 2024 15:56:42 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 07/10] PCI/TPH: Introduce API to update TPH steering tags in PCIe devices Date: Wed, 17 Jul 2024 15:55:08 -0500 Message-ID: <20240717205511.2541693-8-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240717205511.2541693-1-wei.huang2@amd.com> References: <20240717205511.2541693-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE39:EE_|SJ2PR12MB7944:EE_ X-MS-Office365-Filtering-Correlation-Id: c4b55367-5aff-447a-2ac4-08dca6a2f76c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:56:44.4491 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4b55367-5aff-447a-2ac4-08dca6a2f76c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE39.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7944 Add an API function, pcie_tph_set_st(), to allow endpoint device driver to update the steering tags. Depending on ST table location, the tags will be written into device's MSI-X table or TPH Requester Extended Capability structure. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- drivers/pci/pcie/tph.c | 190 ++++++++++++++++++++++++++++++++++++++++ include/linux/pci-tph.h | 7 ++ 2 files changed, 197 insertions(+) diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index c805c8b1a7d2..8a0e48c913cf 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -171,6 +172,160 @@ static bool int_vec_mode_supported(struct pci_dev *pdev) return !!mode; } +static u32 get_st_table_loc(struct pci_dev *pdev) +{ + u32 reg_val; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®_val); + + return FIELD_GET(PCI_TPH_CAP_LOC_MASK, reg_val); +} + +static bool msix_index_in_bound(struct pci_dev *pdev, int msi_idx) +{ + u32 reg_val; + u16 st_tbl_sz; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®_val); + st_tbl_sz = FIELD_GET(PCI_TPH_CAP_ST_MASK, reg_val); + + return msi_idx <= st_tbl_sz; +} + +/* Write ST to MSI-X vector control reg - Return 0 if OK, otherwise errno */ +static int tph_write_tag_to_msix(struct pci_dev *pdev, int msi_idx, u16 tag) +{ + struct msi_desc *msi_desc = NULL; + void __iomem *vec_ctrl; + u32 val; + int err = 0; + + if (!msix_index_in_bound(pdev, msi_idx)) + return -EINVAL; + + msi_lock_descs(&pdev->dev); + + /* find the msi_desc entry with matching msi_idx */ + msi_for_each_desc(msi_desc, &pdev->dev, MSI_DESC_ASSOCIATED) { + if (msi_desc->msi_index == msi_idx) + break; + } + + if (!msi_desc) { + pci_err(pdev, "MSI-X descriptor for #%d not found\n", msi_idx); + err = -ENXIO; + goto err_out; + } + + /* get the vector control register (offset 0xc) pointed by msi_idx */ + vec_ctrl = pdev->msix_base + msi_idx * PCI_MSIX_ENTRY_SIZE; + vec_ctrl += PCI_MSIX_ENTRY_VECTOR_CTRL; + + val = readl(vec_ctrl); + val &= 0xffff; + val |= (tag << 16); + writel(val, vec_ctrl); + + /* read back to flush the update */ + val = readl(vec_ctrl); + +err_out: + msi_unlock_descs(&pdev->dev); + return err; +} + +/* Return root port TPH completer capability - 0 means none */ +static u8 get_rp_completer_support(struct pci_dev *pdev) +{ + struct pci_dev *rp; + u32 reg_val; + int ret; + + rp = pcie_find_root_port(pdev); + if (!rp) { + pci_err(pdev, "cannot find root port of %s\n", dev_name(&pdev->dev)); + return 0; + } + + ret = pcie_capability_read_dword(rp, PCI_EXP_DEVCAP2, ®_val); + if (ret) { + pci_err(pdev, "cannot read device capabilities 2\n"); + return 0; + } + + return FIELD_GET(PCI_EXP_DEVCAP2_TPH_COMP_MASK, reg_val); +} + +/* + * TPH device needs to be below a rootport with the TPH Completer and + * the completer must offer a compatible level of completer support to that + * requested by the device driver. + */ +static bool rp_completer_support_ok(struct pci_dev *pdev, u8 req_cap) +{ + u8 rp_cap; + + rp_cap = get_rp_completer_support(pdev); + + if (req_cap > rp_cap) { + pci_err(pdev, "root port lacks proper TPH completer capability\n"); + return false; + } + + return true; +} + +/* Return 0 if OK, otherwise errno on failure */ +static int pcie_tph_write_st(struct pci_dev *pdev, unsigned int msix_idx, + u8 req_type, u16 tag) +{ + int offset; + u32 loc; + int err = 0; + + /* setting ST isn't needed - not an error, just return OK */ + if (!pdev->tph_cap || pci_tph_disabled() || pci_tph_nostmode() || + !pdev->msix_enabled || !int_vec_mode_supported(pdev)) + return 0; + + /* setting ST is incorrect in the following cases - return error */ + if (!msix_index_in_bound(pdev, msix_idx) || !rp_completer_support_ok(pdev, req_type)) + return -EINVAL; + + /* + * disable TPH before updating the tag to avoid potential instability + * as cautioned in PCIE Base Spec r6.2, sect 6.17.3 "ST Modes of Operation" + */ + pcie_tph_disable(pdev); + + loc = get_st_table_loc(pdev); + /* Note: use FIELD_PREP to match PCI_TPH_LOC_* definitions in header */ + loc = FIELD_PREP(PCI_TPH_CAP_LOC_MASK, loc); + + switch (loc) { + case PCI_TPH_LOC_MSIX: + err = tph_write_tag_to_msix(pdev, msix_idx, tag); + break; + case PCI_TPH_LOC_CAP: + offset = pdev->tph_cap + PCI_TPH_BASE_SIZEOF + msix_idx * sizeof(u16); + err = pci_write_config_word(pdev, offset, tag); + break; + default: + pci_err(pdev, "unable to write steering tag for device %s\n", + dev_name(&pdev->dev)); + err = -EINVAL; + break; + } + + if (!err) { + /* re-enable interrupt vector mode */ + set_ctrl_reg_mode_sel(pdev, PCI_TPH_INT_VEC_MODE); + set_ctrl_reg_req_en(pdev, req_type); + } + + return err; +} + void pcie_tph_set_nostmode(struct pci_dev *pdev) { if (!pdev->tph_cap) @@ -251,3 +406,38 @@ int pcie_tph_get_st_from_acpi(struct pci_dev *pdev, unsigned int cpu_acpi_uid, return 0; } EXPORT_SYMBOL(pcie_tph_get_st_from_acpi); + +/** + * pcie_tph_set_st() - Set steering tag in ST table entry + * @pdev: pci device + * @msix_idx: ordinal number of msix interrupt. + * @cpu_acpi_uid: the acpi cpu_uid. + * @mem_type: memory type (vram, nvram) + * @req_type: request type (disable, tph, extended tph) + * + * Return: 0 if success, otherwise errno + */ +int pcie_tph_set_st(struct pci_dev *pdev, unsigned int msix_idx, + unsigned int cpu_acpi_uid, enum tph_mem_type mem_type, + u8 req_type) +{ + u16 tag; + int err = 0; + + if (!pdev->tph_cap) + return -ENODEV; + + err = pcie_tph_get_st_from_acpi(pdev, cpu_acpi_uid, mem_type, + req_type, &tag); + + if (err) + return err; + + pci_dbg(pdev, "%s: writing tag %d for msi-x intr %d (cpu: %d)\n", + __func__, tag, msix_idx, cpu_acpi_uid); + + err = pcie_tph_write_st(pdev, msix_idx, req_type, tag); + + return err; +} +EXPORT_SYMBOL(pcie_tph_set_st); diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index b12a592f3d49..1cc99cc528bd 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -21,6 +21,9 @@ bool pcie_tph_intr_vec_supported(struct pci_dev *dev); int pcie_tph_get_st_from_acpi(struct pci_dev *dev, unsigned int cpu_acpi_uid, enum tph_mem_type tag_type, u8 req_enable, u16 *tag); +int pcie_tph_set_st(struct pci_dev *dev, unsigned int msix_nr, + unsigned int cpu, enum tph_mem_type tag_type, + u8 req_enable); #else static inline void pcie_tph_disable(struct pci_dev *dev) {} static inline void pcie_tph_set_nostmode(struct pci_dev *dev) {} @@ -30,6 +33,10 @@ static inline int pcie_tph_get_st_from_acpi(struct pci_dev *dev, unsigned int cp enum tph_mem_type tag_type, u8 req_enable, u16 *tag) { return false; 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Wed, 17 Jul 2024 20:56:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE3F.mail.protection.outlook.com (10.167.242.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Wed, 17 Jul 2024 20:56:55 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 17 Jul 2024 15:56:54 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 08/10] PCI/TPH: Add TPH documentation Date: Wed, 17 Jul 2024 15:55:09 -0500 Message-ID: <20240717205511.2541693-9-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240717205511.2541693-1-wei.huang2@amd.com> References: <20240717205511.2541693-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3F:EE_|MN0PR12MB5860:EE_ X-MS-Office365-Filtering-Correlation-Id: 39493087-cf27-4ac7-6219-08dca6a2fe3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:56:55.8735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39493087-cf27-4ac7-6219-08dca6a2fe3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5860 Provide a document for TPH feature, including the description of kernel options and driver API interface. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek Reviewed-by: Jonathan Cameron --- Documentation/PCI/index.rst | 1 + Documentation/PCI/tph.rst | 57 ++++++++++++++++++++++++++++ Documentation/driver-api/pci/pci.rst | 3 ++ 3 files changed, 61 insertions(+) create mode 100644 Documentation/PCI/tph.rst diff --git a/Documentation/PCI/index.rst b/Documentation/PCI/index.rst index e73f84aebde3..5e7c4e6e726b 100644 --- a/Documentation/PCI/index.rst +++ b/Documentation/PCI/index.rst @@ -18,3 +18,4 @@ PCI Bus Subsystem pcieaer-howto endpoint/index boot-interrupts + tph diff --git a/Documentation/PCI/tph.rst b/Documentation/PCI/tph.rst new file mode 100644 index 000000000000..103f4c3251e2 --- /dev/null +++ b/Documentation/PCI/tph.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=========== +TPH Support +=========== + + +:Copyright: 2024 Advanced Micro Devices, Inc. +:Authors: - Eric van Tassell + - Wei Huang + +Overview +======== +TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices +to provide optimization hints, such as desired caching behavior, for +requests that target memory space. These hints, in a format called steering +tags, are provided in the requester's TLP headers and can empower the system +hardware, including the Root Complex, to optimize the utilization of platform +resources for the requests. + +User Guide +========== + +Kernel Options +-------------- +There are two kernel command line options available to control TPH feature + + * "notph": TPH will be disabled for all endpoint devices. + * "nostmode": TPH will be enabled but the ST Mode will be forced to "No ST Mode". + +Device Driver API +----------------- +In brief, an endpoint device driver using the TPH interface to configure +Interrupt Vector Mode will call pcie_tph_set_st() when setting up MSI-X +interrupts as shown below: + +.. code-block:: c + + for (i = 0, j = 0; i < nr_rings; i++) { + ... + rc = request_irq(irq->vector, irq->handler, flags, irq->name, NULL); + ... + if (!pcie_tph_set_st(pdev, i, cpumask_first(irq->cpu_mask), + TPH_MEM_TYPE_VM, PCI_TPH_REQ_TPH_ONLY)) + pr_err("Error in configuring steering tag\n"); + ... + } + +The caller is suggested to check if interrupt vector mode is supported using +pcie_tph_intr_vec_supported() before updating the steering tags. If a device only +supports TPH vendor specific mode, its driver can call pcie_tph_get_st_from_acpi() +to retrieve the steering tag for a specific CPU and uses the tag to control TPH +behavior. + +.. kernel-doc:: drivers/pci/pcie/tph.c + :export: + :identifiers: pcie_tph_intr_vec_supported pcie_tph_get_st_from_acpi pcie_tph_set_st diff --git a/Documentation/driver-api/pci/pci.rst b/Documentation/driver-api/pci/pci.rst index aa40b1cc243b..3d896b2cf16e 100644 --- a/Documentation/driver-api/pci/pci.rst +++ b/Documentation/driver-api/pci/pci.rst @@ -46,6 +46,9 @@ PCI Support Library .. kernel-doc:: drivers/pci/pci-sysfs.c :internal: +.. kernel-doc:: drivers/pci/pcie/tph.c + :export: + PCI Hotplug Support Library --------------------------- From patchwork Wed Jul 17 20:55:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 13735775 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2078.outbound.protection.outlook.com [40.107.92.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B2BB184129; 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Wed, 17 Jul 2024 15:57:10 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 09/10] bnxt_en: Add TPH support in BNXT driver Date: Wed, 17 Jul 2024 15:55:10 -0500 Message-ID: <20240717205511.2541693-10-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240717205511.2541693-1-wei.huang2@amd.com> References: <20240717205511.2541693-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|IA0PR12MB8373:EE_ X-MS-Office365-Filtering-Correlation-Id: a023e7f3-9b44-40a5-f9eb-08dca6a308bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: yWVO59VtT03H6h3mdAdljzz4aihGSPx1RuspcCbTRmUaPY+m3bvYO5jBywclf4mTyoP1Zor24sABMqIrSuf1TO1MN86AkYfzrczI10ixhRfwd5uJRywjns4OnBxkP5IqNGIsPJitccMShT7Jsm9qVWs8JhXaPblp/giNcesHJXnO7gzAVbJCqrPowRdNLAe8pUVvAt3pAf4TcisGJqflpf0xfvtEP0aa+2RdGM0DRS/E0nO7PB/1CLEhO0+KIHlDn70koeERdx8zIi/p2SzXTOPWvfRgI3HryJHZKx3GzO7i1iQxBs0ftPDDRinwB4rRA/oBhaHM9xMC2ZaAiiJYmElH5bwOEW8up2aYKj6K/TeHGOx/KxDqO+SlHRDvPJt63xCz6jstpSQ2E6bTe5nbxR7Rlt9pTmHl7fXB/D4pUmeDYQcpqXoH0RNt6R8WujCQ5M2EMHE8fgE0R4PMDdE1mu4TtJP7etJNyZv9bJjqoNfjEzL2QNyxGs20/PvlbSnoPTU81nKLNufo/x+mL7TKVJkfqyO8vk8Fpc2vqXMJyeQdEqufdov8tXcFKu34wp3gai0plpG43yEjiZNDq3rWDSthNEEMVMhT1gXb8cl/d+bOzJMi5BFBGejeptTdjMAp/a89MDM8f03GPITp/p4c7DQ94Y/1DbJJT2EyKZrKGp86jejqeovnIxjAwddyHIMGMQkdlJJb/mu9Ve+N5PNn1cXS5bC0Ks5VeXDAidE2cIg71IQeXCI4/E4l/T9BM+uUwHUJ3qalggIxIlNzS/iuO/jbnUnTCNp7vY7STkgWbNvKupelaKFkMirFbHS/MjTbJh2svffdcZFnlRkz1Kgu6C33XK9ScyXovmgtJKOQZ78GDSl9jNUErXb8/DD4DjKyuyjwQ/1vIEsb4tEAFXkOISLNmgQS/Yg4ep9NSOC291kV3tLoaQYhctfzKIIbmPxykVc1YXEl/Qq/tpduDKCBFnEjTr/tPgX1c68HKu1+yVJhL3RJliujzMRiM7QLJE1iLVtbED1n5IzXmp55AZNt66kZTt2RNYbRqZ1XxflRVQ1SZNXqXpcHvGxxn3L64toX8Ttr9Vn7fqXtnt22h4QE4WWjAoYKP2gr7jybDKd2RyFMkH0NVUGuz7/q8dqjiX99tCJahcx/4rRSO0KhiMwccUZjutyeaMYDnNfK4CVjeUWPSmszULytW79W3lrlvG9kAhCzxtUlAzkv0KEMAMHURgngu1UfOtHtKhoFtXhO669t7ZWRmNUe2B7QpNnrkSHo/K9YAqQDUwsfLZzItIdxBZ+HNCeL164XlCV/Ey00na1lkC5/N1zv+9w1JKhdLr+bknjCgJcqJEvXArsV79rIgVhjn5wCSSZ7pPeUffMkb6Q5TtbKkEZQ1o6HUvPyTXG0jpTnQouk8TH0mrWZ+2qVf3ASf6kx9diKuGDmxwnCt0ITv8RZ1mcxyHAd3i9OyglQ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:57:13.5091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a023e7f3-9b44-40a5-f9eb-08dca6a308bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8373 From: Manoj Panicker Implement TPH support in Broadcom BNXT device driver by invoking pcie_tph_set_st() function when interrupt affinity is changed. Signed-off-by: Manoj Panicker Reviewed-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 54 +++++++++++++++++++++++ drivers/net/ethernet/broadcom/bnxt/bnxt.h | 4 ++ 2 files changed, 58 insertions(+) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index c437ca1c0fd3..2207dac8ce18 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -55,6 +55,7 @@ #include #include #include +#include #include "bnxt_hsi.h" #include "bnxt.h" @@ -10683,6 +10684,8 @@ static void bnxt_free_irq(struct bnxt *bp) free_cpumask_var(irq->cpu_mask); irq->have_cpumask = 0; } + if (pcie_tph_intr_vec_supported(bp->pdev)) + irq_set_affinity_notifier(irq->vector, NULL); free_irq(irq->vector, bp->bnapi[i]); } @@ -10690,6 +10693,45 @@ static void bnxt_free_irq(struct bnxt *bp) } } +static void bnxt_rtnl_lock_sp(struct bnxt *bp); +static void bnxt_rtnl_unlock_sp(struct bnxt *bp); +static void __bnxt_irq_affinity_notify(struct irq_affinity_notify *notify, + const cpumask_t *mask) +{ + struct bnxt_irq *irq; + + irq = container_of(notify, struct bnxt_irq, affinity_notify); + cpumask_copy(irq->cpu_mask, mask); + + if (!pcie_tph_set_st(irq->bp->pdev, irq->msix_nr, + cpumask_first(irq->cpu_mask), + TPH_MEM_TYPE_VM, PCI_TPH_REQ_TPH_ONLY)) + netdev_dbg(irq->bp->dev, "error in setting steering tag\n"); + + if (netif_running(irq->bp->dev)) { + rtnl_lock(); + bnxt_close_nic(irq->bp, false, false); + bnxt_open_nic(irq->bp, false, false); + rtnl_unlock(); + } +} + +static void __bnxt_irq_affinity_release(struct kref __always_unused *ref) +{ +} + +static inline void bnxt_register_affinity_notifier(struct bnxt_irq *irq) +{ + struct irq_affinity_notify *notify; + + notify = &irq->affinity_notify; + notify->irq = irq->vector; + notify->notify = __bnxt_irq_affinity_notify; + notify->release = __bnxt_irq_affinity_release; + + irq_set_affinity_notifier(irq->vector, notify); +} + static int bnxt_request_irq(struct bnxt *bp) { int i, j, rc = 0; @@ -10735,6 +10777,7 @@ static int bnxt_request_irq(struct bnxt *bp) int numa_node = dev_to_node(&bp->pdev->dev); irq->have_cpumask = 1; + irq->msix_nr = map_idx; cpumask_set_cpu(cpumask_local_spread(i, numa_node), irq->cpu_mask); rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); @@ -10744,6 +10787,17 @@ static int bnxt_request_irq(struct bnxt *bp) irq->vector); break; } + + if (pcie_tph_intr_vec_supported(bp->pdev)) { + irq->bp = bp; + bnxt_register_affinity_notifier(irq); + + /* first setup */ + if (!pcie_tph_set_st(bp->pdev, i, + cpumask_first(irq->cpu_mask), + TPH_MEM_TYPE_VM, PCI_TPH_REQ_TPH_ONLY)) + netdev_dbg(bp->dev, "error in setting steering tag\n"); + } } } return rc; diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index 656ab81c0272..4a841e8ccfb7 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -1195,6 +1195,10 @@ struct bnxt_irq { u8 have_cpumask:1; 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Wed, 17 Jul 2024 20:57:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE39.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Wed, 17 Jul 2024 20:57:23 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 17 Jul 2024 15:57:22 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 10/10] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Date: Wed, 17 Jul 2024 15:55:11 -0500 Message-ID: <20240717205511.2541693-11-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240717205511.2541693-1-wei.huang2@amd.com> References: <20240717205511.2541693-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE39:EE_|CY5PR12MB6322:EE_ X-MS-Office365-Filtering-Correlation-Id: b84f2344-2755-4fed-896a-08dca6a30ec0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2024 20:57:23.5428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b84f2344-2755-4fed-896a-08dca6a30ec0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE39.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6322 From: Michael Chan Newer firmware can use the NQ ring ID associated with each RX/RX AGG ring to enable PCIe steering tag. Older firmware will just ignore the information. Signed-off-by: Michael Chan Signed-off-by: Andy Gospodarek Reviewed-by: Hongguang Gao Reviewed-by: Ajit Khaparde --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 2207dac8ce18..308b4747d041 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -6699,10 +6699,12 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp, /* Association of rx ring with stats context */ grp_info = &bp->grp_info[ring->grp_idx]; + req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); req->enables |= cpu_to_le32( - RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); + RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID | + RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); if (NET_IP_ALIGN == 2) flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; req->flags = cpu_to_le16(flags); @@ -6714,11 +6716,13 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp, /* Association of agg ring with rx ring */ grp_info = &bp->grp_info[ring->grp_idx]; req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); + req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); req->enables |= cpu_to_le32( RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | - RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); + RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID | + RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); } else { req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX; }