From patchwork Wed Jul 17 21:25:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13735801 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6972B18757C; Wed, 17 Jul 2024 21:25:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251557; cv=none; b=FCoFUuvT2xStQl/1FQSmN0hSEoxf62VsNrkq63xk4DfA3zPNySZwpeDvrRJ+dP8Ka5Lr735U0cI0lVw0UJBTWk1srWwTgjpTBGHQ/TUYPfJCtmzaVnLGk+4bjiHTzd8MFpOdobfhcg2Gmozsc2ODhOIvjljTSQunLU81AEIx2BA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251557; c=relaxed/simple; bh=MwH4ZbeVtJDn9nLY/Lcp4DnUPzjHuUxaI30Mjp+RPm4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=quylNe0Rc500RSD5WTy2Bf4kGs+lCPxxNqF84W9+mdebUiLbqfAFmX604XjD5VA1ErJv6TMUWBQaNcfpXxFM4yRI6MMjkjcOy0Kuc1+PRJYrTqzQV7oxay6J3PnwuxB/5hEhSTRMcVPLeW9lORMQW+gQ3Xgr7xMry69xvzRsZqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AYQlx+GM; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AYQlx+GM" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4266fcb311cso879195e9.1; Wed, 17 Jul 2024 14:25:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721251554; x=1721856354; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=og7z13DastBZEYSjicgLUwM+3MEwA4uV60q45Xpmo0A=; b=AYQlx+GME3dBME2ldMRWQtfJ6tJvsBhyigyZwnCBMZ/WeOb5mseo336WZKfkLlETU8 oNYxWMwmtnmdfy3pb3F4SStHJjpmuXdUwYrsyvv3kwyJMfC/9ExgerInPRyUrwB34neZ yfNwRWwEMpOfp7Y0rfAs3e1g2i/fwoIYJMBnlTXozVhpKoUQ+NQ1Xl0Tfsx/QSPr2wz9 ywCdNOX+fbCvUm8FNNPtjMRUTiYwj4Y3oEugfSy50UzUt1KVivWOopqXYcgRDzI30QwQ 3pZLMWVJamVP1loF+Um8Ey+nisImnuG0N/YMWWLoxbVF5PSwFCnPqqdAXN6mv8K8zf9X EwfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721251554; x=1721856354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=og7z13DastBZEYSjicgLUwM+3MEwA4uV60q45Xpmo0A=; b=U723McabCSc/8vixmFVMmTR3FGaOSTpap9q6IX6dKX1APeDOQ7410cAYltvvng7/Yd On5a8voxar3/59KJ15IFZwc2X0hCYQQe0iAeUBr7KOnKAkUY55pkgAkI7FCPSw7U4o4J Sk6LcjzuP7vBqGIm8KvJmP2sOuhGkkgOZ3061tV8m68J3bAZNtYIKia43o7YRRxfrnyq iEK3IrKL1esgvk39abrLBcsyX0TaPLSletDQhVz1AzoLhLlr4o3xp5T7ecBzQrI01J0E GElvQFfBIdRMys7WV3nJpRrX3B0q/mTZltp/Dx0d9+/tAYlzB+Jqwc5PCeh+DdRG/yb4 Cs6A== X-Forwarded-Encrypted: i=1; AJvYcCUNJisQaMrGBIsHm1y8qhzdaqJsOKSCNobyVRrzmyOaT54rTjw+wAYnWkc17NpFU0PRDIyGx9L2zUsx/tnBE5e/9+OMvYz71wd12+lfwz8n6KEmpzIPWBsI05fXNQ3s30Izq03nw+nlBerLPeAsXj45Sp+WmpJAsILWZDZ99aWWHdu0hQ== X-Gm-Message-State: AOJu0Yw3k4wLFaw9xHKcEAjL4DdVFSq8pn4ydd8Sw5jk2b/ZN2xEWJ4K v2CuTOZ5ZRygbDCqxH998VFlxjeUs8Obp/LwPJbboA9L0SgBwbAE X-Google-Smtp-Source: AGHT+IFKkECmiZpqOalMmBkaR4AregsEXjfqJf+QJIIDLYKT32z681Qa7rZcKRcb40nV21PAaSloFw== X-Received: by 2002:a05:600c:19cc:b0:426:689b:65b7 with SMTP id 5b1f17b1804b1-427c2d2d8fbmr21819195e9.25.1721251553808; Wed, 17 Jul 2024 14:25:53 -0700 (PDT) Received: from spiri.. ([86.124.123.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427c77b030bsm10532735e9.17.2024.07.17.14.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 14:25:53 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conor Dooley Subject: [PATCH v7 1/4] dt-bindings: iio: adc: ad7192: Update clock config Date: Thu, 18 Jul 2024 00:25:32 +0300 Message-Id: <20240717212535.8348-2-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240717212535.8348-1-alisa.roman@analog.com> References: <20240717212535.8348-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. To configure external clock as either a crystal or a CMOS-compatible clock, changing the register settings is necessary. Therefore, add clock name xtal alongside mclk. By selecting one or the other, the register is configured. The presence of an external clock source is optional, not required. When both clocks and clock-names properties are present, an external clock source is used. If the intention is to use the internal clock, both properties should be absent. Modify required properties accordingly. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Conor Dooley --- .../bindings/iio/adc/adi,ad7192.yaml | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index a03da9489ed9..c3adc32684cf 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -39,11 +39,15 @@ properties: clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: + Optionally, either a crystal can be attached externally between MCLK1 and + MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 + pin. If absent, internal 4.92MHz clock is used. clock-names: - items: - - const: mclk + enum: + - xtal + - mclk interrupts: maxItems: 1 @@ -135,8 +139,6 @@ patternProperties: required: - compatible - reg - - clocks - - clock-names - interrupts - dvdd-supply - avdd-supply @@ -157,6 +159,16 @@ allOf: then: patternProperties: "^channel@[0-9a-f]+$": false + - if: + anyOf: + - required: + - clocks + - required: + - clock-names + then: + required: + - clocks + - clock-names unevaluatedProperties: false From patchwork Wed Jul 17 21:25:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13735802 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 395F718C32F; Wed, 17 Jul 2024 21:26:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251561; cv=none; b=i8iykbuwb7pkWGtLbuwv1XGltOfdTKfQaVqP7MwtD2STEJFNDtsmTHYifZmX9BkncERhKvc4BiDkeMEwY7tbav8UtcylPyyhpE8OjuTqdzdjnclsYiYnj/QHJPE4A96eCwUIfbeG/9EN2TKFGnTuAwO3d3YuCpgLhFTEdEQCfX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251561; c=relaxed/simple; bh=EPnqK00Zbzb3HGOrZO6C1bpI7XsCkYhT1PpT9l8PLfY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YfspdmJccy5xe2YAJDnVKwo6MkIGhHLrQU7z0fDjXASBrQ108NK6IdSLQRGpwEhLLjOb7389j2UKlJrZwVWpLyzbHtjNleMbwyp+wnmYH2FCKiI7YPDRR4rr+pQmeFrmkJWDEdj2jPnasJykO3eilYb3SdaMu3y2tWnICyvojjI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KzVhWP2Z; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KzVhWP2Z" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-42797bcfc77so825155e9.2; Wed, 17 Jul 2024 14:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721251558; x=1721856358; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/nMwL8aJUa7GifJHTRApBtb5HON4txSFXIHmf17V1nM=; b=KzVhWP2Zqc/mkmwU9/DrumDUByF0Gjj/V4MpfqkOAH7G5AcMKMDBqLj3wbaz/qWps6 DfKKaEx/tmFgavrHvHqn3cHH2HV260TZB7ABzT1fUDKwhtOFYbtnH9o5dXSRN36lkWX2 W9ozxSRDOZThJoKH8ZXokmoRQHmD4fPwZdas3WCivMZ2qiw6rCof109FKkBycbM1mWO7 4+AY/dKKHN3kRTQFj2ADTjJ8/AY2T/pK82oiaa+r3V8LDQqEMHLDflDKwKBb8RKRZuzA gvn94fmZy2wMGuRjzVBpR5sifZkWMuqaJDfnPqTmAzdWwEl6tiORUltTebT1WDUvA+mW 3k3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721251558; x=1721856358; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/nMwL8aJUa7GifJHTRApBtb5HON4txSFXIHmf17V1nM=; b=X11z+xM+stLE1pD73GNxQEL4Kz84U8O91P/Wn5dVcTmxrnIi4jaYJ47dg9zn/3HvC8 iv6uku6LlYmZMtqCNaMYv0FwnOExjlYSPrIxxAQu7nMj1Jxbmop6zoqva+FM7V7H+jPe 4pQtqKTJm9DhG2f/7WJ9RKKtU0tXI8baRi76UnIXJ9dvlO2UhmGakKoXPOyQSySPWJ7g g1/fqogUHBUZgCN18yZqYNwAj5hcL/5H5Vh4qJx2eGXRDaqlaol6Qx9x5oLx1ud19ne4 BjEqffVa3f0857mzulP0/x2a3EOD5sqp4eNXgKpI5d4L77uivkU8skAxE9TToO1bQNMM FHaQ== X-Forwarded-Encrypted: i=1; AJvYcCVozqjRXR+KtVLa9jRGaoyIO/XhzW6hq/lV6lA9SS5EiJzQ/eLR69l1iXSMBGym5aOV3voCN1X/BIDnzJUZIbHyHITHI81zVhEqfG5pEWAR2mfmis12/TcAKkq7iUdwkuKkseasCVXBL+8ZPN6gHSgiSCRTHxA2AfvmPpUT/Ex9XH+r1g== X-Gm-Message-State: AOJu0YzqrIcW3nYUDU1gXa3F3irJ5glGsr7/cJSQhcd3vpcx3wzxfW0M 7IM6YAqaQilWOdC0IrhLweIUkHlmwIoVshyOz3TUDdATWi6IBE0UrDgE6HsB X-Google-Smtp-Source: AGHT+IE8186YpyhsC3RlwZDCa3EJDjw5UlTZGJXIBrBMFVmM7AEbS5mdadmVyfiiqEpDIZsQdfOWOA== X-Received: by 2002:a05:600c:1d1e:b0:426:64a2:5362 with SMTP id 5b1f17b1804b1-427c2cc97efmr21803495e9.8.1721251558588; Wed, 17 Jul 2024 14:25:58 -0700 (PDT) Received: from spiri.. ([86.124.123.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427c77b030bsm10532735e9.17.2024.07.17.14.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 14:25:58 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v7 2/4] iio: adc: ad7192: Update clock config Date: Thu, 18 Jul 2024 00:25:33 +0300 Message-Id: <20240717212535.8348-3-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240717212535.8348-1-alisa.roman@analog.com> References: <20240717212535.8348-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. Undocumented properties adi,int-clock-output-enable and adi,clock-xtal still supported for backward compatibility, but their use is highly discouraged. Use cleaner alternative of configuring external clock by using clock names mclk and xtal. Functionality of AD7192_CLK_INT_CO will be implemented in complementary patch by adding clock provider. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Nuno Sa --- drivers/iio/adc/ad7192.c | 91 +++++++++++++++++++++++++++------------- 1 file changed, 63 insertions(+), 28 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 334ab90991d4..042319f0c641 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -396,25 +396,72 @@ static inline bool ad7192_valid_external_frequency(u32 freq) freq <= AD7192_EXT_FREQ_MHZ_MAX); } -static int ad7192_clock_select(struct ad7192_state *st) +/* + * Position 0 of ad7192_clock_names, xtal, corresponds to clock source + * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to + * AD7192_CLK_EXT_MCLK2 + */ +static const char *const ad7192_clock_names[] = { + "xtal", + "mclk" +}; + +static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev = &st->sd.spi->dev; - unsigned int clock_sel; + int ret; - clock_sel = AD7192_CLK_INT; + /* + * The following two if branches are kept for backward compatibility but + * the use of the two devicetree properties is highly discouraged. Clock + * configuration should be done according to the bindings. + */ - /* use internal clock */ - if (!st->mclk) { - if (device_property_read_bool(dev, "adi,int-clock-output-enable")) - clock_sel = AD7192_CLK_INT_CO; - } else { - if (device_property_read_bool(dev, "adi,clock-xtal")) - clock_sel = AD7192_CLK_EXT_MCLK1_2; - else - clock_sel = AD7192_CLK_EXT_MCLK2; + if (device_property_read_bool(dev, "adi,int-clock-output-enable")) { + st->clock_sel = AD7192_CLK_INT_CO; + st->fclk = AD7192_INT_FREQ_MHZ; + dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n"); + return 0; } - return clock_sel; + if (device_property_read_bool(dev, "adi,clock-xtal")) { + st->clock_sel = AD7192_CLK_EXT_MCLK1_2; + st->mclk = devm_clk_get_enabled(dev, "mclk"); + if (IS_ERR(st->mclk)) + return dev_err_probe(dev, PTR_ERR(st->mclk), + "Failed to get mclk\n"); + + st->fclk = clk_get_rate(st->mclk); + if (!ad7192_valid_external_frequency(st->fclk)) + return dev_err_probe(dev, -EINVAL, + "External clock frequency out of bounds\n"); + + dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n"); + return 0; + } + + ret = device_property_match_property_string(dev, "clock-names", + ad7192_clock_names, + ARRAY_SIZE(ad7192_clock_names)); + if (ret < 0) { + st->clock_sel = AD7192_CLK_INT; + st->fclk = AD7192_INT_FREQ_MHZ; + return 0; + } + + st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; + + st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); + if (IS_ERR(st->mclk)) + return dev_err_probe(dev, PTR_ERR(st->mclk), + "Failed to get clock source\n"); + + st->fclk = clk_get_rate(st->mclk); + if (!ad7192_valid_external_frequency(st->fclk)) + return dev_err_probe(dev, -EINVAL, + "External clock frequency out of bounds\n"); + + return 0; } static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) @@ -1275,21 +1322,9 @@ static int ad7192_probe(struct spi_device *spi) if (ret) return ret; - st->fclk = AD7192_INT_FREQ_MHZ; - - st->mclk = devm_clk_get_optional_enabled(dev, "mclk"); - if (IS_ERR(st->mclk)) - return PTR_ERR(st->mclk); - - st->clock_sel = ad7192_clock_select(st); - - if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || - st->clock_sel == AD7192_CLK_EXT_MCLK2) { - st->fclk = clk_get_rate(st->mclk); - if (!ad7192_valid_external_frequency(st->fclk)) - return dev_err_probe(dev, -EINVAL, - "External clock frequency out of bounds\n"); - } + ret = ad7192_clock_setup(st); + if (ret) + return ret; ret = ad7192_setup(indio_dev, dev); if (ret) From patchwork Wed Jul 17 21:25:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13735803 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8B6A187327; Wed, 17 Jul 2024 21:26:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251565; cv=none; b=jPAd55oXgEUOxCEgGsmGb4wgAsJeMi7QKvyoflK6AQaEm17uy3nswus0gas7YrUG+zPonM5s0gY+zStLKV7wfeLnAlYJyMMIgfKUZR7IyfcFI2rgzzd4Yz11VdY7qMai46mr2Um6HieST6e9woURHIyM5zt/ri2XwJ+JTSMF4lc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251565; c=relaxed/simple; bh=q0QXKPOoj/Khd748ndxVYRbG9o7mTel+H5n9hSzkqUA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hmjMMxezocFR98UYwES6pqrkBZX6zGO8EXwZAtRO1wfS8GIBL3PtLeeo01vxFvLxvTsrcU8H3zq1Mg+pGgWLZNz8aE1rPa6S+SpjklYBQDtdZRIaCETJGa9vVoonXWf3ymuB9MDhL/u0nlug1b+mxtCHCMex8P7PID/OJBxw6LA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Gdi/cAPk; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Gdi/cAPk" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-42793fc0a6dso953065e9.0; Wed, 17 Jul 2024 14:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721251561; x=1721856361; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0sg8LKJx++D3XfRHX+4zY2+YNwXjqTcalUFZETrZ3jQ=; b=Gdi/cAPkixlLPlXvIPZKFxjS46lJUQmz7mjh7sXBQLZiSXr/ilWHU5h8NwDj6Q/mNq F2zSbiwT1QEJH+OIXHfoBYtfkG6IdDFERlvqnvQaTGW9cK++tunDnohmST/hgu07y8Ly E/Hf9q1O2CVHbELRLvFkvCwQhyaHZzVjce9npBFNZrEU4vU4NIDvulUYzFMcDdAGjE1R aS9mJ9Gq7vTpx/8TNIO9WEIR/WpamFRQ1y9Vcm91KV0otMTyq8XFkciI8u3bWudCdlaU yNfYKM6RMtuWWv5ZYGr/Kme50/953kX2yU5bsJNuDRCbTQFXJVEDu1hKP0Wt2JDl3NI7 +1Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721251561; x=1721856361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0sg8LKJx++D3XfRHX+4zY2+YNwXjqTcalUFZETrZ3jQ=; b=NFyM0hVze/lXik/gfdkTtuUOH8OQJz/UtQBMq8rStmuCgTIxfqIcBgscY9XaAunLa9 cDmVrjA5+y2ufXlhUsrvOm6kQALVeFQc+svsZ68TLrQPutooNyF5U7DKs+mMV57prW4R tteocpfelHIRrBdJM4ZAqcveXUHSKMutbCf0Bd5TtT1WaoTjIHpJHNhDMSkpO6azLhIT IXSEOKkFoTtYeik70hMo90Yt3m6A640maQh3e/HfzLGj7Z1E1ib4KoA70nf6C+F2mXYl aAfvqBjjcZ6m4gr30z47GoA87hjRujJTOh6/oKamVuJSpWRfD+VtckgCp2lp72AFNR5n WLow== X-Forwarded-Encrypted: i=1; AJvYcCXBck/8Y87I3+OIOoyzt2i987VwPn5rHuQr4Upy1VBnLsxXv/1FQPuY3RHi4iA6+jdfLBE6mIM0eMfuwI+XqT6Qjvbl3tT9KyblIB50oBHD/72iKLguNvDmt7YD/tnFrxkHkiGl8UVdK2xrxu6Rz+YAcb9b3rGghLZUN3IQ4l6MFLoB6w== X-Gm-Message-State: AOJu0Yy39ZYrfv1foTdfNnBKRgr82wvdA6DPfEPIK0rT7oENLxCZnjVz /xEUyvq9HN8bU3jFpN1aE1yZcAOcYvHTTQl9x2fWK6Fi3HuBPjdV8v3548zE X-Google-Smtp-Source: AGHT+IH3UgY6jeuxXwJsetVvU8SPN5MVMd+5wsN5vchiFc+o68wYOtFPgyDuRbpyOlYtVUw+z5Wraw== X-Received: by 2002:a05:600c:1551:b0:426:6960:34b2 with SMTP id 5b1f17b1804b1-427c2d0d613mr17359325e9.33.1721251561244; Wed, 17 Jul 2024 14:26:01 -0700 (PDT) Received: from spiri.. ([86.124.123.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427c77b030bsm10532735e9.17.2024.07.17.14.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 14:26:00 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v7 3/4] dt-bindings: iio: adc: ad7192: Add clock provider Date: Thu, 18 Jul 2024 00:25:34 +0300 Message-Id: <20240717212535.8348-4-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240717212535.8348-1-alisa.roman@analog.com> References: <20240717212535.8348-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality when clock cells property is present. The clock source can be either provided externally or the internal clock is used. Pair of clocks and clock-names property is mutally exclusive with #clock-cells property. Modify second example to showcase the mode where internal clock is used. Signed-off-by: Alisa-Dariana Roman Acked-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7192.yaml | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index c3adc32684cf..edfa4378e838 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -42,13 +42,19 @@ properties: description: Optionally, either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 - pin. If absent, internal 4.92MHz clock is used. + pin. If absent, internal 4.92MHz clock is used, which can be made + available on MCLK2 pin. clock-names: enum: - xtal - mclk + "#clock-cells": + const: 0 + description: + If present when internal clock is used, configured as clock provider. + interrupts: maxItems: 1 @@ -169,6 +175,8 @@ allOf: required: - clocks - clock-names + properties: + "#clock-cells": false unevaluatedProperties: false @@ -214,8 +222,7 @@ examples: spi-max-frequency = <1000000>; spi-cpol; spi-cpha; - clocks = <&ad7192_mclk>; - clock-names = "mclk"; + #clock-cells = <0>; interrupts = <25 0x2>; interrupt-parent = <&gpio>; aincom-supply = <&aincom>; From patchwork Wed Jul 17 21:25:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13735804 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00055186E48; Wed, 17 Jul 2024 21:26:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251567; cv=none; b=EC7uuDsUWGQ+jMfyCXl3HII4UCiQFRu5Kxow0MVCW2abxRmpOSxKqHYRsg1TzQPZqpxfPnwBAcEbc2ZK6s/BAfPl7EUZiHFajrlZXQdY0O0mOYLP6dP5LYm7/Pqo95JgX27NZKmWVwWmvJ1gf59Rir76S/NgxUqJMZs5XsLhZEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721251567; c=relaxed/simple; bh=OYZ4Lp+LsKfB963iUHxM1nUX0jbGE/poJifLj3btfQE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nG+sAPithfurUHNTfjHzwAatuP2kXUsMAakf5gsGHVowyuS7tzX9w7eNWMDJjHEC5BxTM/KEIUlD74vkya4Noisc8SrekO18yuPV7cQZ7WnvrJu4mGE9M00XoGqrydekL8dNHoBeeMy34lbWAME47pWKfqh761MRxTc9/8NRTbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bW6eKiP5; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bW6eKiP5" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-427b4c621b9so867645e9.1; Wed, 17 Jul 2024 14:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721251564; x=1721856364; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HjTTLNALQlo0+Bax0fTOpezWlVszgVp9jzrNq2e7X+M=; b=bW6eKiP5S+7NNsyBu5VQhtwI2qIEfHO+q8ldaUYY35VqV2huooipx58YXc0+1vSxH5 4ePvbqellPGdUhAnwSotXq/abC5p5oCj/y1/MC5xSuTB/0NnsSwXgcuO+J9ZxURfpZxg estj4FrakZy52JVUwJZdU38fXubQrl89PA+OZe32jeHbz6JSKbGmTh8ObHA0Pbr6+N/0 YvFT8dIUNHeoCuawrSW5uHaSdMxXO7Qa1rwD4/YATugHQPvDEH5SBSFfzA/T+AvMbI18 JxM4hgjyMZDvQt1qtlDvxzwYUEGiJA6zXom49d223uQDhkSVBkO+Vh/u1qeymSPtRsOR XyWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721251564; x=1721856364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HjTTLNALQlo0+Bax0fTOpezWlVszgVp9jzrNq2e7X+M=; b=otIz2r+hDsVGhrFxwD9xXlngOcutIidK0m87CA/4qo0XgFqp85b3ETSsdn/uAoJwQK xyAlSN2odOOW2f0Xy+vdkp8yGytEAlhLa6Ga38qDcd4gEwrOVUhOO8AJjNXZad7YvLl6 XhSb2bq9Iz7RrgU5DG36+SOlVdSqe4acVxuJ3KWptGTtlNuV7wmJfk4akHLkJbhVlruJ L5idJJr/3IDl4PFQnsn+LbbKel8pUxKDuPhATM2l2AJRVjP1pkJ0qIis9x+/PM/zVJfN J3aMZ4UpSnutAWCC+2hXR5iyYyHGX7DT0vc+bF60R1ljqSTI0YvpMtM/twJGyA4vN40s wTxQ== X-Forwarded-Encrypted: i=1; AJvYcCW74Perpjhg6HcwZmyHRiu6r7V7Plpkq62VRb+LsgWAPRnYawR0a3ytUg/o2FT+kAJ7IMtFG6P+hDW6dgaWgmHI1IYPcUGV30FeLIWsAZx5qrR/IzEdDVIWzhiJAUALVs59Q6aV6gdw7dhL0CfKf0KklTIeS4Sqp5D/a1wcX0WbnOcG+g== X-Gm-Message-State: AOJu0YyeZeG8xyYX3SxRwnHeEgfH2dLrjrskCezvhw3mmxxiyG7WxM5w QZcn2yQg/8lPWR/AZdtLviybj7zwzeVNnPEg79CChr9lP+RLNguV X-Google-Smtp-Source: AGHT+IHQVgh0uOb82kEziBzXJYj5fYIPt6ZSjzoHJBgc1tRu2d6lV/BbXSIrNGNIMO/2jiUKn2UJgg== X-Received: by 2002:a05:600c:4e90:b0:426:6617:ae4a with SMTP id 5b1f17b1804b1-427c2cbd731mr19414705e9.22.1721251564274; Wed, 17 Jul 2024 14:26:04 -0700 (PDT) Received: from spiri.. ([86.124.123.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427c77b030bsm10532735e9.17.2024.07.17.14.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 14:26:03 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v7 4/4] iio: adc: ad7192: Add clock provider Date: Thu, 18 Jul 2024 00:25:35 +0300 Message-Id: <20240717212535.8348-5-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240717212535.8348-1-alisa.roman@analog.com> References: <20240717212535.8348-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality when clock cells property is present. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Nuno Sa --- drivers/iio/adc/ad7192.c | 92 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 042319f0c641..3f803b1eefcc 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -201,6 +202,7 @@ struct ad7192_chip_info { struct ad7192_state { const struct ad7192_chip_info *chip_info; struct clk *mclk; + struct clk_hw int_clk_hw; u16 int_vref_mv; u32 aincom_mv; u32 fclk; @@ -406,6 +408,91 @@ static const char *const ad7192_clock_names[] = { "mclk" }; +static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) +{ + return container_of(hw, struct ad7192_state, int_clk_hw); +} + +static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return AD7192_INT_FREQ_MHZ; +} + +static int ad7192_clk_output_is_enabled(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + + return st->clock_sel == AD7192_CLK_INT_CO; +} + +static int ad7192_clk_prepare(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + int ret; + + st->mode &= ~AD7192_MODE_CLKSRC_MASK; + st->mode |= AD7192_CLK_INT_CO; + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return ret; + + st->clock_sel = AD7192_CLK_INT_CO; + + return 0; +} + +static void ad7192_clk_unprepare(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + int ret; + + st->mode &= ~AD7192_MODE_CLKSRC_MASK; + st->mode |= AD7192_CLK_INT; + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return; + + st->clock_sel = AD7192_CLK_INT; +} + +static const struct clk_ops ad7192_int_clk_ops = { + .recalc_rate = ad7192_clk_recalc_rate, + .is_enabled = ad7192_clk_output_is_enabled, + .prepare = ad7192_clk_prepare, + .unprepare = ad7192_clk_unprepare, +}; + +static int ad7192_register_clk_provider(struct ad7192_state *st) +{ + struct device *dev = &st->sd.spi->dev; + struct clk_init_data init = {}; + int ret; + + if (!device_property_present(dev, "#clock-cells")) + return 0; + + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + return 0; + + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", + fwnode_get_name(dev_fwnode(dev))); + if (!init.name) + return -ENOMEM; + + init.ops = &ad7192_int_clk_ops; + + st->int_clk_hw.init = &init; + ret = devm_clk_hw_register(dev, &st->int_clk_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &st->int_clk_hw); +} + static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev = &st->sd.spi->dev; @@ -446,6 +533,11 @@ static int ad7192_clock_setup(struct ad7192_state *st) if (ret < 0) { st->clock_sel = AD7192_CLK_INT; st->fclk = AD7192_INT_FREQ_MHZ; + + ret = ad7192_register_clk_provider(st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clock provider\n"); return 0; }