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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:49:51.4306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bfb8d7d-8a19-4759-8196-08dca7281d7b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7591 Remove the redundant local outb() implementation in favour of using the common outb() implementation defined in lib/x86/asm/io.h, and convert set_irq_line() to not open-code the out instruction. Verfied no changes in assembly output for all three callsites, tested, no functional changes were observed. The rationale behind this change is that, support for SNP tests that are introduced later will need apic sources to include common library io code and if we don't remove apic's local outb() implementation, then we get the following compilation conflicts: In file included from lib/x86/apic.c:7: lib/x86/asm/io.h:30:14: error: conflicting types for ‘outb’; have ‘void(unsigned char, short unsigned int)’ 30 | #define outb outb | ^~~~ Signed-off-by: Pavan Kumar Paluri --- lib/x86/apic.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/lib/x86/apic.c b/lib/x86/apic.c index 0d15147677dd..bbc2d8ae85b1 100644 --- a/lib/x86/apic.c +++ b/lib/x86/apic.c @@ -4,6 +4,7 @@ #include "processor.h" #include "smp.h" #include "asm/barrier.h" +#include "asm/io.h" /* xAPIC and I/O APIC are identify mapped, and never relocated. */ static void *g_apic = (void *)APIC_DEFAULT_PHYS_BASE; @@ -23,11 +24,6 @@ static struct apic_ops *get_apic_ops(void) return this_cpu_read_apic_ops(); } -static void outb(unsigned char data, unsigned short port) -{ - asm volatile ("out %0, %1" : : "a"(data), "d"(port)); -} - void eoi(void) { apic_write(APIC_EOI, 0); @@ -232,7 +228,7 @@ void set_mask(unsigned line, int mask) void set_irq_line(unsigned line, int val) { - asm volatile("out %0, %1" : : "a"((u8)val), "d"((u16)(0x2000 + line))); + outb((u8)val, (u16)(0x2000 + line)); } void enable_apic(void) From patchwork Thu Jul 18 12:49:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736453 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC35D13A407 for ; Thu, 18 Jul 2024 12:50:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721307013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:50:07.3194 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b19bd1d4-2df5-4869-f251-08dca72826f3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7180 MMIO access to APIC's private GPA with C-bit set that is not backed by memslots is no longer treated as MMIO access and is treated as an invalid guest access. So unset the C-bit on APIC page for it to be treated as a valid MMIO access. This applies to both SEV-ES/SNP guests. Signed-off-by: Pavan Kumar Paluri --- lib/x86/apic.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/lib/x86/apic.c b/lib/x86/apic.c index bbc2d8ae85b1..45ac36c5cbaf 100644 --- a/lib/x86/apic.c +++ b/lib/x86/apic.c @@ -5,6 +5,8 @@ #include "smp.h" #include "asm/barrier.h" #include "asm/io.h" +#include "amd_sev.h" +#include "x86/vm.h" /* xAPIC and I/O APIC are identify mapped, and never relocated. */ static void *g_apic = (void *)APIC_DEFAULT_PHYS_BASE; @@ -233,7 +235,19 @@ void set_irq_line(unsigned line, int val) void enable_apic(void) { + pteval_t *pte; + printf("enabling apic\n"); + + if (amd_sev_es_enabled()) { + pte = get_pte((pgd_t *)read_cr3(), + (void *)APIC_DEFAULT_PHYS_BASE); + + flush_tlb(); + *pte &= ~get_amd_sev_c_bit_mask(); + flush_tlb(); + } + xapic_write(APIC_SPIV, 0x1ff); } From patchwork Thu Jul 18 12:49:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736454 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2089.outbound.protection.outlook.com [40.107.244.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A4D13AA26 for ; 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Thu, 18 Jul 2024 07:50:22 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 03/16] x86 AMD SEV-ES: Rename setup_amd_sev_es() to setup_vc_handler() Date: Thu, 18 Jul 2024 07:49:19 -0500 Message-ID: <20240718124932.114121-4-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000011:EE_|BY5PR12MB4162:EE_ X-MS-Office365-Filtering-Correlation-Id: d1c7eb0a-e783-495d-8151-08dca7283072 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:50:23.2171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1c7eb0a-e783-495d-8151-08dca7283072 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000011.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4162 Re-organize the existing code to include a common helper function setup_vc_handler() to setup #VC handler that applies to both SEV-ES and SEV-SNP guests. On configuring KUT with --amdsev-efi-vc flag, This setup_vc_handler() continues to re-use UEFI's #VC handler. This is useful since it allows some KUT SNP tests to exercise aspects of OVMF's #VC handler support in addition to testing hypervisor support. However, if one prefers using SEV-ES/SNP's #VC handler, then --amdsev-efi-vc flag should not be passed during configuration. No functional change has been introduced in this patch. Signed-off-by: Pavan Kumar Paluri --- lib/x86/amd_sev.c | 6 +++++- lib/x86/amd_sev.h | 2 +- lib/x86/setup.c | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c index 987b59f9d650..ff435c90eeea 100644 --- a/lib/x86/amd_sev.c +++ b/lib/x86/amd_sev.c @@ -89,12 +89,16 @@ bool amd_sev_es_enabled(void) return sev_es_enabled; } -efi_status_t setup_amd_sev_es(void) +efi_status_t setup_vc_handler(void) { struct descriptor_table_ptr idtr; idt_entry_t *idt; idt_entry_t vc_handler_idt; + /* + * If AMD SEV-SNP is enabled, then SEV-ES is also enabled, so + * checking for SEV-ES covers both. + */ if (!amd_sev_es_enabled()) { return EFI_UNSUPPORTED; } diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index efd439fb5036..b5715082284b 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -139,7 +139,7 @@ efi_status_t setup_amd_sev(void); #define SEV_ES_GHCB_MSR_INDEX 0xc0010130 bool amd_sev_es_enabled(void); -efi_status_t setup_amd_sev_es(void); +efi_status_t setup_vc_handler(void); void setup_ghcb_pte(pgd_t *page_table); void handle_sev_es_vc(struct ex_regs *regs); diff --git a/lib/x86/setup.c b/lib/x86/setup.c index 65f5972adb29..d79a9f86eda4 100644 --- a/lib/x86/setup.c +++ b/lib/x86/setup.c @@ -334,7 +334,7 @@ efi_status_t setup_efi(efi_bootinfo_t *efi_bootinfo) /* Continue if AMD SEV is not supported, but skip SEV-ES setup */ if (status == EFI_SUCCESS) { phase = "AMD SEV-ES"; - status = setup_amd_sev_es(); + status = setup_vc_handler(); } if (status != EFI_SUCCESS && status != EFI_UNSUPPORTED) { From patchwork Thu Jul 18 12:49:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736455 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2080.outbound.protection.outlook.com [40.107.220.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F29954645 for ; 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Thu, 18 Jul 2024 07:50:33 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 04/16] x86/efi: Add support for running tests with UEFI in SEV-SNP environment Date: Thu, 18 Jul 2024 07:49:20 -0500 Message-ID: <20240718124932.114121-5-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000012:EE_|CH2PR12MB4198:EE_ X-MS-Office365-Filtering-Correlation-Id: b1389027-174b-4503-33df-08dca72836e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:50:34.0417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1389027-174b-4503-33df-08dca72836e6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000012.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4198 SEV-SNP guests require different QEMU command line parameters in comparison to SEV-ES, so adjust the QEMU options accordingly. It is important to note that SEV-SNP guests have some additional requirements versus an SEV/SEV-ES guest: - bios: SEV-SNP guests need a UEFI BIOS, and unlike with SEV-ES they cannot be loaded via pflash and instead rely on -bios option. - cpu: guest CPUID values are validated by SEV-SNP firmware and only a strictly-validated set of features should be advertised to the guest. This will usually require the use of an updated/architected QEMU CPU model version. "-cpu EPYC-v4" is used here as it has most common set of features compared to EPYC-Milan*/EPYC-Turin*/etc. models. - memory-backend-memfd: To support freeing memory after it is converted from shared->private, QEMU relies on memory that can be discarded via FALLOC_FL_PUNCH_HOLE, which is provided via object memory-backend-memfd. Add these options to the QEMU cmdline (in x86/eri/run) for bringing up SEV-SNP guest only when EFI_SNP is enabled. Signed-off-by: Pavan Kumar Paluri --- x86/efi/README.md | 6 ++++++ x86/efi/run | 33 +++++++++++++++++++++++++-------- 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/x86/efi/README.md b/x86/efi/README.md index af6e339c2cca..2c61dba336ec 100644 --- a/x86/efi/README.md +++ b/x86/efi/README.md @@ -34,6 +34,12 @@ the env variable `EFI_UEFI`: EFI_UEFI=/path/to/OVMF.fd ./x86/efi/run ./x86/msr.efi +### Run SEV-SNP tests with UEFI + +To run SEV-SNP related unit tests with UEFI: + + EFI_SNP=y ./x86/efi/run ./x86/amd_sev.efi + ## Code structure ### Code from GNU-EFI diff --git a/x86/efi/run b/x86/efi/run index 85aeb94fe605..da74eef4bd58 100755 --- a/x86/efi/run +++ b/x86/efi/run @@ -18,6 +18,7 @@ source config.mak : "${EFI_TEST:=efi-tests}" : "${EFI_SMP:=1}" : "${EFI_CASE:=$(basename $1 .efi)}" +: "${EFI_SNP:=n}" if [ ! -f "$EFI_UEFI" ]; then echo "UEFI firmware not found: $EFI_UEFI" @@ -54,11 +55,27 @@ cp "$EFI_SRC/$EFI_CASE.efi" "$EFI_CASE_BINARY" # to x86/run. This `smp` flag overrides any previous `smp` flags (e.g., # `-smp 4`). This is necessary because KVM-Unit-Tests do not currently support # SMP under UEFI. This last flag should be removed when this issue is resolved. -"$TEST_DIR/run" \ - -drive file="$EFI_UEFI",format=raw,if=pflash,readonly=on \ - -drive file.dir="$EFI_TEST/$EFI_CASE/",file.driver=vvfat,file.rw=on,format=raw,if=virtio \ - -net none \ - -nographic \ - -m 256 \ - "$@" \ - -smp "$EFI_SMP" +if [ "$EFI_SNP" != "y" ]; then + "$TEST_DIR/run" \ + -drive file="$EFI_UEFI",format=raw,if=pflash,readonly=on \ + -drive file.dir="$EFI_TEST/$EFI_CASE/",file.driver=vvfat,file.rw=on,format=raw,if=virtio \ + -net none \ + -nographic \ + -m 256 \ + "$@" \ + -smp "$EFI_SMP" + +else + "$TEST_DIR/run" \ + -bios "${EFI_UEFI}" \ + -drive file.dir="$EFI_TEST/$EFI_CASE/",file.driver=vvfat,file.rw=on,format=raw,if=virtio \ + -net none \ + -nographic \ + -m 256 \ + -object memory-backend-memfd,id=ram1,size=256M,share=true,prealloc=false \ + -machine q35,confidential-guest-support=sev0,memory-backend=ram1 \ + -object sev-snp-guest,id=sev0,cbitpos=51,reduced-phys-bits=1 \ + -cpu EPYC-v4 \ + "$@" \ + -smp "$EFI_SMP" +fi From patchwork Thu Jul 18 12:49:21 2024 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000017.mail.protection.outlook.com (10.167.244.122) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.5 via Frontend Transport; Thu, 18 Jul 2024 12:50:49 +0000 Received: from ethanolx16dchost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 18 Jul 2024 07:50:49 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 05/16] x86 AMD SEV-SNP: Enable SEV-SNP support Date: Thu, 18 Jul 2024 07:49:21 -0500 Message-ID: <20240718124932.114121-6-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000017:EE_|CH3PR12MB9282:EE_ X-MS-Office365-Filtering-Correlation-Id: 2065fb3e-1a63-402a-79ca-08dca7284061 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:50:49.9490 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2065fb3e-1a63-402a-79ca-08dca7284061 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000017.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9282 Incorporate support for SEV-SNP enablement. Provide a simple activation test to determine whether SEV-SNP is enabled or not. SKIP this activation test if the guest is not an SEV-SNP guest. Besides, for SEV-SNP, the requirement is that SEV-ES and SEV be enabled. In addition, setup_vc_handler() is common to both SEV-ES and SEV-SNP. Therefore, call setup_vc_handler() only when SEV-ES is enabled. Signed-off-by: Pavan Kumar Paluri --- lib/x86/amd_sev.c | 15 +++++++++++++++ lib/x86/amd_sev.h | 2 ++ lib/x86/setup.c | 13 ++++++++++--- x86/amd_sev.c | 13 +++++++++++++ 4 files changed, 40 insertions(+), 3 deletions(-) diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c index ff435c90eeea..f84230eba2a4 100644 --- a/lib/x86/amd_sev.c +++ b/lib/x86/amd_sev.c @@ -89,6 +89,21 @@ bool amd_sev_es_enabled(void) return sev_es_enabled; } +bool amd_sev_snp_enabled(void) +{ + static bool sev_snp_enabled; + static bool initialized; + + if (!initialized) { + if (amd_sev_es_enabled()) + sev_snp_enabled = rdmsr(MSR_SEV_STATUS) & + SEV_SNP_ENABLED_MASK; + initialized = true; + } + + return sev_snp_enabled; +} + efi_status_t setup_vc_handler(void) { struct descriptor_table_ptr idtr; diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index b5715082284b..4c58e761c4af 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -122,6 +122,7 @@ struct es_em_ctxt { #define MSR_SEV_STATUS 0xc0010131 #define SEV_ENABLED_MASK 0b1 #define SEV_ES_ENABLED_MASK 0b10 +#define SEV_SNP_ENABLED_MASK 0b100 bool amd_sev_enabled(void); efi_status_t setup_amd_sev(void); @@ -140,6 +141,7 @@ efi_status_t setup_amd_sev(void); bool amd_sev_es_enabled(void); efi_status_t setup_vc_handler(void); +bool amd_sev_snp_enabled(void); void setup_ghcb_pte(pgd_t *page_table); void handle_sev_es_vc(struct ex_regs *regs); diff --git a/lib/x86/setup.c b/lib/x86/setup.c index d79a9f86eda4..561397af93d5 100644 --- a/lib/x86/setup.c +++ b/lib/x86/setup.c @@ -331,9 +331,16 @@ efi_status_t setup_efi(efi_bootinfo_t *efi_bootinfo) phase = "AMD SEV"; status = setup_amd_sev(); - /* Continue if AMD SEV is not supported, but skip SEV-ES setup */ - if (status == EFI_SUCCESS) { - phase = "AMD SEV-ES"; + /* + * Continue if AMD SEV is not supported, but skip SEV-ES or + * SEV-SNP setup. + * setup_vc_handler() already checks whether SEV-ES is enabled + * or not before it does anything. However, for an SEV-guest, a + * function call to setup_vc_handler() can be avoided altogether + * by incorporating amd_sev_es_enabled() check below. + */ + if (status == EFI_SUCCESS && amd_sev_es_enabled()) { + phase = amd_sev_snp_enabled() ? "AMD SEV-SNP" : "AMD SEV-ES"; status = setup_vc_handler(); } diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 7757d4f85b7a..3e6e9129cfaa 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -69,6 +69,18 @@ static void test_sev_es_activation(void) } } +static void test_sev_snp_activation(void) +{ + report_info("TEST: SEV-SNP Activation test"); + + if (!(rdmsr(MSR_SEV_STATUS) & SEV_SNP_ENABLED_MASK)) { + report_skip("SEV-SNP is not enabled"); + return; + } + + report_info("SEV-SNP is enabled"); +} + static void test_stringio(void) { int st1_len = sizeof(st1) - 1; @@ -92,6 +104,7 @@ int main(void) rtn = test_sev_activation(); report(rtn == EXIT_SUCCESS, "SEV activation test."); test_sev_es_activation(); + test_sev_snp_activation(); test_stringio(); return report_summary(); } From patchwork Thu Jul 18 12:49:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736457 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2069.outbound.protection.outlook.com [40.107.220.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0333913AA26 for ; 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Thu, 18 Jul 2024 07:50:59 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 06/16] x86 AMD SEV-SNP: Add tests for presence of confidential computing blob Date: Thu, 18 Jul 2024 07:49:22 -0500 Message-ID: <20240718124932.114121-7-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000018:EE_|DS0PR12MB7679:EE_ X-MS-Office365-Filtering-Correlation-Id: c9d9067d-1ef0-405b-e35b-08dca728473e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; 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The SEV-SNP Confidential Computing (CC) blob (GHCB spec, Table-5) contains metadata that needs to remain accessible during the guest's lifetime. The metadata contains information on SNP reserved pages such as pointers to SNP secrets page and SNP CPUID table. Having access to SNP CPUID table aids in providing CPUID #VC handler support. Also, Determining the presence of SNP CC blob in KUT guest verfies whether OVMF has properly provided the CC blob to the guest via the system configuration table. Put out a warning message in case the CC blob is not found. Import the definitions of CC_BLOB_SEV_HDR_MAGIC and cc_blob_sev_info structure from upstream linux (arch/x86/include/asm/sev.h). Signed-off-by: Pavan Kumar Paluri --- lib/linux/efi.h | 1 + lib/x86/amd_sev.h | 18 ++++++++++++++++++ x86/amd_sev.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/lib/linux/efi.h b/lib/linux/efi.h index 8fa23ad078ce..64323ff498f5 100644 --- a/lib/linux/efi.h +++ b/lib/linux/efi.h @@ -69,6 +69,7 @@ typedef guid_t efi_guid_t; #define DEVICE_TREE_GUID EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0) #define LOADED_IMAGE_PROTOCOL_GUID EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) +#define EFI_CC_BLOB_GUID EFI_GUID(0x067b1f5f, 0xcf26, 0x44c5, 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42) #define EFI_LOAD_FILE2_PROTOCOL_GUID EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d) #define LINUX_EFI_INITRD_MEDIA_GUID EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, 0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68) diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index 4c58e761c4af..70f3763fe231 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -106,6 +106,24 @@ struct es_em_ctxt { struct es_fault_info fi; }; +/* + * AMD SEV Confidential computing blob structure. The structure is + * defined in OVMF UEFI firmware header: + * https://github.com/tianocore/edk2/blob/master/OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h + */ +#define CC_BLOB_SEV_HDR_MAGIC 0x45444d41 +struct cc_blob_sev_info { + u32 magic; + u16 version; + u16 reserved; + u64 secrets_phys; + u32 secrets_len; + u32 rsvd1; + u64 cpuid_phys; + u32 cpuid_len; + u32 rsvd2; +} __packed; + /* * AMD Programmer's Manual Volume 3 * - Section "Function 8000_0000h - Maximum Extended Function Number and Vendor String" diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 3e6e9129cfaa..4c34a5965a1b 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -69,8 +69,35 @@ static void test_sev_es_activation(void) } } +/* Check to find if SEV-SNP's Confidential Computing Blob is present */ +static efi_status_t find_cc_blob_efi(void) +{ + struct cc_blob_sev_info *snp_cc_blob; + efi_status_t status; + + status = efi_get_system_config_table(EFI_CC_BLOB_GUID, + (void **)&snp_cc_blob); + + if (status != EFI_SUCCESS) + return status; + + if (!snp_cc_blob) { + printf("SEV-SNP CC blob not found\n"); + return EFI_NOT_FOUND; + } + + if (snp_cc_blob->magic != CC_BLOB_SEV_HDR_MAGIC) { + printf("SEV-SNP CC blob header/signature mismatch"); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + static void test_sev_snp_activation(void) { + efi_status_t status; + report_info("TEST: SEV-SNP Activation test"); if (!(rdmsr(MSR_SEV_STATUS) & SEV_SNP_ENABLED_MASK)) { @@ -79,6 +106,9 @@ static void test_sev_snp_activation(void) } report_info("SEV-SNP is enabled"); + + status = find_cc_blob_efi(); + report(status == EFI_SUCCESS, "SEV-SNP CC-blob presence"); } static void test_stringio(void) From patchwork Thu Jul 18 12:49:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736458 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2047.outbound.protection.outlook.com [40.107.92.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21F8054645 for ; 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Thu, 18 Jul 2024 07:51:10 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 07/16] x86 AMD SEV-ES: Set GHCB page attributes for a new page table Date: Thu, 18 Jul 2024 07:49:23 -0500 Message-ID: <20240718124932.114121-8-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000012:EE_|SA1PR12MB7175:EE_ X-MS-Office365-Filtering-Correlation-Id: b389d7b8-7643-457d-bb27-08dca7284d49 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:51:11.6194 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b389d7b8-7643-457d-bb27-08dca7284d49 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000012.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7175 SEV-ES/SNP guest uses GHCB page to communicate with the host. Such a page should remain unencrypted (its C-bit should be unset in the guest page table). Therefore, call setup_ghcb_pte() in the path of setup_vm() to ensure C-bit of GHCB's pte is unset for a new page table that will be setup as a part of page allocation for UEFI-based SEV-ES/SNP tests later on. It is important to note that setup_ghcb_pte() is also called from setup_page_table() in lib/x86/setup.c. However, page allocation callers return a null address (0x0) for UEFI based tests with the initial page table setup via this path. Hence, a new page table is setup via setup_vm() to allocate valid pages. Signed-off-by: Pavan Kumar Paluri --- lib/x86/vm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index 90f73fbb2dfd..ce2063aee75d 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -3,6 +3,7 @@ #include "vmalloc.h" #include "alloc_page.h" #include "smp.h" +#include "amd_sev.h" static pteval_t pte_opt_mask; @@ -197,6 +198,11 @@ void *setup_mmu(phys_addr_t end_of_memory, void *opt_mask) init_alloc_vpage((void*)(3ul << 30)); #endif +#ifdef CONFIG_EFI + if (amd_sev_es_enabled()) + setup_ghcb_pte(cr3); +#endif + write_cr3(virt_to_phys(cr3)); #ifndef __x86_64__ write_cr4(X86_CR4_PSE); From patchwork Thu Jul 18 12:49:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736459 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2054.outbound.protection.outlook.com [40.107.100.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 814B213A407 for ; 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Thu, 18 Jul 2024 07:51:21 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 08/16] x86 AMD SEV-SNP: Test Private->Shared page state changes using GHCB MSR Date: Thu, 18 Jul 2024 07:49:24 -0500 Message-ID: <20240718124932.114121-9-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000012:EE_|MW6PR12MB7087:EE_ X-MS-Office365-Filtering-Correlation-Id: 736c568e-952b-43a3-0794-08dca72853d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:51:22.5724 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 736c568e-952b-43a3-0794-08dca72853d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000012.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7087 As mentioned in the GHCB spec (Section 2.3.1 GHCB MSR protocol), the page state change GHCB MSR protocol is used to convert a 4K page from private to shared or vice-versa. Add support for this test by allocating a total of 1024 4K pages to ensure the test can handle large cases. The purpose of this test is to determine whether the hypervisor changes the page state to shared when using the MSR protocol. Before the conversion test, ensure the state of the pages are in an expected state (i.e., private) by issuing a re-validation on one of the newly allocated page to determine the expected state of the page matches with the page's current state. Report failure if the expected page state is not private. After the page state conversion to shared by the hypervisor, ensure the state of the pages are in shared by writing data to these pages while the C-bit in its PTEs is not set. Report a failure otherwise. Provide support for cleaning up the physical pages by converting the pages to default guest-owned state before freeing them. Import GHCB MSR PSC related and pvalidate definitions from upstream linux. (arch/x86/inlcude/asm/sev-common.h and arch/x86/include/asm/sev.h) Signed-off-by: Pavan Kumar Paluri --- lib/asm-generic/page.h | 2 + lib/x86/amd_sev.c | 158 +++++++++++++++++++++++++++++++++++++++++ lib/x86/amd_sev.h | 69 ++++++++++++++++++ lib/x86/vm.h | 3 + x86/amd_sev.c | 88 +++++++++++++++++++++++ 5 files changed, 320 insertions(+) diff --git a/lib/asm-generic/page.h b/lib/asm-generic/page.h index 5ed086129657..ed9be58e31d0 100644 --- a/lib/asm-generic/page.h +++ b/lib/asm-generic/page.h @@ -14,6 +14,8 @@ #define PAGE_SHIFT 12 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) +#define LARGE_PAGE_SIZE (512 * PAGE_SIZE) +#define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE - 1)) #ifndef __ASSEMBLY__ diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c index f84230eba2a4..5cbdeb35bba8 100644 --- a/lib/x86/amd_sev.c +++ b/lib/x86/amd_sev.c @@ -12,6 +12,8 @@ #include "amd_sev.h" #include "x86/processor.h" #include "x86/vm.h" +#include "vmalloc.h" +#include "alloc_page.h" static unsigned short amd_sev_c_bit_pos; phys_addr_t ghcb_addr; @@ -188,3 +190,159 @@ unsigned long long get_amd_sev_addr_upperbound(void) return PT_ADDR_UPPER_BOUND_DEFAULT; } } + +void set_pte_decrypted(unsigned long vaddr, int npages) +{ + pteval_t *pte; + unsigned long vaddr_end = vaddr + (npages * PAGE_SIZE); + + while (vaddr < vaddr_end) { + pte = get_pte((pgd_t *)read_cr3(), (void *)vaddr); + + if (!pte) + assert_msg(pte, "No pte found for vaddr 0x%lx", vaddr); + + /* unset C-bit */ + *pte &= ~get_amd_sev_c_bit_mask(); + + vaddr += PAGE_SIZE; + } + + flush_tlb(); +} + +void set_pte_encrypted(unsigned long vaddr, int npages) +{ + pteval_t *pte; + unsigned long vaddr_end = vaddr + (npages * PAGE_SIZE); + + while (vaddr < vaddr_end) { + pte = get_pte((pgd_t *)read_cr3(), (void *)vaddr); + + if (!pte) + assert_msg(pte, "No pte found for vaddr 0x%lx", vaddr); + + /* set C-bit */ + *pte |= get_amd_sev_c_bit_mask(); + + vaddr += PAGE_SIZE; + } + + flush_tlb(); +} + +int pvalidate(unsigned long vaddr, bool rmp_size, bool validate) +{ + bool rmp_unchanged; + int result; + + asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t" + CC_SET(c) + : CC_OUT(c) (rmp_unchanged), "=a" (result) + : "a" (vaddr), "c" (rmp_size), "d" (validate) + : "memory", "cc"); + + if (rmp_unchanged) + return PVALIDATE_FAIL_NOUPDATE; + + return result; +} + +bool is_validated_private_page(unsigned long vaddr, bool rmp_size) +{ + int ret; + + /* Attempt a PVALIDATE here for the provided page size */ + ret = pvalidate(vaddr, rmp_size, true); + if (ret == PVALIDATE_FAIL_NOUPDATE) + return true; + + /* + * If PVALIDATE_FAIL_SIZEMISMATCH, entry in the RMP is 4K and + * what guest is providing is a 2M entry. Therefore, fallback + * to pvalidating 4K entries within 2M range. + */ + if (rmp_size && ret == PVALIDATE_FAIL_SIZEMISMATCH) { + unsigned long vaddr_end = vaddr + LARGE_PAGE_SIZE; + + for (; vaddr < vaddr_end; vaddr += PAGE_SIZE) { + ret = pvalidate(vaddr, RMP_PG_SIZE_4K, true); + if (ret != PVALIDATE_FAIL_NOUPDATE) + return false; + } + + return true; + } + + return false; +} + +enum es_result __sev_set_pages_state_msr_proto(unsigned long vaddr, int npages, + int operation) +{ + unsigned long vaddr_end = vaddr + (npages * PAGE_SIZE); + unsigned long paddr; + int ret; + unsigned long val; + + /* + * GHCB maybe established at this point, so save and restore the + * current value which will be overwritten by the MSR protocol + * request. + */ + phys_addr_t ghcb_old_msr = rdmsr(SEV_ES_GHCB_MSR_INDEX); + + while (vaddr < vaddr_end) { + paddr = __pa(vaddr); + + if (operation == SNP_PAGE_STATE_SHARED) { + ret = pvalidate(vaddr, RMP_PG_SIZE_4K, false); + if (ret) { + printf("Failed to invalidate vaddr: 0x%lx, ret: %d\n", + vaddr, ret); + wrmsr(SEV_ES_GHCB_MSR_INDEX, ghcb_old_msr); + return ES_UNSUPPORTED; + } + } + + wrmsr(SEV_ES_GHCB_MSR_INDEX, + GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, operation)); + + VMGEXIT(); + + val = rdmsr(SEV_ES_GHCB_MSR_INDEX); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP) { + printf("Incorrect PSC response code: 0x%x\n", + (unsigned int)GHCB_RESP_CODE(val)); + wrmsr(SEV_ES_GHCB_MSR_INDEX, ghcb_old_msr); + return ES_VMM_ERROR; + } + + if (GHCB_MSR_PSC_RESP_VAL(val)) { + printf("Failed to change page state to %s paddr: 0x%lx error: 0x%llx\n", + operation == SNP_PAGE_STATE_PRIVATE ? "private" : + "shared", + paddr, GHCB_MSR_PSC_RESP_VAL(val)); + wrmsr(SEV_ES_GHCB_MSR_INDEX, ghcb_old_msr); + return ES_VMM_ERROR; + } + + if (operation == SNP_PAGE_STATE_PRIVATE) { + ret = pvalidate(vaddr, RMP_PG_SIZE_4K, true); + if (ret) { + printf("Failed to validate vaddr: 0x%lx, ret: %d\n", + vaddr, ret); + wrmsr(SEV_ES_GHCB_MSR_INDEX, ghcb_old_msr); + return ES_UNSUPPORTED; + } + } + + vaddr += PAGE_SIZE; + } + + /* Restore old GHCB msr - setup by OVMF */ + wrmsr(SEV_ES_GHCB_MSR_INDEX, ghcb_old_msr); + + return ES_OK; +} diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index 70f3763fe231..04c569be57eb 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -84,6 +84,16 @@ struct ghcb { #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } +/* PVALIDATE return codes */ +#define PVALIDATE_FAIL_SIZEMISMATCH 6 + +/* Software defined (when rFlags.CF = 1) */ +#define PVALIDATE_FAIL_NOUPDATE 255 + +/* RMP page size */ +#define RMP_PG_SIZE_4K 0 +#define RMP_PG_SIZE_2M 1 + enum es_result { ES_OK, /* All good */ ES_UNSUPPORTED, /* Requested operation not supported */ @@ -106,6 +116,13 @@ struct es_em_ctxt { struct es_fault_info fi; }; +/* + * Assign a large enough order to run SEV-SNP based tests for 4K as well + * as 2M ranges + */ +#define SEV_ALLOC_ORDER 10 +#define SEV_ALLOC_PAGE_COUNT 1 << SEV_ALLOC_ORDER + /* * AMD SEV Confidential computing blob structure. The structure is * defined in OVMF UEFI firmware header: @@ -157,15 +174,67 @@ efi_status_t setup_amd_sev(void); */ #define SEV_ES_GHCB_MSR_INDEX 0xc0010130 +#define GHCB_DATA_LOW 12 +#define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1) +#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) + +/* + * SNP Page State Change Operation + * + * GHCBData[55:52] - Page operation: + * 0x0001 Page assignment, Private + * 0x0002 Page assignment, Shared + * 0x0003 PSMASH + * 0x0004 UNSMASH + */ +enum psc_op { + SNP_PAGE_STATE_PRIVATE = 1, + SNP_PAGE_STATE_SHARED, + SNP_PAGE_STATE_PSMASH, + SNP_PAGE_STATE_UNSMASH, +}; + +#define GHCB_MSR_PSC_REQ 0x14 +#define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ + /* GHCBData[55:52] */ \ + (((u64)((op) & 0xf) << 52) | \ + /* GHCBData[51:12] */ \ + ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \ + /* GHCBData[11:0] */ \ + GHCB_MSR_PSC_REQ) + +#define GHCB_MSR_PSC_RESP 0x15 +#define GHCB_MSR_PSC_RESP_VAL(val) \ + /* GHCBData[63:32] */ \ + (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) + bool amd_sev_es_enabled(void); efi_status_t setup_vc_handler(void); bool amd_sev_snp_enabled(void); void setup_ghcb_pte(pgd_t *page_table); void handle_sev_es_vc(struct ex_regs *regs); +int pvalidate(unsigned long vaddr, bool rmp_size, bool validate); +void set_pte_decrypted(unsigned long vaddr, int npages); +void set_pte_encrypted(unsigned long vaddr, int npages); +bool is_validated_private_page(unsigned long vaddr, bool rmp_size); +enum es_result __sev_set_pages_state_msr_proto(unsigned long vaddr, + int npages, int operation); unsigned long long get_amd_sev_c_bit_mask(void); unsigned long long get_amd_sev_addr_upperbound(void); +/* + * Macros to generate condition code outputs from inline assembly, + * The output operand must be type "bool". + */ +#ifdef __GCC_ASM_FLAG_OUTPUTS__ +# define CC_SET(c) "\n\t/* output condition code " #c "*/\n" +# define CC_OUT(c) "=@cc" #c +#else +# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n" +# define CC_OUT(c)[_cc_ ## c] "=qm" +#endif + /* GHCB Accessor functions from Linux's include/asm/svm.h */ #define GHCB_BITMAP_IDX(field) \ (offsetof(struct ghcb_save_area, field) / sizeof(u64)) diff --git a/lib/x86/vm.h b/lib/x86/vm.h index cf39787aa8b0..a5bd8d4ecf7c 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -7,6 +7,9 @@ #include "asm/io.h" #include "asm/bitops.h" +#define ORDER_4K 0 +#define ORDER_2M 9 + void setup_5level_page_table(void); struct pte_search { diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 4c34a5965a1b..3b1593e42634 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -14,6 +14,9 @@ #include "x86/processor.h" #include "x86/amd_sev.h" #include "msr.h" +#include "vmalloc.h" +#include "x86/vm.h" +#include "alloc_page.h" #define EXIT_SUCCESS 0 #define EXIT_FAILURE 1 @@ -128,6 +131,85 @@ static void test_stringio(void) report((got & 0xff00) >> 8 == st1[sizeof(st1) - 2], "outsb up"); } +static enum es_result sev_set_pages_state_msr_proto(unsigned long vaddr, + int npages, int operation) +{ + efi_status_t status; + + vaddr &= PAGE_MASK; + + if (operation == SNP_PAGE_STATE_SHARED) { + status = __sev_set_pages_state_msr_proto(vaddr, npages, operation); + + if (status != ES_OK) { + printf("Page state change (private->shared) failure"); + return status; + } + + set_pte_decrypted(vaddr, npages); + } else { + set_pte_encrypted(vaddr, npages); + + status = __sev_set_pages_state_msr_proto(vaddr, npages, operation); + + if (status != ES_OK) { + printf("Page state change (shared->private) failure.\n"); + return status; + } + } + + return ES_OK; +} + +static int test_write(unsigned long vaddr, int npages) +{ + unsigned long vaddr_end = vaddr + (npages << PAGE_SHIFT); + + while (vaddr < vaddr_end) { + memcpy((void *)vaddr, st1, strnlen(st1, PAGE_SIZE)); + vaddr += PAGE_SIZE; + } + + return 0; +} + +static void test_sev_psc_ghcb_msr(void) +{ + void *vaddr; + efi_status_t status; + + report_info("TEST: GHCB MSR based Page state change test"); + + vaddr = alloc_pages(SEV_ALLOC_ORDER); + force_4k_page(vaddr); + + report(is_validated_private_page((unsigned long)vaddr, RMP_PG_SIZE_4K), + "Expected page state: Private"); + + status = sev_set_pages_state_msr_proto((unsigned long)vaddr, + SEV_ALLOC_PAGE_COUNT, + SNP_PAGE_STATE_SHARED); + + report(status == ES_OK, "Private->Shared Page state change for %d pages", + SEV_ALLOC_PAGE_COUNT); + + /* + * Access the now-shared page(s) with C-bit cleared and ensure + * writes to these pages are successful + */ + report(!test_write((unsigned long)vaddr, SEV_ALLOC_PAGE_COUNT), + "Write to %d unencrypted 4K pages after private->shared conversion", + (SEV_ALLOC_PAGE_COUNT) / (1 << ORDER_4K)); + + /* convert the pages back to private after PSC */ + status = sev_set_pages_state_msr_proto((unsigned long)vaddr, + SEV_ALLOC_PAGE_COUNT, + SNP_PAGE_STATE_PRIVATE); + + /* Free up all the pages */ + free_pages_by_order(vaddr, SEV_ALLOC_ORDER); +} + int main(void) { int rtn; @@ -136,5 +218,11 @@ int main(void) test_sev_es_activation(); test_sev_snp_activation(); test_stringio(); + + /* Setup a new page table via setup_vm() */ + setup_vm(); + if (amd_sev_snp_enabled()) + test_sev_psc_ghcb_msr(); + return report_summary(); } From patchwork Thu Jul 18 12:49:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736460 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2055.outbound.protection.outlook.com [40.107.223.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A9A054645 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:51:33.3227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fc6a028-9fb8-48a5-64f1-08dca7285a39 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000014.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7415 Perform the translation of a guest virtual address to a guest physical address using the currently installed page tables. This must be used for virtual addresses that are not identity mapped addresses, e.g. a virtual address returned by alloc_vpage(), where virt_to_phys() won't work. Signed-off-by: Pavan Kumar Paluri --- lib/x86/vm.c | 24 ++++++++++++++++++++++++ lib/x86/vm.h | 1 + 2 files changed, 25 insertions(+) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index ce2063aee75d..078665b2faf4 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -332,3 +332,27 @@ void walk_pte(void *virt, size_t len, pte_callback_t callback) callback(search, (void *)curr); } } + +unsigned long pgtable_va_to_pa(unsigned long va) +{ + pteval_t *pt = (pgd_t *)read_cr3(); + unsigned long offset, paddr; + int level; + + for (level = PAGE_LEVEL; level; level--) { + offset = PGDIR_OFFSET((uintptr_t)va, level); + assert_msg(pt[offset], "PTE absent"); + + if (level == 1 || + (level <= 3 && (pt[offset] & PT_PAGE_SIZE_MASK))) { + paddr = pt[offset] & PT_ADDR_MASK; + paddr += va & ((1UL << PGDIR_BITS(level)) - 1); + + return paddr; + } + + pt = phys_to_virt(pt[offset] & PT_ADDR_MASK); + } + + __builtin_unreachable(); +} diff --git a/lib/x86/vm.h b/lib/x86/vm.h index a5bd8d4ecf7c..9f72c267086d 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -59,6 +59,7 @@ static inline void *current_page_table(void) void split_large_page(unsigned long *ptep, int level); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:51:44.1517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b87e2693-4d76-41df-c39a-08dca72860ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000017.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6552 Introduce install_large_pages() helper similar to install_pages(), that is helpful while dealing with more than 1 2M large page mappings. This helper is useful when running SEV-SNP VMGEXIT PSC tests that deal with a bunch of 2M pages. Signed-off-by: Pavan Kumar Paluri --- lib/x86/vm.c | 14 ++++++++++++++ lib/x86/vm.h | 1 + 2 files changed, 15 insertions(+) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index 078665b2faf4..cfca452bb110 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -128,6 +128,20 @@ void install_pages(pgd_t *cr3, phys_addr_t phys, size_t len, void *virt) } } +void install_large_pages(pgd_t *cr3, phys_addr_t phys, size_t len, void *virt) +{ + phys_addr_t max = (u64)len + (u64)phys; + assert(phys % LARGE_PAGE_SIZE == 0); + assert((uintptr_t)virt % LARGE_PAGE_SIZE == 0); + assert(len % LARGE_PAGE_SIZE == 0); + + while (phys + LARGE_PAGE_SIZE <= max) { + install_large_page(cr3, phys, virt); + phys += LARGE_PAGE_SIZE; + virt = (char *)virt + LARGE_PAGE_SIZE; + } +} + bool any_present_pages(pgd_t *cr3, void *virt, size_t len) { uintptr_t max = (uintptr_t) virt + len; diff --git a/lib/x86/vm.h b/lib/x86/vm.h index 9f72c267086d..0216ea1f37f9 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -41,6 +41,7 @@ pteval_t *install_pte(pgd_t *cr3, pteval_t *install_large_page(pgd_t *cr3, phys_addr_t phys, void *virt); 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Thu, 18 Jul 2024 12:51:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000018.mail.protection.outlook.com (10.167.244.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.5 via Frontend Transport; Thu, 18 Jul 2024 12:51:54 +0000 Received: from ethanolx16dchost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 18 Jul 2024 07:51:54 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 11/16] x86 AMD SEV-SNP: Change guest pages from Private->Shared using GHCB NAE Date: Thu, 18 Jul 2024 07:49:27 -0500 Message-ID: <20240718124932.114121-12-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000018:EE_|DS0PR12MB8341:EE_ X-MS-Office365-Filtering-Correlation-Id: b59e1ac9-cfd7-4357-111a-08dca7286720 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:51:54.9515 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b59e1ac9-cfd7-4357-111a-08dca7286720 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000018.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8341 As mentioned in the GHCB spec (Section 4 GHCB protocol, Table-5 SNP page state change), perform page state change conversions on a user inputted number of pages from private to hypervisor-owned. The page state change NAE event allows for SEV-SNP guest to request page state changes to hypervisor using GHCB protocol. The test handles both 4K pages and 2M large pages, depending on the order specified and whether the address of the page is 2M aligned or not. If 2M range is backed by a 4K page, 'pvalidate' fails with FAIL_SIZEMISMATCH error. In such a case, the guest tries to pvalidate all the 4K entries in this 2M range. Conduct a test to re-validate the private page before conversion to ensure PVALIDATE_FAIL_NOUPDATE is met, indicating that expected page state is met. Then, perform the page state conversions, unset the C-bits on these pages and write data to the shared guest pages post page state conversions with C-bits unset appropriately to ensure pages are in expected shared state. Signed-off-by: Pavan Kumar Paluri --- lib/x86/amd_sev.c | 168 +++++++++++++++++++++++++++++++++++++++++++ lib/x86/amd_sev.h | 27 +++++++ lib/x86/amd_sev_vc.c | 2 +- lib/x86/svm.h | 1 + lib/x86/vm.c | 26 +++++++ lib/x86/vm.h | 1 + x86/amd_sev.c | 78 +++++++++++++++++++- 7 files changed, 301 insertions(+), 2 deletions(-) diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c index 5cbdeb35bba8..e2f99bc8eded 100644 --- a/lib/x86/amd_sev.c +++ b/lib/x86/amd_sev.c @@ -346,3 +346,171 @@ enum es_result __sev_set_pages_state_msr_proto(unsigned long vaddr, int npages, return ES_OK; } + +static void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr) +{ + struct psc_entry *entry; + int ret, i; + unsigned long vaddr; + bool validate; + + for (i = 0; i <= desc->hdr.end_entry; i++) { + vaddr = vaddr_arr[i]; + entry = &desc->entries[i]; + validate = entry->operation == SNP_PAGE_STATE_PRIVATE ? true : false; + + ret = pvalidate(vaddr, entry->pagesize, validate); + if (ret == PVALIDATE_FAIL_SIZEMISMATCH) { + assert(entry->pagesize == RMP_PG_SIZE_2M); + unsigned long vaddr_end = vaddr + LARGE_PAGE_SIZE; + + for (; vaddr < vaddr_end; vaddr += PAGE_SIZE) { + ret = pvalidate(vaddr, RMP_PG_SIZE_4K, validate); + if (ret) + break; + } + } + assert(!ret); + } +} + +static int verify_exception(struct ghcb *ghcb) +{ + return ghcb->save.sw_exit_info_1 & GENMASK_ULL(31, 0); +} + +static int sev_ghcb_hv_call(struct ghcb *ghcb, u64 exit_code, + u64 exit_info_1, u64 exit_info_2) +{ + ghcb->version = GHCB_PROTOCOL_MAX; + ghcb->ghcb_usage = GHCB_DEFAULT_USAGE; + + ghcb_set_sw_exit_code(ghcb, exit_code); + ghcb_set_sw_exit_info_1(ghcb, exit_info_1); + ghcb_set_sw_exit_info_2(ghcb, exit_info_2); + + VMGEXIT(); + + return verify_exception(ghcb); +} + +static int vmgexit_psc(struct snp_psc_desc *desc, struct ghcb *ghcb) +{ + int cur_entry, end_entry, ret = 0; + struct snp_psc_desc *data; + + /* Ensure end_entry is within bounds */ + assert(desc->hdr.end_entry < VMGEXIT_PSC_MAX_ENTRY); + + vc_ghcb_invalidate(ghcb); + + data = (struct snp_psc_desc *)ghcb->shared_buffer; + memcpy(ghcb->shared_buffer, desc, GHCB_SHARED_BUF_SIZE); + + cur_entry = data->hdr.cur_entry; + end_entry = data->hdr.end_entry; + + while (data->hdr.cur_entry <= data->hdr.end_entry) { + ghcb_set_sw_scratch(ghcb, (u64)__pa(data)); + + ret = sev_ghcb_hv_call(ghcb, SVM_VMGEXIT_PSC, 0, 0); + + if (ret) { + report_info("SNP: PSC failed with ret: %d\n", ret); + ret = 1; + break; + } + + if (cur_entry > data->hdr.cur_entry) { + report_info("SNP: PSC processing going backward, cur_entry %d (got %d)\n", + cur_entry, data->hdr.cur_entry); + ret = 1; + break; + } + + if (data->hdr.end_entry != end_entry) { + report_info("End entry mismatch: end_entry %d (got %d)\n", + end_entry, data->hdr.end_entry); + ret = 1; + break; + } + + if (data->hdr.reserved) { + report_info("Reserved bit is set in the PSC header\n"); + ret = 1; + break; + } + } + + /* Copy the output in shared buffer back to desc */ + memcpy(desc, ghcb->shared_buffer, GHCB_SHARED_BUF_SIZE); + + return ret; +} + +static void add_psc_entry(struct snp_psc_desc *desc, u8 idx, u8 op, unsigned long vaddr, + bool large_entry, u16 cur_page_offset) +{ + struct psc_hdr *hdr = &desc->hdr; + struct psc_entry *entry = &desc->entries[idx]; + + assert_msg(!large_entry || IS_ALIGNED(vaddr, LARGE_PAGE_SIZE), + "Must use 2M-aligned addresses for large PSC entries"); + + entry->gfn = pgtable_va_to_pa(vaddr) >> PAGE_SHIFT; + entry->operation = op; + entry->pagesize = large_entry; + entry->cur_page = cur_page_offset; + hdr->end_entry = idx; +} + +unsigned long __sev_set_pages_state(struct snp_psc_desc *desc, unsigned long vaddr, + unsigned long vaddr_end, int op, + struct ghcb *ghcb, bool large_entry) +{ + unsigned long vaddr_arr[VMGEXIT_PSC_MAX_ENTRY]; + int ret, iter = 0, iter2 = 0; + u8 page_size; + + memset(desc, 0, sizeof(*desc)); + + report_info("%s: address start %lx end %lx op %d large %d", + __func__, vaddr, vaddr_end, op, large_entry); + + while (vaddr < vaddr_end && iter < ARRAY_SIZE(desc->entries)) { + vaddr_arr[iter] = vaddr; + + if (large_entry && IS_ALIGNED(vaddr, LARGE_PAGE_SIZE) && + (vaddr_end - vaddr) >= LARGE_PAGE_SIZE) { + add_psc_entry(desc, iter, op, vaddr, true, 0); + vaddr += LARGE_PAGE_SIZE; + } else { + add_psc_entry(desc, iter, op, vaddr, false, 0); + vaddr += PAGE_SIZE; + } + + iter++; + } + + if (op == SNP_PAGE_STATE_SHARED) + pvalidate_pages(desc, vaddr_arr); + + ret = vmgexit_psc(desc, ghcb); + assert_msg(!ret, "VMGEXIT failed with ret value: %d", ret); + + if (op == SNP_PAGE_STATE_PRIVATE) + pvalidate_pages(desc, vaddr_arr); + + for (iter2 = 0; iter2 < iter; iter2++) { + page_size = desc->entries[iter2].pagesize; + + if (page_size == RMP_PG_SIZE_2M) + assert_msg(desc->entries[iter2].cur_page == 512, + "Failed to process sub-entries within 2M range"); + else if (page_size == RMP_PG_SIZE_4K) + assert_msg(desc->entries[iter2].cur_page == 1, + "Failed to process 4K entry"); + } + + return vaddr; +} diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index 04c569be57eb..bf065ef613b7 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -208,6 +208,29 @@ enum psc_op { /* GHCBData[63:32] */ \ (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) +struct psc_hdr { + u16 cur_entry; + u16 end_entry; + u32 reserved; +}; + +struct psc_entry { + u64 cur_page : 12, + gfn : 40, + operation : 4, + pagesize : 1, + reserved : 7; +}; + +#define VMGEXIT_PSC_MAX_ENTRY \ + ((GHCB_SHARED_BUF_SIZE - sizeof(struct psc_hdr)) / \ + sizeof(struct psc_entry)) + +struct snp_psc_desc { + struct psc_hdr hdr; + struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY]; +}; + bool amd_sev_es_enabled(void); efi_status_t setup_vc_handler(void); bool amd_sev_snp_enabled(void); @@ -219,6 +242,10 @@ void set_pte_encrypted(unsigned long vaddr, int npages); bool is_validated_private_page(unsigned long vaddr, bool rmp_size); enum es_result __sev_set_pages_state_msr_proto(unsigned long vaddr, int npages, int operation); +unsigned long __sev_set_pages_state(struct snp_psc_desc *desc, unsigned long vaddr, + unsigned long vaddr_end, int op, + struct ghcb *ghcb, bool large_entry); +void vc_ghcb_invalidate(struct ghcb *ghcb); unsigned long long get_amd_sev_c_bit_mask(void); unsigned long long get_amd_sev_addr_upperbound(void); diff --git a/lib/x86/amd_sev_vc.c b/lib/x86/amd_sev_vc.c index 77892edd4678..cdbd7c0bc39c 100644 --- a/lib/x86/amd_sev_vc.c +++ b/lib/x86/amd_sev_vc.c @@ -11,7 +11,7 @@ extern phys_addr_t ghcb_addr; -static void vc_ghcb_invalidate(struct ghcb *ghcb) +void vc_ghcb_invalidate(struct ghcb *ghcb) { ghcb->save.sw_exit_code = 0; memset(ghcb->save.valid_bitmap, 0, sizeof(ghcb->save.valid_bitmap)); diff --git a/lib/x86/svm.h b/lib/x86/svm.h index e0aafe80a290..77061c0a1980 100644 --- a/lib/x86/svm.h +++ b/lib/x86/svm.h @@ -372,6 +372,7 @@ struct __attribute__ ((__packed__)) vmcb { #define SVM_EXIT_NPF 0x400 #define SVM_EXIT_ERR -1 +#define SVM_VMGEXIT_PSC 0x80000010 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index cfca452bb110..3547a1c26869 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -370,3 +370,29 @@ unsigned long pgtable_va_to_pa(unsigned long va) __builtin_unreachable(); } + +void *vmalloc_pages(int num_pages, int order, bool large_page) +{ + unsigned long length = num_pages * PAGE_SIZE; + pgd_t *cr3 = (pgd_t *)read_cr3(); + void *vaddr, *paddr; + + /* Allocate physical pages */ + paddr = alloc_pages(order); + assert(paddr); + + /* Allocate virtual pages */ + vaddr = alloc_vpages_aligned(num_pages, large_page ? ORDER_2M : ORDER_4K); + assert(vaddr); + + /* + * Create pagetable entries that map the newly assigned virtual + * pages to physical pages + */ + if (!large_page) + install_pages(cr3, __pa(paddr), length, vaddr); + else + install_large_pages(cr3, __pa(paddr), length, vaddr); + + return vaddr; +} diff --git a/lib/x86/vm.h b/lib/x86/vm.h index 0216ea1f37f9..dc77d3fcaa1c 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -61,6 +61,7 @@ static inline void *current_page_table(void) void split_large_page(unsigned long *ptep, int level); void force_4k_page(void *addr); unsigned long pgtable_va_to_pa(unsigned long vaddr); +void *vmalloc_pages(int num_pages, int order, bool large_page); struct vm_vcpu_info { u64 cr3; diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 3b1593e42634..15281835d0ef 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -173,6 +173,37 @@ static int test_write(unsigned long vaddr, int npages) return 0; } +static void sev_set_pages_state(unsigned long vaddr, int npages, int op, + struct ghcb *ghcb) +{ + struct snp_psc_desc desc; + unsigned long vaddr_end; + bool large_entry; + + vaddr &= PAGE_MASK; + vaddr_end = vaddr + (npages << PAGE_SHIFT); + + if (IS_ALIGNED(vaddr, LARGE_PAGE_SIZE)) + large_entry = true; + + while (vaddr < vaddr_end) { + vaddr = __sev_set_pages_state(&desc, vaddr, vaddr_end, + op, ghcb, large_entry); + } +} + +static void snp_free_pages(int order, int npages, unsigned long vaddr, + struct ghcb *ghcb) +{ + set_pte_encrypted(vaddr, SEV_ALLOC_PAGE_COUNT); + + /* Convert pages back to default guest-owned state */ + sev_set_pages_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE, ghcb); + + /* Free all the associated physical pages */ + free_pages_by_order((void *)pgtable_va_to_pa(vaddr), order); +} + static void test_sev_psc_ghcb_msr(void) { void *vaddr; @@ -210,6 +241,44 @@ static void test_sev_psc_ghcb_msr(void) free_pages_by_order(vaddr, SEV_ALLOC_ORDER); } +static void init_vpages(void) +{ + /* + * alloc_vpages_aligned() allocates contiguous virtual + * pages that grow downward from vfree_top, 0, and this is + * problematic for SNP related PSC tests because + * vaddr < vaddr_end using unsigned values causes an issue + * (vaddr_end is 0x0). To avoid this, allocate a dummy virtual + * page. + */ + alloc_vpages_aligned(1, 0); +} + +static void test_sev_psc_ghcb_nae(void) +{ + unsigned long vaddr; + struct ghcb *ghcb = (struct ghcb *)rdmsr(SEV_ES_GHCB_MSR_INDEX); + + report_info("TEST: GHCB Protocol based page state change test"); + + vaddr = (unsigned long)vmalloc_pages(SEV_ALLOC_PAGE_COUNT, + SEV_ALLOC_ORDER, RMP_PG_SIZE_2M); + + report(is_validated_private_page(vaddr, RMP_PG_SIZE_2M), + "Expected page state: Private"); + + sev_set_pages_state(vaddr, SEV_ALLOC_PAGE_COUNT, SNP_PAGE_STATE_SHARED, + ghcb); + + set_pte_decrypted(vaddr, SEV_ALLOC_PAGE_COUNT); + + report(!test_write((unsigned long)vaddr, SEV_ALLOC_PAGE_COUNT), + "Write to %d unencrypted 2M pages after private->shared conversion", + (SEV_ALLOC_PAGE_COUNT) / (1 << ORDER_2M)); + + snp_free_pages(SEV_ALLOC_ORDER, SEV_ALLOC_PAGE_COUNT, vaddr, ghcb); +} + int main(void) { int rtn; @@ -221,8 +290,15 @@ int main(void) /* Setup a new page table via setup_vm() */ setup_vm(); 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The test handles both 4K and 2M large pages depending on the order and the page size specified. While at it, make changes to pvalidate_pages() to not treat PVALIDATE_FAIL_NOUPDATE as an error when converting the already private pages as a part of cleanup process. Signed-off-by: Pavan Kumar Paluri --- lib/x86/amd_sev.c | 22 ++++++++++++++++------ lib/x86/amd_sev.h | 3 ++- x86/amd_sev.c | 23 +++++++++++++++++------ 3 files changed, 35 insertions(+), 13 deletions(-) diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c index e2f99bc8eded..c2f2a3f43193 100644 --- a/lib/x86/amd_sev.c +++ b/lib/x86/amd_sev.c @@ -347,7 +347,16 @@ enum es_result __sev_set_pages_state_msr_proto(unsigned long vaddr, int npages, return ES_OK; } -static void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr) +static bool pvalidate_failed(int result, bool allow_noupdate) +{ + if (result && (!allow_noupdate || result != PVALIDATE_FAIL_NOUPDATE)) + return true; + + return false; +} + +static void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr, + bool allow_noupdate) { struct psc_entry *entry; int ret, i; @@ -366,11 +375,11 @@ static void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr) for (; vaddr < vaddr_end; vaddr += PAGE_SIZE) { ret = pvalidate(vaddr, RMP_PG_SIZE_4K, validate); - if (ret) + if (pvalidate_failed(ret, allow_noupdate)) break; } } - assert(!ret); + assert(!pvalidate_failed(ret, allow_noupdate)); } } @@ -466,7 +475,8 @@ static void add_psc_entry(struct snp_psc_desc *desc, u8 idx, u8 op, unsigned lon unsigned long __sev_set_pages_state(struct snp_psc_desc *desc, unsigned long vaddr, unsigned long vaddr_end, int op, - struct ghcb *ghcb, bool large_entry) + struct ghcb *ghcb, bool large_entry, + bool allow_noupdate) { unsigned long vaddr_arr[VMGEXIT_PSC_MAX_ENTRY]; int ret, iter = 0, iter2 = 0; @@ -493,13 +503,13 @@ unsigned long __sev_set_pages_state(struct snp_psc_desc *desc, unsigned long vad } if (op == SNP_PAGE_STATE_SHARED) - pvalidate_pages(desc, vaddr_arr); + pvalidate_pages(desc, vaddr_arr, allow_noupdate); ret = vmgexit_psc(desc, ghcb); assert_msg(!ret, "VMGEXIT failed with ret value: %d", ret); if (op == SNP_PAGE_STATE_PRIVATE) - pvalidate_pages(desc, vaddr_arr); + pvalidate_pages(desc, vaddr_arr, allow_noupdate); for (iter2 = 0; iter2 < iter; iter2++) { page_size = desc->entries[iter2].pagesize; diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index bf065ef613b7..e180a269fb63 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -244,7 +244,8 @@ enum es_result __sev_set_pages_state_msr_proto(unsigned long vaddr, int npages, int operation); unsigned long __sev_set_pages_state(struct snp_psc_desc *desc, unsigned long vaddr, unsigned long vaddr_end, int op, - struct ghcb *ghcb, bool large_entry); + struct ghcb *ghcb, bool large_entry, + bool allow_noupdate); void vc_ghcb_invalidate(struct ghcb *ghcb); unsigned long long get_amd_sev_c_bit_mask(void); diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 15281835d0ef..12fe25dcdd0a 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -174,7 +174,7 @@ static int test_write(unsigned long vaddr, int npages) } static void sev_set_pages_state(unsigned long vaddr, int npages, int op, - struct ghcb *ghcb) + struct ghcb *ghcb, bool allow_noupdate) { struct snp_psc_desc desc; unsigned long vaddr_end; @@ -188,17 +188,19 @@ static void sev_set_pages_state(unsigned long vaddr, int npages, int op, while (vaddr < vaddr_end) { vaddr = __sev_set_pages_state(&desc, vaddr, vaddr_end, - op, ghcb, large_entry); + op, ghcb, large_entry, + allow_noupdate); } } static void snp_free_pages(int order, int npages, unsigned long vaddr, - struct ghcb *ghcb) + struct ghcb *ghcb, bool allow_noupdate) { set_pte_encrypted(vaddr, SEV_ALLOC_PAGE_COUNT); /* Convert pages back to default guest-owned state */ - sev_set_pages_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE, ghcb); + sev_set_pages_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE, ghcb, + allow_noupdate); /* Free all the associated physical pages */ free_pages_by_order((void *)pgtable_va_to_pa(vaddr), order); @@ -268,7 +270,7 @@ static void test_sev_psc_ghcb_nae(void) "Expected page state: Private"); sev_set_pages_state(vaddr, SEV_ALLOC_PAGE_COUNT, SNP_PAGE_STATE_SHARED, - ghcb); + ghcb, false); set_pte_decrypted(vaddr, SEV_ALLOC_PAGE_COUNT); @@ -276,7 +278,16 @@ static void test_sev_psc_ghcb_nae(void) "Write to %d unencrypted 2M pages after private->shared conversion", (SEV_ALLOC_PAGE_COUNT) / (1 << ORDER_2M)); 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Thu, 18 Jul 2024 07:52:15 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 13/16] x86 AMD SEV-SNP: Change guest pages from Intermix->Private using GHCB NAE Date: Thu, 18 Jul 2024 07:49:29 -0500 Message-ID: <20240718124932.114121-14-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000016:EE_|SN7PR12MB7156:EE_ X-MS-Office365-Filtering-Correlation-Id: 95b775f7-9cf3-4cb4-e846-08dca728740c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:52:16.6520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95b775f7-9cf3-4cb4-e846-08dca728740c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000016.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7156 The tests perform the following actions: 1. Allocates a 2M private page (512 4K entries) and converts the entire range to shared. 2. Performs a write operation on these un-encrypted pages. 3. Performs partial page state change conversions on the first 256 4K entries and conducts a re-validation test on one of these now-private entries to determine whether the current page state is private or not. 4. Converts the whole 2M range from an intermixed state to private and perform a re-validation check on the now-private 2M page. The goal of this test is to ensure 2M page state changes are handled properly even if 2M range contains a mix of private/shared pages. Signed-off-by: Pavan Kumar Paluri --- x86/amd_sev.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 12fe25dcdd0a..fc385613b993 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -290,6 +290,59 @@ static void test_sev_psc_ghcb_nae(void) snp_free_pages(SEV_ALLOC_ORDER, SEV_ALLOC_PAGE_COUNT, vaddr, ghcb, true); } +static void __test_sev_psc_private(unsigned long vaddr, struct ghcb *ghcb, + int npages, bool allow_noupdate) +{ + set_pte_encrypted(vaddr, npages); + + /* Convert the whole 2M range back to private */ + sev_set_pages_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE, ghcb, + allow_noupdate); + + report(is_validated_private_page(vaddr, RMP_PG_SIZE_2M), + "Expected page state: Private"); +} + +static void test_sev_psc_intermix(bool to_private) +{ + unsigned long vaddr; + struct ghcb *ghcb = (struct ghcb *)(rdmsr(SEV_ES_GHCB_MSR_INDEX)); + + /* Allocate a 2M private page */ + vaddr = (unsigned long)vmalloc_pages((SEV_ALLOC_PAGE_COUNT) / 2, + SEV_ALLOC_ORDER - 1, RMP_PG_SIZE_2M); + + /* Ensure pages are in private state by checking the page is private */ + report(is_validated_private_page(vaddr, RMP_PG_SIZE_2M), + "Expected page state: Private"); + + sev_set_pages_state(vaddr, (SEV_ALLOC_PAGE_COUNT) / 2, + SNP_PAGE_STATE_SHARED, ghcb, false); + + set_pte_decrypted(vaddr, (SEV_ALLOC_PAGE_COUNT) / 2); + + set_pte_encrypted(vaddr, (SEV_ALLOC_PAGE_COUNT) / 2); + /* Convert a bunch of sub-pages (256) to private and leave the rest shared */ + sev_set_pages_state(vaddr, 256, SNP_PAGE_STATE_PRIVATE, ghcb, false); + + report(is_validated_private_page(vaddr, RMP_PG_SIZE_4K), + "Expected page state: Private"); + + /* Now convert all the pages back to private */ + if (to_private) + __test_sev_psc_private(vaddr, ghcb, (SEV_ALLOC_PAGE_COUNT) / 2, true); + + /* Free up all the used pages */ + snp_free_pages(SEV_ALLOC_ORDER - 1, (SEV_ALLOC_PAGE_COUNT) / 2, + vaddr, ghcb, true); +} + +static void test_sev_psc_intermix_to_private(void) +{ + report_info("TEST: 2M Intermixed to Private PSC test"); + test_sev_psc_intermix(true); +} + int main(void) { int rtn; @@ -309,6 +362,7 @@ int main(void) init_vpages(); test_sev_psc_ghcb_msr(); test_sev_psc_ghcb_nae(); + test_sev_psc_intermix_to_private(); } return report_summary(); From patchwork Thu Jul 18 12:49:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736466 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2053.outbound.protection.outlook.com [40.107.93.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6867154645 for ; Thu, 18 Jul 2024 12:52:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721307156; cv=fail; b=SvnQdFLt+p/BW0LY9rBZiHu0gdevN2EMJZNSt/tZuADxejXwpYO3AGcx4Yt4bH03qAAeS/lUSGELnLTUPNQwf8HIkbb3z+hhRpPx0qHUJkFdy1oQ0+m7bsWkfu854TjQWahoMikTT8q1QYKJcPWUrkQAGrU3r09gQGgRzqdIhmE= ARC-Message-Signature: i=2; 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Thu, 18 Jul 2024 12:52:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000016.mail.protection.outlook.com (10.167.244.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.5 via Frontend Transport; Thu, 18 Jul 2024 12:52:32 +0000 Received: from ethanolx16dchost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 18 Jul 2024 07:52:31 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 14/16] x86 AMD SEV-SNP: Change guest pages from Intermix->Shared using GHCB NAE Date: Thu, 18 Jul 2024 07:49:30 -0500 Message-ID: <20240718124932.114121-15-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000016:EE_|CY5PR12MB6477:EE_ X-MS-Office365-Filtering-Correlation-Id: cba40fcb-82b7-4d02-04cd-08dca7287d88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:52:32.5583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cba40fcb-82b7-4d02-04cd-08dca7287d88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000016.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6477 The test performs the following actions: 1. Allocates a 2M private page (512 4K entries) and performs 2M private to shared conversion. 2. Performs partial page state changes (shared->private) on first 256 4K entries and conducts a re-validation ('pvalidate') check on one of these entries to ensure its state has been changed to private. 3. Performs PSC from intermixed state to shared state on the 2M large page. 4. Conducts a write test on the shared pages to ensure page state change has been successful. The main goal of this test is to ensure 2M page state changes are handled properly even if 2M range contains a mix of private/shared pages. Signed-off-by: Pavan Kumar Paluri --- x86/amd_sev.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/x86/amd_sev.c b/x86/amd_sev.c index fc385613b993..ae19f8ad6cc8 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -303,6 +303,21 @@ static void __test_sev_psc_private(unsigned long vaddr, struct ghcb *ghcb, "Expected page state: Private"); } +static void __test_sev_psc_shared(unsigned long vaddr, struct ghcb *ghcb, + int npages, bool allow_noupdate) +{ + /* Convert the whole 2M range to shared */ + sev_set_pages_state(vaddr, npages, SNP_PAGE_STATE_SHARED, ghcb, + allow_noupdate); + + set_pte_decrypted(vaddr, npages); + + /* Conduct a write test to ensure pages are in expected state */ + report(!test_write(vaddr, npages), + "Write to %d unencrypted 2M pages after private->shared conversion", + npages / (1 << ORDER_2M)); +} + static void test_sev_psc_intermix(bool to_private) { unsigned long vaddr; @@ -331,6 +346,8 @@ static void test_sev_psc_intermix(bool to_private) /* Now convert all the pages back to private */ if (to_private) __test_sev_psc_private(vaddr, ghcb, (SEV_ALLOC_PAGE_COUNT) / 2, true); + else + __test_sev_psc_shared(vaddr, ghcb, (SEV_ALLOC_PAGE_COUNT) / 2, true); /* Free up all the used pages */ snp_free_pages(SEV_ALLOC_ORDER - 1, (SEV_ALLOC_PAGE_COUNT) / 2, @@ -343,6 +360,12 @@ static void test_sev_psc_intermix_to_private(void) test_sev_psc_intermix(true); } +static void test_sev_psc_intermix_to_shared(void) +{ + report_info("TEST: 2M Intermixed to Shared PSC test"); + test_sev_psc_intermix(false); +} + int main(void) { int rtn; @@ -363,6 +386,7 @@ int main(void) test_sev_psc_ghcb_msr(); test_sev_psc_ghcb_nae(); test_sev_psc_intermix_to_private(); + test_sev_psc_intermix_to_shared(); } return report_summary(); From patchwork Thu Jul 18 12:49:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736467 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14EE713AA26 for ; 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Thu, 18 Jul 2024 07:52:47 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 15/16] x86 AMD SEV-SNP: Issue PSMASH/UNSMASH PSC requests on 2M ranges Date: Thu, 18 Jul 2024 07:49:31 -0500 Message-ID: <20240718124932.114121-16-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000016:EE_|BL3PR12MB6620:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e640ae8-cf74-4ea1-5c52-08dca72886fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:52:48.4333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e640ae8-cf74-4ea1-5c52-08dca72886fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000016.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6620 GHCB spec specifies that an SNP guest can submit PSMASH/UNSMASH hints to hypervisor via PSC requests. Include a test to create such a PSC request where KUT-SNP guest requests hypervisor to PSMASH/UNSMASH 2M ranges, to ensure hypervisor handles these requests without any issues. Signed-off-by: Pavan Kumar Paluri --- lib/x86/amd_sev.c | 10 +++---- lib/x86/amd_sev.h | 5 ++++ x86/amd_sev.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 5 deletions(-) diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c index c2f2a3f43193..468ed9eef943 100644 --- a/lib/x86/amd_sev.c +++ b/lib/x86/amd_sev.c @@ -355,8 +355,8 @@ static bool pvalidate_failed(int result, bool allow_noupdate) return false; } -static void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr, - bool allow_noupdate) +void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr, + bool allow_noupdate) { struct psc_entry *entry; int ret, i; @@ -403,7 +403,7 @@ static int sev_ghcb_hv_call(struct ghcb *ghcb, u64 exit_code, return verify_exception(ghcb); } -static int vmgexit_psc(struct snp_psc_desc *desc, struct ghcb *ghcb) +int vmgexit_psc(struct snp_psc_desc *desc, struct ghcb *ghcb) { int cur_entry, end_entry, ret = 0; struct snp_psc_desc *data; @@ -457,8 +457,8 @@ static int vmgexit_psc(struct snp_psc_desc *desc, struct ghcb *ghcb) return ret; } -static void add_psc_entry(struct snp_psc_desc *desc, u8 idx, u8 op, unsigned long vaddr, - bool large_entry, u16 cur_page_offset) +void add_psc_entry(struct snp_psc_desc *desc, u8 idx, u8 op, unsigned long vaddr, + bool large_entry, u16 cur_page_offset) { struct psc_hdr *hdr = &desc->hdr; struct psc_entry *entry = &desc->entries[idx]; diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h index e180a269fb63..8357a658d47d 100644 --- a/lib/x86/amd_sev.h +++ b/lib/x86/amd_sev.h @@ -247,6 +247,11 @@ unsigned long __sev_set_pages_state(struct snp_psc_desc *desc, unsigned long vad struct ghcb *ghcb, bool large_entry, bool allow_noupdate); void vc_ghcb_invalidate(struct ghcb *ghcb); +void pvalidate_pages(struct snp_psc_desc *desc, unsigned long *vaddr_arr, + bool allow_noupdate); +int vmgexit_psc(struct snp_psc_desc *desc, struct ghcb *ghcb); +void add_psc_entry(struct snp_psc_desc *desc, u8 idx, u8 op, + unsigned long vaddr, bool large_entry, u16 offset); unsigned long long get_amd_sev_c_bit_mask(void); unsigned long long get_amd_sev_addr_upperbound(void); diff --git a/x86/amd_sev.c b/x86/amd_sev.c index ae19f8ad6cc8..bd369e5cada7 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -366,6 +366,71 @@ static void test_sev_psc_intermix_to_shared(void) test_sev_psc_intermix(false); } +static void test_sev_snp_psmash(void) +{ + int ret; + unsigned long vaddr, vaddr_arr[3]; + struct snp_psc_desc desc = {0}; + struct ghcb *ghcb = (struct ghcb *)(rdmsr(SEV_ES_GHCB_MSR_INDEX)); + + report_info("TEST: PSMASH and UNSMASH operations on 2M range"); + + vaddr = (unsigned long)vmalloc_pages(SEV_ALLOC_PAGE_COUNT, + SEV_ALLOC_ORDER, RMP_PG_SIZE_2M); + + /* + * Create a PSC request for first PSC entry where: + * - guest issues an UNSMASH on a 2M private range. + * Hypervisor treats an UNSMASH hint from guest as a nop. + * So it is expected that the state of pages after conversion to + * be in the same state as before. + */ + vaddr_arr[0] = vaddr; + add_psc_entry(&desc, 0, SNP_PAGE_STATE_UNSMASH, vaddr_arr[0], + true, 0); + + /* + * Create a PSC request for second PSC entry where: + * - guest issues a PSMASH on the next 2M private range. + * Hypervisor should also treat PSMASH hint from guest as a nop. + */ + vaddr_arr[1] = vaddr + LARGE_PAGE_SIZE; + add_psc_entry(&desc, 1, SNP_PAGE_STATE_PSMASH, vaddr_arr[1], + true, 0); + + /* + * For 3rd PSC entry: + * Perform an UNSMASH on the PSMASH'd entry where: + * - guest now issues an UNSMASH on a 2M private PSMASH'd entry, + * but since a PSMASH/UNSMASH are noops, states of these pages + * should be in their original (private) states. + */ + vaddr_arr[2] = vaddr_arr[1]; + add_psc_entry(&desc, 2, SNP_PAGE_STATE_UNSMASH, vaddr_arr[2], + true, 0); + + ret = vmgexit_psc(&desc, ghcb); + + assert_msg(!ret, "VMGEXIT failed with ret value: %d", ret); + + /* + * Ensure the page states are still in the original (private) + * state after hypervisor handled PSMASH/UNSMASH operations. + */ + report(is_validated_private_page(vaddr, RMP_PG_SIZE_2M), + "Expected page state: Private"); + + report(is_validated_private_page(vaddr + LARGE_PAGE_SIZE, + RMP_PG_SIZE_2M), + "Expected page state: Private"); + + pvalidate_pages(&desc, vaddr_arr, true); + + /* Free up all the used pages */ + snp_free_pages(SEV_ALLOC_ORDER, SEV_ALLOC_PAGE_COUNT, vaddr, + ghcb, true); +} + int main(void) { int rtn; @@ -387,6 +452,7 @@ int main(void) test_sev_psc_ghcb_nae(); test_sev_psc_intermix_to_private(); test_sev_psc_intermix_to_shared(); + test_sev_snp_psmash(); } return report_summary(); From patchwork Thu Jul 18 12:49:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paluri, PavanKumar" X-Patchwork-Id: 13736468 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2081.outbound.protection.outlook.com [40.107.237.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 442B154645 for ; Thu, 18 Jul 2024 12:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 18 Jul 2024 07:52:58 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests PATCH v2 16/16] x86 AMD SEV-SNP: Inject random cur_page offsets for 2M ranges Date: Thu, 18 Jul 2024 07:49:32 -0500 Message-ID: <20240718124932.114121-17-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718124932.114121-1-papaluri@amd.com> References: <20240718124932.114121-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000018:EE_|SJ0PR12MB6942:EE_ X-MS-Office365-Filtering-Correlation-Id: c358a5d4-a957-4502-46b3-08dca7288d7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2024 12:52:59.3117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c358a5d4-a957-4502-46b3-08dca7288d7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000018.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6942 While issuing a page state change request using VMGEXIT for 2M large ranges, a normal SEV-SNP guest usually sets cur_page offset as zero and it is then the responsibility of the hypervisor to ensure all the 512 4K pages within 2M range are successfully processed or not. Introduce a test case where a malicious guest sets random cur_page offsets to demonstrate how hypervisor handles such partial page state change requests beginning at a random cur_page offset. Signed-off-by: Pavan Kumar Paluri --- x86/amd_sev.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/x86/amd_sev.c b/x86/amd_sev.c index bd369e5cada7..c83862ea26f7 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -431,6 +431,63 @@ static void test_sev_snp_psmash(void) ghcb, true); } +static void __test_sev_snp_page_offset(int cur_page_offset) +{ + struct ghcb *ghcb = (struct ghcb *)(rdmsr(SEV_ES_GHCB_MSR_INDEX)); + struct snp_psc_desc desc = {0}; + unsigned long vaddr, vaddr_start; + int ret, iter; + + /* Allocate a 2M large page */ + vaddr = (unsigned long)vmalloc_pages((SEV_ALLOC_PAGE_COUNT) / 2, + SEV_ALLOC_ORDER - 1, + RMP_PG_SIZE_2M); + /* + * Create a PSC private->shared request where a non-zero + * cur_page offset is set to examine how hypervisor handles such + * requests. + */ + add_psc_entry(&desc, 0, SNP_PAGE_STATE_SHARED, vaddr, true, + cur_page_offset); + + ret = vmgexit_psc(&desc, ghcb); + assert_msg(!ret, "VMGEXIT failed with ret value: %d", ret); + + /* + * Conduct a re-validation test to examine if the pages within 1 + * to cur_page offset are still in their expected private state. + */ + vaddr_start = vaddr; + for (iter = 0; iter < cur_page_offset; iter++) { + ret = is_validated_private_page(vaddr_start, RMP_PG_SIZE_4K); + assert_msg(ret, "Page not in expected private state"); + vaddr_start += PAGE_SIZE; + } + + pvalidate_pages(&desc, &vaddr, true); + + /* Free up the used pages */ + snp_free_pages(SEV_ALLOC_ORDER - 1, (SEV_ALLOC_PAGE_COUNT) / 2, + vaddr, ghcb, true); +} + +static void test_sev_snp_page_offset(void) +{ + int iter; + /* + * Set a pool of current page offsets such that all + * possible edge-cases are covered in order to examine + * how hypervisor handles PSC requests with non-zero cur_page + * offsets. + */ + int cur_page_offsets[] = {0, 1, 256, 511, 512}; + + report_info("TEST: Injecting non-zero current page offsets"); + + for (iter = 0; iter < ARRAY_SIZE(cur_page_offsets); iter++) + __test_sev_snp_page_offset(cur_page_offsets[iter]); +} + int main(void) { int rtn; @@ -453,6 +510,7 @@ int main(void) test_sev_psc_intermix_to_private(); test_sev_psc_intermix_to_shared(); test_sev_snp_psmash(); + test_sev_snp_page_offset(); } return report_summary();