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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70cff491231sm234930b3a.31.2024.07.18.19.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 19:39:57 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v3 1/5] riscv: Extend exception handling support for interrupts Date: Fri, 19 Jul 2024 10:39:43 +0800 Message-ID: <20240719023947.112609-2-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240719023947.112609-1-jamestiotio@gmail.com> References: <20240719023947.112609-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Andrew Jones Add install_irq_handler() to enable tests to install interrupt handlers. Also add local_irq_enable() and local_irq_disable() to respectively enable and disable IRQs via the sstatus.SIE bit. Signed-off-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 2 ++ lib/riscv/asm/processor.h | 13 +++++++++++++ lib/riscv/processor.c | 27 +++++++++++++++++++++++---- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index 52608512..d6909d93 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -11,6 +11,8 @@ #define CSR_STVAL 0x143 #define CSR_SATP 0x180 +#define SR_SIE _AC(0x00000002, UL) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 32c499d0..6451adb5 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -5,6 +5,7 @@ #include #define EXCEPTION_CAUSE_MAX 16 +#define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *); @@ -13,6 +14,7 @@ struct thread_info { unsigned long hartid; unsigned long isa[1]; exception_fn exception_handlers[EXCEPTION_CAUSE_MAX]; + exception_fn interrupt_handlers[INTERRUPT_CAUSE_MAX]; }; static inline struct thread_info *current_thread_info(void) @@ -20,7 +22,18 @@ static inline struct thread_info *current_thread_info(void) return (struct thread_info *)csr_read(CSR_SSCRATCH); } +static inline void local_irq_enable(void) +{ + csr_set(CSR_SSTATUS, SR_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_SIE); +} + void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *)); +void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *)); void do_handle_exception(struct pt_regs *regs); void thread_info_init(void); diff --git a/lib/riscv/processor.c b/lib/riscv/processor.c index ece7cbff..0dffadc7 100644 --- a/lib/riscv/processor.c +++ b/lib/riscv/processor.c @@ -36,10 +36,21 @@ void do_handle_exception(struct pt_regs *regs) { struct thread_info *info = current_thread_info(); - assert(regs->cause < EXCEPTION_CAUSE_MAX); - if (info->exception_handlers[regs->cause]) { - info->exception_handlers[regs->cause](regs); - return; + if (regs->cause & CAUSE_IRQ_FLAG) { + unsigned long irq_cause = regs->cause & ~CAUSE_IRQ_FLAG; + + assert(irq_cause < INTERRUPT_CAUSE_MAX); + if (info->interrupt_handlers[irq_cause]) { + info->interrupt_handlers[irq_cause](regs); + return; + } + } else { + assert(regs->cause < EXCEPTION_CAUSE_MAX); + + if (info->exception_handlers[regs->cause]) { + info->exception_handlers[regs->cause](regs); + return; + } } show_regs(regs); @@ -47,6 +58,14 @@ void do_handle_exception(struct pt_regs *regs) abort(); } +void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *)) +{ + struct thread_info *info = current_thread_info(); + + assert(cause < INTERRUPT_CAUSE_MAX); + info->interrupt_handlers[cause] = handler; +} + void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *)) { struct thread_info *info = current_thread_info(); From patchwork Fri Jul 19 02:39:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Raphael Tiovalen X-Patchwork-Id: 13736831 Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CECC17BD9 for ; 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70cff491231sm234930b3a.31.2024.07.18.19.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 19:40:00 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v3 2/5] riscv: Update exception cause list Date: Fri, 19 Jul 2024 10:39:44 +0800 Message-ID: <20240719023947.112609-3-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240719023947.112609-1-jamestiotio@gmail.com> References: <20240719023947.112609-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the list of exception and interrupt causes to follow the latest RISC-V privileged ISA specification (version 20240411 section 18.6.1). Reviewed-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 10 ++++++++++ lib/riscv/asm/processor.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index d6909d93..ba810c9f 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -36,6 +36,16 @@ #define EXC_VIRTUAL_INST_FAULT 22 #define EXC_STORE_GUEST_PAGE_FAULT 23 +/* Interrupt causes */ +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 6451adb5..4c9ad968 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -4,7 +4,7 @@ #include #include -#define EXCEPTION_CAUSE_MAX 16 +#define EXCEPTION_CAUSE_MAX 24 #define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *); From patchwork Fri Jul 19 02:39:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Raphael Tiovalen X-Patchwork-Id: 13736832 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B7A617C61 for ; Fri, 19 Jul 2024 02:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721356805; cv=none; b=qb7y3Wke0IAJTOMrbtThfM9Zymjs3Fphbnm2RTgWB4uf6F43B0o9CJyT+Xz3rNX/6Rq754dp0KuNHNIeDm7/LT5+zuLFGnQ/Khqe43QV/+s4Oh3+dxHPFqZdFl1SWkyG8JumS8sxMVGHbXAyxW1QE3cwrxkfVd9BnnHwjowJ61c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721356805; c=relaxed/simple; bh=2ojPZa4h2oYAX55qtj8WvJCbwq5yeV93EXeRORL+gpU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Oy1ZRNxZgxlfFqosYdGBaysz6MOgZnAogV/xJb/Y9KCFJqRrQKoys6D710TAFrrNsuGKT3VJbhK4JI5ZSjTkGg57ykL7lmItz3O88lt4F1BUD0wlEc78wrCIjce0gujXXc7Jo6Gfdl/m7lqd1ZuogpatMXjj4k9urmnj1cXVoT8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jvb6irOB; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jvb6irOB" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-70b0e7f6f8bso391214b3a.3 for ; Thu, 18 Jul 2024 19:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721356803; x=1721961603; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OLU7dzQvfkJ9Ef0blGKudWZ8SLP+KA1hEm/nsUl2wGw=; b=jvb6irOBvMZUFVnHi+RmkMdlxg/oN+0jIOR7O3xzilU/inX83eMmUsGlmYWGVjuqwD vhMsNilbwF8Q7SXt+LV9ksVmO4QhtOTZr5MbAShgCMLRt9QwAX2HRxszOlsqvUImKxMc SjC3cAm+6FX3nBiFs5QUU6Gsd8gXYs/FhHaupiHPbuAkhCsyKa/HayeObvMEnDMMAUgS r9+zwmfQ3Bu8WC6LAXBiAgNN2KcfrbdltqajPTXQsfBPJfTeyNoHb4YCp4XT/oVrUi2o PeU+mi5pbbd7Y5m3+sip4XIndWGeMzCrJYGID1YNGSTS9gquKG4CwRlZzSISsU+W3684 iPAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721356803; x=1721961603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OLU7dzQvfkJ9Ef0blGKudWZ8SLP+KA1hEm/nsUl2wGw=; b=TS4nFXLEIr0Ug15GhmpJVaJKl6/opf/TeY7t7r57yw39AjYDTP0+XRo3G+WxwXeGno BdXQ3pn8dVlb1bey91fLcBFNhv3Tq7wI80/P0z24hcsVyAKq/eF0kpIGz9bCHBaODzst 8G9M+ZhEwBpnnEA8xtp8THw7dk/YIZUr+E3RRt56EVrpcwOxcwEQA30IhfMsZ5tRRAiz 8Kdp5EvM7dFPlsdSACnNURcvdipqAJrpRxWew9g+GzrkyuaNvExxvnvV4SK0YQqh+a8m LsIgJ0cVlqm7e3Y9iEdwWRdbsgaWOie6gKPcLMdKpiSAfg5F/QvLZ5djp9rTBNWB7eXU G5xA== X-Gm-Message-State: AOJu0YysLK5JdQvxiZZr5ncEGCL5YOtDyM4Fvse8YBz3uIwtQ6npdJox xHlvtVvVa/qHkkQMd+J329CuVT3z+MAcmzMMt+mA/+ooVd4Y5AmKvlgtUp90 X-Google-Smtp-Source: AGHT+IE7JpMmfmafXElRljUIBX5nNaC28/MohzaDsxFle4aKtRo45YlHaoMlFZzgUMTdcxt2s61H3A== X-Received: by 2002:a05:6a00:4fc5:b0:706:6b0b:9573 with SMTP id d2e1a72fcca58-70ce4fb5f42mr8187623b3a.19.1721356803260; Thu, 18 Jul 2024 19:40:03 -0700 (PDT) Received: from JRT-PC.. ([202.166.44.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70cff491231sm234930b3a.31.2024.07.18.19.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 19:40:02 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v3 3/5] riscv: Add method to probe for SBI extensions Date: Fri, 19 Jul 2024 10:39:45 +0800 Message-ID: <20240719023947.112609-4-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240719023947.112609-1-jamestiotio@gmail.com> References: <20240719023947.112609-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a `sbi_probe` helper method that can be used by SBI extension tests to check if a given extension is available. Signed-off-by: James Raphael Tiovalen Reviewed-by: Andrew Jones --- lib/riscv/asm/sbi.h | 1 + lib/riscv/sbi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index d82a384d..5e1a674a 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -49,6 +49,7 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, void sbi_shutdown(void); struct sbiret sbi_hart_start(unsigned long hartid, unsigned long entry, unsigned long sp); +long sbi_probe(int ext); #endif /* !__ASSEMBLY__ */ #endif /* _ASMRISCV_SBI_H_ */ diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c index f39134c4..7d7d09c3 100644 --- a/lib/riscv/sbi.c +++ b/lib/riscv/sbi.c @@ -38,3 +38,13 @@ struct sbiret sbi_hart_start(unsigned long hartid, unsigned long entry, unsigned { return sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START, hartid, entry, sp, 0, 0, 0); } + +long sbi_probe(int ext) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, ext, 0, 0, 0, 0, 0); + assert(!ret.error); + + return ret.value; +} From patchwork Fri Jul 19 02:39:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Raphael Tiovalen X-Patchwork-Id: 13736833 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B72BB22094 for ; Fri, 19 Jul 2024 02:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721356808; cv=none; b=BuOJGZrSko0BRacov1/0+Es5A9R2E8p2QPVi3xS/AiNs8anLpYhj+YbaF5SKgTJhhLt+NL+Kxn5DXt8DWZU2xc3W80kjUGlJzePDwG7GvIQMuvyxcQ9ziVCR17mS58t+fQosqZ6MEim3RSZDkvVRnoOVWRiisK+HH2a5AjVg7R8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721356808; c=relaxed/simple; bh=jecQVlJXe4cgGggLdbAFJT9ADB00vwwpDrqUxrMcSJM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OQF+TLXPpSON37Nh5BuAXSFjxMKZQlpSJ9TJ4YNPm9hcXXvsolSCaRfoJ+3nGZRMryhEH/w2ISkJwgKZSXpvBfRguEByrd6QwMXJkXPA6BPXW2wBQ+E0smwCsK6Y2RShZy5gdL5DzsdqYcQSRakcU2g9Ous5S+rshcnZE1rcaWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bghUbdpg; arc=none smtp.client-ip=209.85.210.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bghUbdpg" Received: by mail-pf1-f181.google.com with SMTP id d2e1a72fcca58-70af0684c2bso373393b3a.0 for ; Thu, 18 Jul 2024 19:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721356806; x=1721961606; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fOsMqz9z7Oh6nOgISuqIG8CJ1WmrFbXS0QT63MVa3N8=; b=bghUbdpgQGHvt1/k/aKj2s+x4DNPpgVse8ojd/b0BJl8RvUYsULGAbug06SLR8gT52 5NLMKIBrQkh3vxpTy3HXDf0oFziGV0Lx/u62+7QwU+0XerH/dRQx4uNmpX/euCLE+vl4 unxh9GdZW0D3TJYbhilGIz/XLUxN+SBGPBXRjZ47KJARa/Nw6u/rpg2PL/oueARDKtlA Dqn+VeHK72lRrEQqH1vbql/BTi5oBpZeTy5Q4dQMBxOZbiq8ypWJ5fXJ+HaNlqJX/G1o 8rfEfezTdBtk6qINbIjPextEq+w0v3EM6FWA/10Kn340vhCZOP/HyWYsBrTaVo3MeXrn qaQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721356806; x=1721961606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fOsMqz9z7Oh6nOgISuqIG8CJ1WmrFbXS0QT63MVa3N8=; b=UYFGyXDNq/1xPOqWDXdnB2F3QiQNy7l9811cKB8Uz7+i3fai+KMIFvbiKu5NFGLfMe jT6VO5buepMqdZQoGTEx2KNNh8mM9hw3HwMzP3iYJnxo0cyXKzW2lZkwtQxjK0k7ZA+r oLokaG5n27ItM3cEbrjF1s3LVS21WWlseqI5loaTg/Fz2lixb2CcXBS8mla1MqOy1F6c BZAyV2Srq1XNJrKzSN4l5aB/ose1exJ9UHfV/Np7SKQK7yekr4RtbBC7W3RMVX5nXk+l hDT3FSWZrMInDmjwL6QLfoGCwzPShBUgn70eNaVnMNExenL1AhgKW242tZIWSE8/ZBE5 rabA== X-Gm-Message-State: AOJu0YzE+PwPCf6nLedlmSC3rmkJmSYI7gPfiT0/30dVotCXQcj37ZOh EGuX6DYQpNAtgSyZSlQc0tDDpbS4z/CLASQXUze52sn4i2QRhmAzeiwcHqGJ X-Google-Smtp-Source: AGHT+IHmveWlmRRR9abbnxX8207M4lbpHXpK3hIFLSfirKbPsB5gPB8hMI155QLlcMWCbOkPIReenA== X-Received: by 2002:a05:6a00:180b:b0:706:7577:c564 with SMTP id d2e1a72fcca58-70ce500d42emr8522056b3a.21.1721356805471; Thu, 18 Jul 2024 19:40:05 -0700 (PDT) Received: from JRT-PC.. ([202.166.44.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70cff491231sm234930b3a.31.2024.07.18.19.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 19:40:05 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v3 4/5] riscv: Add some delay and timer routines Date: Fri, 19 Jul 2024 10:39:46 +0800 Message-ID: <20240719023947.112609-5-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240719023947.112609-1-jamestiotio@gmail.com> References: <20240719023947.112609-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a delay method that would allow tests to wait for some specified number of cycles. Also add a conversion helper method between microseconds and cycles. This conversion is done by using the timebase frequency, which is obtained during setup via the device tree. Signed-off-by: James Raphael Tiovalen Reviewed-by: Andrew Jones --- riscv/Makefile | 2 ++ lib/riscv/asm/csr.h | 1 + lib/riscv/asm/delay.h | 15 +++++++++++++++ lib/riscv/asm/setup.h | 1 + lib/riscv/asm/timer.h | 14 ++++++++++++++ lib/riscv/delay.c | 16 ++++++++++++++++ lib/riscv/setup.c | 4 ++++ lib/riscv/timer.c | 26 ++++++++++++++++++++++++++ 8 files changed, 79 insertions(+) create mode 100644 lib/riscv/asm/delay.h create mode 100644 lib/riscv/asm/timer.h create mode 100644 lib/riscv/delay.c create mode 100644 lib/riscv/timer.c diff --git a/riscv/Makefile b/riscv/Makefile index 919a3ebb..b0cd613f 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -30,6 +30,7 @@ cflatobjs += lib/memregions.o cflatobjs += lib/on-cpus.o cflatobjs += lib/vmalloc.o cflatobjs += lib/riscv/bitops.o +cflatobjs += lib/riscv/delay.o cflatobjs += lib/riscv/io.o cflatobjs += lib/riscv/isa.o cflatobjs += lib/riscv/mmu.o @@ -38,6 +39,7 @@ cflatobjs += lib/riscv/sbi.o cflatobjs += lib/riscv/setup.o cflatobjs += lib/riscv/smp.o cflatobjs += lib/riscv/stack.o +cflatobjs += lib/riscv/timer.o ifeq ($(ARCH),riscv32) cflatobjs += lib/ldiv32.o endif diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index ba810c9f..a9b1bd42 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -10,6 +10,7 @@ #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SATP 0x180 +#define CSR_TIME 0xc01 #define SR_SIE _AC(0x00000002, UL) diff --git a/lib/riscv/asm/delay.h b/lib/riscv/asm/delay.h new file mode 100644 index 00000000..ce540f4c --- /dev/null +++ b/lib/riscv/asm/delay.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_DELAY_H_ +#define _ASMRISCV_DELAY_H_ + +#include +#include + +extern void delay(u64 cycles); + +static inline uint64_t usec_to_cycles(uint64_t usec) +{ + return (timebase_frequency * usec) / 1000000; +} + +#endif /* _ASMRISCV_DELAY_H_ */ diff --git a/lib/riscv/asm/setup.h b/lib/riscv/asm/setup.h index 7f81a705..a13159bf 100644 --- a/lib/riscv/asm/setup.h +++ b/lib/riscv/asm/setup.h @@ -7,6 +7,7 @@ #define NR_CPUS 16 extern struct thread_info cpus[NR_CPUS]; extern int nr_cpus; +extern uint64_t timebase_frequency; int hartid_to_cpu(unsigned long hartid); void io_init(void); diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h new file mode 100644 index 00000000..2e319391 --- /dev/null +++ b/lib/riscv/asm/timer.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_TIMER_H_ +#define _ASMRISCV_TIMER_H_ + +#include + +extern void timer_get_frequency(const void *fdt); + +static inline uint64_t timer_get_cycles(void) +{ + return csr_read(CSR_TIME); +} + +#endif /* _ASMRISCV_TIMER_H_ */ diff --git a/lib/riscv/delay.c b/lib/riscv/delay.c new file mode 100644 index 00000000..6b5c78da --- /dev/null +++ b/lib/riscv/delay.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, James Raphael Tiovalen + */ +#include +#include +#include +#include + +void delay(uint64_t cycles) +{ + uint64_t start = timer_get_cycles(); + + while ((timer_get_cycles() - start) < cycles) + cpu_relax(); +} diff --git a/lib/riscv/setup.c b/lib/riscv/setup.c index 50ffb0d0..905ea708 100644 --- a/lib/riscv/setup.c +++ b/lib/riscv/setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #define VA_BASE ((phys_addr_t)3 * SZ_1G) #if __riscv_xlen == 64 @@ -38,6 +39,7 @@ u32 initrd_size; struct thread_info cpus[NR_CPUS]; int nr_cpus; +uint64_t timebase_frequency; static struct mem_region riscv_mem_regions[NR_MEM_REGIONS + 1]; @@ -199,6 +201,7 @@ void setup(const void *fdt, phys_addr_t freemem_start) mem_init(PAGE_ALIGN(__pa(freemem))); cpu_init(); + timer_get_frequency(dt_fdt()); thread_info_init(); io_init(); @@ -264,6 +267,7 @@ efi_status_t setup_efi(efi_bootinfo_t *efi_bootinfo) } cpu_init(); + timer_get_frequency(dt_fdt()); thread_info_init(); io_init(); initrd_setup(); diff --git a/lib/riscv/timer.c b/lib/riscv/timer.c new file mode 100644 index 00000000..db8dbb36 --- /dev/null +++ b/lib/riscv/timer.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, James Raphael Tiovalen + */ +#include +#include +#include +#include + +void timer_get_frequency(const void *fdt) +{ + const struct fdt_property *prop; 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70cff491231sm234930b3a.31.2024.07.18.19.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 19:40:07 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v3 5/5] riscv: sbi: Add test for timer extension Date: Fri, 19 Jul 2024 10:39:47 +0800 Message-ID: <20240719023947.112609-6-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240719023947.112609-1-jamestiotio@gmail.com> References: <20240719023947.112609-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a test for the set_timer function of the time extension. The test checks that: - The time extension is available - The time counter monotonically increases - The installed timer interrupt handler is called - The timer interrupt is received within a reasonable time interval - The timer interrupt pending bit is cleared after the set_timer SBI call is made - The timer interrupt can be cleared either by requesting a timer interrupt infinitely far into the future or by masking the timer interrupt The timer interrupt delay can be set using the TIMER_DELAY environment variable in microseconds. The default delay value is 1 second. Since the interrupt can arrive a little later than the specified delay, allow some margin of error. This margin of error can be specified via the TIMER_MARGIN environment variable in microseconds. The default margin of error is 200 milliseconds. This test has been verified on RV32 and RV64 with OpenSBI using QEMU. Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 8 +++ lib/riscv/asm/sbi.h | 5 ++ lib/riscv/asm/timer.h | 10 ++++ riscv/sbi.c | 136 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 159 insertions(+) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index a9b1bd42..052c0412 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -4,13 +4,17 @@ #include #define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 +#define CSR_SIP 0x144 #define CSR_SATP 0x180 #define CSR_TIME 0xc01 +#define CSR_STIMECMP 0x14d +#define CSR_STIMECMPH 0x15d #define SR_SIE _AC(0x00000002, UL) @@ -47,6 +51,10 @@ #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 +#define IE_TIE (_AC(0x1, UL) << IRQ_S_TIMER) + +#define IP_TIP IE_TIE + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index 5e1a674a..73ab5438 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -16,6 +16,7 @@ enum sbi_ext_id { SBI_EXT_BASE = 0x10, + SBI_EXT_TIME = 0x54494d45, SBI_EXT_HSM = 0x48534d, SBI_EXT_SRST = 0x53525354, }; @@ -37,6 +38,10 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_SUSPEND, }; +enum sbi_ext_time_fid { + SBI_EXT_TIME_SET_TIMER = 0, +}; + struct sbiret { long error; long value; diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h index 2e319391..cd20262f 100644 --- a/lib/riscv/asm/timer.h +++ b/lib/riscv/asm/timer.h @@ -11,4 +11,14 @@ static inline uint64_t timer_get_cycles(void) return csr_read(CSR_TIME); } +static inline void timer_irq_enable(void) +{ + csr_set(CSR_SIE, IE_TIE); +} + +static inline void timer_irq_disable(void) +{ + csr_clear(CSR_SIE, IE_TIE); +} + #endif /* _ASMRISCV_TIMER_H_ */ diff --git a/riscv/sbi.c b/riscv/sbi.c index 762e9711..9798b989 100644 --- a/riscv/sbi.c +++ b/riscv/sbi.c @@ -6,7 +6,21 @@ */ #include #include +#include +#include +#include +#include +#include +#include #include +#include +#include + +static bool timer_works; +static bool mask_timer_irq; +static bool timer_irq_set; +static bool timer_irq_cleared; +static unsigned long timer_irq_count; static void help(void) { @@ -19,6 +33,33 @@ static struct sbiret __base_sbi_ecall(int fid, unsigned long arg0) return sbi_ecall(SBI_EXT_BASE, fid, arg0, 0, 0, 0, 0, 0); } +static struct sbiret __time_sbi_ecall(unsigned long stime_value) +{ + return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0); +} + +static inline bool timer_irq_pending(void) +{ + return csr_read(CSR_SIP) & IP_TIP; +} + +static void timer_irq_handler(struct pt_regs *regs) +{ + timer_irq_count = (timer_irq_count == ULONG_MAX) ? ULONG_MAX : timer_irq_count + 1; + + timer_works = true; + if (timer_irq_pending()) + timer_irq_set = true; + + if (mask_timer_irq) + timer_irq_disable(); + else { + __time_sbi_ecall(ULONG_MAX); + if (!timer_irq_pending()) + timer_irq_cleared = true; + } +} + static bool env_or_skip(const char *env) { if (!getenv(env)) { @@ -112,6 +153,100 @@ static void check_base(void) report_prefix_pop(); } +static void check_time(void) +{ + struct sbiret ret; + unsigned long begin, end, duration; + unsigned long d = getenv("TIMER_DELAY") ? strtol(getenv("TIMER_DELAY"), NULL, 0) + : 1000000; + unsigned long margin = getenv("TIMER_MARGIN") ? strtol(getenv("TIMER_MARGIN"), NULL, 0) + : 200000; + + d = usec_to_cycles(d); + margin = usec_to_cycles(margin); + + report_prefix_push("time"); + + if (!sbi_probe(SBI_EXT_TIME)) { + report_skip("time extension not available"); + report_prefix_pop(); + return; + } + + begin = timer_get_cycles(); + delay(d); + end = timer_get_cycles(); + assert(begin + d <= end); + + report_prefix_push("set_timer"); + + install_irq_handler(IRQ_S_TIMER, timer_irq_handler); + local_irq_enable(); + if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) +#if __riscv_xlen == 64 + csr_write(CSR_STIMECMP, ULONG_MAX); +#else + csr_write(CSR_STIMECMPH, ULONG_MAX); +#endif + timer_irq_enable(); + + begin = timer_get_cycles(); + ret = __time_sbi_ecall(begin + d); + + report(!ret.error, "set timer"); + if (ret.error) + report_info("set timer failed with %ld\n", ret.error); + + report(!timer_irq_pending(), "pending timer interrupt bit cleared"); + + while ((end = timer_get_cycles()) <= (begin + d + margin) && !timer_works) + cpu_relax(); + + report(timer_works, "timer interrupt received"); + report(timer_irq_set, "pending timer interrupt bit set in irq handler"); + report(timer_irq_cleared, "pending timer interrupt bit cleared by setting timer to -1"); + + if (timer_works) { + duration = end - begin; + report(duration >= d && duration <= (d + margin), "timer delay honored"); + } + + if (timer_irq_count > 1) + report_fail("timer interrupt received multiple times"); + + timer_works = false; + timer_irq_set = false; + timer_irq_count = 0; + mask_timer_irq = true; + begin = timer_get_cycles(); + ret = __time_sbi_ecall(begin + d); + + report(!ret.error, "set timer for mask irq test"); + if (ret.error) + report_info("set timer for mask irq test failed with %ld\n", ret.error); + + while ((end = timer_get_cycles()) <= (begin + d + margin) && !timer_works) + cpu_relax(); + + report(timer_works, "timer interrupt received for mask irq test"); + report(timer_irq_set, "pending timer interrupt bit set in irq handler for mask irq test"); + + if (timer_works) { + duration = end - begin; + report(duration >= d && duration <= (d + margin), + "timer delay honored for mask irq test"); + } + + if (timer_irq_count > 1) + report_fail("timer interrupt received multiple times for mask irq test"); + + local_irq_disable(); + install_irq_handler(IRQ_S_TIMER, NULL); + + report_prefix_pop(); + report_prefix_pop(); +} + int main(int argc, char **argv) { @@ -122,6 +257,7 @@ int main(int argc, char **argv) report_prefix_push("sbi"); check_base(); + check_time(); return report_summary(); }