From patchwork Fri Jul 19 16:29:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6FFCC3DA5D for ; Fri, 19 Jul 2024 17:36:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUrVR-0004Aj-2a; Fri, 19 Jul 2024 13:34:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3cJSaZggKCj8xifoesjlhpphmf.dpnrfnv-efwfmopohov.psh@flex--whendrik.bounces.google.com>) id 1sUqUH-0002LG-VA for qemu-devel@nongnu.org; Fri, 19 Jul 2024 12:29:41 -0400 Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3cJSaZggKCj8xifoesjlhpphmf.dpnrfnv-efwfmopohov.psh@flex--whendrik.bounces.google.com>) id 1sUqUF-0004CP-0M for qemu-devel@nongnu.org; Fri, 19 Jul 2024 12:29:41 -0400 Received: by mail-wm1-x349.google.com with SMTP id 5b1f17b1804b1-427a7a65e7dso7655685e9.1 for ; Fri, 19 Jul 2024 09:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1721406577; x=1722011377; darn=nongnu.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=EuegESfmjtOPOYVDWqUdcW99Kxin32wkde1axwvFNOQ=; b=0ltkSNuraYIwg7A0L4pjawWGo/7/5zZaMCRNk456a1vjufscT/YsPOw+0zG6OPGLNM cyuKZaBj09PB7LsaBXS+cImRnxkqmTwjvQurByYboycCuswKnxkL4qCjyKet6dZ+6dz/ /qk3sGKXC+Wh8CCd1qcMp6SoALxsXZtVxVsM7B7FjR60/R3W6LEIkwZCX0eUFC9xrem0 3RJxi9OOoh7/jdBVV7Fa44kLh75igd+xyXz1ZkOUdeUUnNfo9Lb7BvPRLDAOfBLXJ+7L usLT0pehaFBsWEKGMjrXgRqbzAMmjtyWUMSXD9M/b17zI4SrjJK4fV83AyJXvdKBrwYZ Bubw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721406577; x=1722011377; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=EuegESfmjtOPOYVDWqUdcW99Kxin32wkde1axwvFNOQ=; b=AqhGlN/KfC04y94vaG76HuXZXIk1xJ60/N4eivbr3Nz6gAgIEonwsKOOyXuCh0MnHh 78FPUZ2CRHWmq+zwnuJUP2hg1Z3Wr1P+8gcGGD0ITqMN8IWx8o7rKyqKf6AU85XmZ1wT 2pRa+dK+8a5s3erjPC+UJifRqeKT1AYSEGxuXwapl6f0fCwH2FjAmlQD2+ifw+MxLWV2 13o/hclXMIEizX6lSMJPm03b2IYzmjz64d2lOVrACtJmCrlXlDjDsxm1TEAwRyEQiXZ7 U4rUUDbRTPY7+pAuP3qvXxcivXEy+1ZeK6uBNxm5kv8fQ0Cu1W3Kr0XUNULuQ8vViZBV 0cww== X-Gm-Message-State: AOJu0YzcLinjCdzNFV/4MmLdha/xDzKF8hLxg/HMxbvHLb2qAS79XlEq yj3MrnQDzftP5VBXmn0VCy2qZLkJqrpF+zdpCNkh1qQhZmcnaCwyzVRIaR/IGIkblZCgWkl7U6Z zjfOOw8SPigMkKB+D+Q0Cos79tbN9cj8Ygqrg15TlpQz9jM2nBhZ6K0e5E9EN50R3vEm3OK+ZQS 5XTPIijit/Jza4iXsopxJCQqOaLilhkVNn+JSQUM0Cvw== X-Google-Smtp-Source: AGHT+IFv0AX1gUZXag6niCN+z/eeMcO9hLQ0PBPZwp13D1t/x/HZxPTHu7Fi/4o0Et9+KaOV4SYRmubJNz4xFw== X-Received: from whendrik-specialist-workstation.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:967]) (user=whendrik job=sendgmr) by 2002:a05:600c:1c1d:b0:426:6761:2fea with SMTP id 5b1f17b1804b1-427d2ac80c1mr636785e9.3.1721406576860; Fri, 19 Jul 2024 09:29:36 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:21 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-2-whendrik@google.com> Subject: [PATCH v1 1/9] Add Intel RDT device to config. From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::349; envelope-from=3cJSaZggKCj8xifoesjlhpphmf.dpnrfnv-efwfmopohov.psh@flex--whendrik.bounces.google.com; helo=mail-wm1-x349.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:48 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Change config to show RDT, add minimal code to the rdt.c module to make sure things still compile. Signed-off-by: Hendrik Wüthrich --- hw/i386/Kconfig | 4 ++++ hw/i386/meson.build | 1 + hw/i386/rdt.c | 49 +++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 12 +++++++++++ 4 files changed, 66 insertions(+) create mode 100644 hw/i386/rdt.c create mode 100644 include/hw/i386/rdt.h diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index f4a33b6c08..4dd05ed6f2 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -10,6 +10,9 @@ config SGX bool depends on KVM +config RDT + bool + config PC bool imply APPLESMC @@ -26,6 +29,7 @@ config PC imply QXL imply SEV imply SGX + imply RDT imply TEST_DEVICES imply TPM_CRB imply TPM_TIS_ISA diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 03aad10df7..fdbf5962b5 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -21,6 +21,7 @@ i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), if_false: files('sgx-stub.c')) +i386_ss.add(when: 'CONFIG_RDT', if_true: files('rdt.c')) i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c')) i386_ss.add(when: 'CONFIG_PC', if_true: files( diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c new file mode 100644 index 0000000000..0a5e95606b --- /dev/null +++ b/hw/i386/rdt.c @@ -0,0 +1,49 @@ +#include "qemu/osdep.h" +#include "hw/i386/rdt.h" +#include +#include "hw/qdev-properties.h" +#include "qemu/typedefs.h" +#include "qom/object.h" +#include "target/i386/cpu.h" +#include "hw/isa/isa.h" + +#define TYPE_RDT "rdt" + +OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); + +struct RDTState { + ISADevice parent; +}; + +struct RDTStateClass { }; + +OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); + +static Property rdt_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void rdt_init(Object *obj) +{ +} + +static void rdt_realize(DeviceState *dev, Error **errp) +{ +} + +static void rdt_finalize(Object *obj) +{ +} + +static void rdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->hotpluggable = false; + dc->desc = "RDT"; + dc->user_creatable = true; + dc->realize = rdt_realize; + + device_class_set_props(dc, rdt_properties); +} + diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h new file mode 100644 index 0000000000..45e34d3103 --- /dev/null +++ b/include/hw/i386/rdt.h @@ -0,0 +1,12 @@ +#ifndef HW_RDT_H +#define HW_RDT_H + +#include +#include + +typedef struct RDTState RDTState; +typedef struct RDTStateInstance RDTStateInstance; +typedef struct RDTMonitor RDTMonitor; +typedef struct RDTAllocation RDTAllocation; + +#endif From patchwork Fri Jul 19 16:29:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EFF2C3DA5D for ; Fri, 19 Jul 2024 17:36:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUrVP-00041Q-OK; Fri, 19 Jul 2024 13:34:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3c5SaZggKCkI0lirhvmoksskpi.gsquiqy-hiziprsrkry.svk@flex--whendrik.bounces.google.com>) id 1sUqUK-0002XA-SC for qemu-devel@nongnu.org; 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Fri, 19 Jul 2024 09:29:39 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:22 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-3-whendrik@google.com> Subject: [PATCH v1 2/9] Add state for RDT device. From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::44a; envelope-from=3c5SaZggKCkI0lirhvmoksskpi.gsquiqy-hiziprsrkry.svk@flex--whendrik.bounces.google.com; helo=mail-wr1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:48 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Add structures and variables needed to emulate Intel RDT, including module-internal sturctures and state in ArchCPU. No functionality yet. Signed-off-by: Hendrik Wüthrich --- hw/i386/rdt.c | 33 +++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++++ 2 files changed, 38 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 0a5e95606b..cf246ab835 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -7,12 +7,44 @@ #include "target/i386/cpu.h" #include "hw/isa/isa.h" +/* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ +#define MAX_L3_MASK_COUNT 128 +#define MAX_L2_MASK_COUNT 48 +#define MAX_MBA_THRTL_COUNT 31 + #define TYPE_RDT "rdt" +#define RDT_NUM_RMID_PROP "rmids" OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); +struct RDTMonitor { + uint64_t count_local; + uint64_t count_remote; + uint64_t count_l3; +}; + +struct RDTAllocation { + uint32_t active_cos; +}; + +struct RDTStateInstance { + uint32_t active_rmid; + GArray *monitors; + + RDTState *rdtstate; +}; + struct RDTState { ISADevice parent; + + uint32_t rmids; + + GArray *rdtInstances; + GArray *allocations; + + uint32_t msr_L3_ia32_mask_n[MAX_L3_MASK_COUNT]; + uint32_t msr_L2_ia32_mask_n[MAX_L2_MASK_COUNT]; + uint32_t ia32_L2_qos_ext_bw_thrtl_n[MAX_MBA_THRTL_COUNT]; }; struct RDTStateClass { }; @@ -20,6 +52,7 @@ struct RDTStateClass { }; OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); static Property rdt_properties[] = { + DEFINE_PROP_UINT32(RDT_NUM_RMID_PROP, RDTState, rmids, 256), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1e121acef5..bd0bbb75f2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1987,6 +1987,8 @@ typedef struct CPUArchState { struct kvm_msrs; +struct RDTState; +struct rdtStateInstance; /** * X86CPU: * @env: #CPUX86State @@ -2143,6 +2145,9 @@ struct ArchCPU { struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; Notifier machine_done; + /* Help the RDT MSRs find the RDT device */ + struct RDTStateInstance *rdt; + struct kvm_msrs *kvm_msr_buf; int32_t node_id; /* NUMA node this CPU belongs to */ From patchwork Fri Jul 19 16:29:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4E03C3DA70 for ; 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From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3dZSaZggKCkQ2nktjxoqmuumrk.iuswks0-jk1krtutmt0.uxm@flex--whendrik.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:48 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Add code to initialize all necessary state for the RDT device. Signed-off-by: Hendrik Wüthrich --- hw/i386/rdt.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index cf246ab835..259dafc963 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -62,10 +62,38 @@ static void rdt_init(Object *obj) static void rdt_realize(DeviceState *dev, Error **errp) { + CPUState *cs = first_cpu; + + RDTState *rdtDev = RDT(dev); + rdtDev->rdtInstances = g_array_new(false, true, sizeof(RDTStateInstance)); + g_array_set_size(rdtDev->rdtInstances, cs->nr_cores); + CPU_FOREACH(cs) { + RDTStateInstance *rdt = &g_array_index(rdtDev->rdtInstances, RDTStateInstance, cs->cpu_index); + + X86CPU *cpu = X86_CPU(cs); + rdt->rdtstate = rdtDev; + cpu->rdt = rdt; + + rdt->monitors = g_array_new(false, true, sizeof(RDTMonitor)); + rdt->rdtstate->allocations = g_array_new(false, true, sizeof(RDTAllocation)); + + g_array_set_size(rdt->monitors, rdtDev->rmids); + g_array_set_size(rdt->rdtstate->allocations, rdtDev->rmids); + } } static void rdt_finalize(Object *obj) { + CPUState *cs; + RDTState *rdt = RDT(obj); + + CPU_FOREACH(cs) { + RDTStateInstance *rdtInstance = &g_array_index(rdt->rdtInstances, RDTStateInstance, cs->cpu_index); + g_array_free(rdtInstance->monitors, true); + g_array_free(rdtInstance->rdtstate->allocations, true); + } + + g_array_free(rdt->rdtInstances, true); } static void rdt_class_init(ObjectClass *klass, void *data) From patchwork Fri Jul 19 16:29:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3FECFC3DA59 for ; Fri, 19 Jul 2024 17:36:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUrVQ-00048l-GL; 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Fri, 19 Jul 2024 09:29:43 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:24 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-5-whendrik@google.com> Subject: [PATCH v1 4/9] Add RDT functionality From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3d5SaZggKCkY4pmvlzqsowwotm.kwuymu2-lm3mtvwvov2.wzo@flex--whendrik.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Add RDT code to Associate CLOSID with RMID / set RMID for monitoring, write COS, and read monitoring data. This patch does not add code for the guest to interact through these things with MSRs, only the actual ability for the RDT device to do them. Signed-off-by: Hendrik Wüthrich --- hw/i386/rdt.c | 124 ++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 13 +++++ 2 files changed, 137 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 259dafc963..77b7b4f2d4 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -7,6 +7,11 @@ #include "target/i386/cpu.h" #include "hw/isa/isa.h" +/* RDT Monitoring Event Codes */ +#define RDT_EVENT_L3_OCCUPANCY 1 +#define RDT_EVENT_L3_REMOTE_BW 2 +#define RDT_EVENT_L3_LOCAL_BW 3 + /* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ #define MAX_L3_MASK_COUNT 128 #define MAX_L2_MASK_COUNT 48 @@ -15,6 +20,9 @@ #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" +#define QM_CTR_Error (1ULL << 63) +#define QM_CTR_Unavailable (1ULL << 62) + OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); struct RDTMonitor { @@ -49,6 +57,122 @@ struct RDTState { struct RDTStateClass { }; +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + RDTAllocation *alloc; + + uint32_t cos_id = (msr_ia32_pqr_assoc & 0xffff0000) >> 16; + uint32_t rmid = msr_ia32_pqr_assoc & 0xffff; + + if (cos_id > MAX_L3_MASK_COUNT || cos_id > MAX_L2_MASK_COUNT || + cos_id > MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) { + return false; + } + + rdt->active_rmid = rmid; + + alloc = &g_array_index(rdt->rdtstate->allocations, RDTAllocation, rmid); + + alloc->active_cos = cos_id; + + return true; +} + +uint32_t rdt_read_l3_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->msr_L3_ia32_mask_n[pos]; + return val; +} + +uint32_t rdt_read_l2_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->msr_L2_ia32_mask_n[pos]; + return val; +} + +uint32_t rdt_read_mba_thrtl(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos]; + return val; +} + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + rdt->rdtstate->msr_L3_ia32_mask_n[pos] = val; +} + +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + rdt->rdtstate->msr_L2_ia32_mask_n[pos] = val; +} + +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos] = val; +} + +uint32_t rdt_max_rmid(RDTStateInstance *rdt) +{ + RDTState *rdtdev = rdt->rdtstate; + return rdtdev->rmids - 1; +} + +uint64_t rdt_read_event_count(RDTStateInstance *rdtInstance, uint32_t rmid, uint32_t event_id) +{ + CPUState *cs; + RDTMonitor *mon; + RDTState *rdt = rdtInstance->rdtstate; + + uint32_t count_l3 = 0; + uint32_t count_local= 0; + uint32_t count_remote = 0; + + if (!rdt) { + return 0; + } + + CPU_FOREACH(cs) { + rdtInstance = &g_array_index(rdt->rdtInstances, RDTStateInstance, cs->cpu_index); + if (rmid >= rdtInstance->monitors->len) { + return QM_CTR_Error; + } + mon = &g_array_index(rdtInstance->monitors, RDTMonitor, rmid); + count_l3 += mon->count_l3; + count_local += mon->count_local; + count_remote += mon->count_remote; + } + + switch (event_id) { + case RDT_EVENT_L3_OCCUPANCY: + return count_l3 == 0 ? QM_CTR_Unavailable : count_l3; + break; + case RDT_EVENT_L3_REMOTE_BW: + return count_remote == 0 ? QM_CTR_Unavailable : count_remote; + break; + case RDT_EVENT_L3_LOCAL_BW: + return count_local == 0 ? QM_CTR_Unavailable : count_local; + break; + default: + return QM_CTR_Error; + } +} + OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); static Property rdt_properties[] = { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index 45e34d3103..8092c5f290 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -10,3 +10,16 @@ typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; #endif +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val); +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val); + +uint32_t rdt_read_l3_mask(uint32_t pos); +uint32_t rdt_read_l2_mask(uint32_t pos); +uint32_t rdt_read_mba_thrtl(uint32_t pos); + +uint64_t rdt_read_event_count(RDTStateInstance *rdt, uint32_t rmid, uint32_t event_id); +uint32_t rdt_max_rmid(RDTStateInstance *rdt); + From patchwork Fri Jul 19 16:29:25 2024 Content-Type: text/plain; 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Fri, 19 Jul 2024 09:29:45 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:25 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-6-whendrik@google.com> Subject: [PATCH v1 5/9] Add RDT device interface through MSRs From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3eZSaZggKCkg6roxn1suqyyqvo.myw0ow4-no5ovxyxqx4.y1q@flex--whendrik.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Implement rdmsr and wrmsr for the following MSRs: * MSR_IA32_PQR_ASSOC * MSR_IA32_QM_EVTSEL * MSR_IA32_QM_CTR * IA32_L3_QOS_Mask_n * IA32_L2_QOS_Mask_n * IA32_L2_QoS_Ext_BW_Thrtl_n This allows for the guest to call RDT-internal functions to associate an RMID with a CLOSID / set an active RMID for monitoring, read monitoring data, and set classes of service. Signed-off-by: Hendrik Wüthrich --- hw/i386/rdt.c | 8 +++ include/hw/i386/rdt.h | 8 ++- target/i386/cpu.h | 14 +++++ target/i386/tcg/sysemu/misc_helper.c | 80 ++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+), 1 deletion(-) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 77b7b4f2d4..0d0e5751fc 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -17,6 +17,10 @@ #define MAX_L2_MASK_COUNT 48 #define MAX_MBA_THRTL_COUNT 31 +#define CPUID_10_1_EDX_COS_MAX MAX_L3_MASK_COUNT +#define CPUID_10_2_EDX_COS_MAX MAX_L2_MASK_COUNT +#define CPUID_10_3_EDX_COS_MAX MAX_MBA_THRTL_COUNT + #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" @@ -57,6 +61,10 @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return CPUID_10_1_EDX_COS_MAX; } +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return CPUID_10_2_EDX_COS_MAX; } +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return CPUID_10_3_EDX_COS_MAX; } + bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { X86CPU *cpu = X86_CPU(current_cpu); RDTStateInstance *rdt = cpu->rdt; diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index 8092c5f290..51d36822f0 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -9,7 +9,12 @@ typedef struct RDTStateInstance RDTStateInstance; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; -#endif +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); + bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); @@ -23,3 +28,4 @@ uint32_t rdt_read_mba_thrtl(uint32_t pos); uint64_t rdt_read_event_count(RDTStateInstance *rdt, uint32_t rmid, uint32_t event_id); uint32_t rdt_max_rmid(RDTStateInstance *rdt); +#endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bd0bbb75f2..0b3aca2d02 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -574,6 +574,17 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_QM_EVTSEL 0x0c8d +#define MSR_IA32_QM_CTR 0x0c8e +#define MSR_IA32_PQR_ASSOC 0x0c8f + +#define MSR_IA32_L3_CBM_BASE 0x0c90 +#define MSR_IA32_L3_MASKS_END 0x0d0f +#define MSR_IA32_L2_CBM_BASE 0x0d10 +#define MSR_IA32_L2_CBM_END 0x0d4f +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50 +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd80 + #define MSR_APIC_START 0x00000800 #define MSR_APIC_END 0x000008ff @@ -1778,6 +1789,9 @@ typedef struct CPUArchState { uint64_t msr_ia32_feature_control; uint64_t msr_ia32_sgxlepubkeyhash[4]; + uint64_t msr_ia32_qm_evtsel; + uint64_t msr_ia32_pqr_assoc; + uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 094aa56a20..e48e6b0da1 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -25,6 +25,7 @@ #include "exec/address-spaces.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" +#include "hw/i386/rdt.h" #include "hw/i386/apic.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) @@ -293,6 +294,44 @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; + case MSR_IA32_QM_EVTSEL: + env->msr_ia32_qm_evtsel = val; + break; + case MSR_IA32_PQR_ASSOC: + { + env->msr_ia32_pqr_assoc = val; + bool res = rdt_associate_rmid_cos(val); + if (!res) + goto error; + break; + } + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) { + goto error; + } + rdt_write_msr_l3_mask(pos, val); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) { + goto error; + } + rdt_write_msr_l2_mask(pos, val); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) { + goto error; + } + rdt_write_mba_thrtl(pos, val); + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -472,6 +511,44 @@ void helper_rdmsr(CPUX86State *env) val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); break; } + case MSR_IA32_QM_CTR: + val = rdt_read_event_count(x86_cpu->rdt, + (env->msr_ia32_qm_evtsel >> 32) & 0xff, + env->msr_ia32_qm_evtsel & 0xff); + break; + case MSR_IA32_QM_EVTSEL: + val = env->msr_ia32_qm_evtsel; + break; + case MSR_IA32_PQR_ASSOC: + val = env->msr_ia32_pqr_assoc; + break; + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) { + goto error; + } + val = rdt_read_l3_mask(pos); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) { + goto error; + } + val = rdt_read_l2_mask(pos); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) { + goto error; + } + val = rdt_read_mba_thrtl(pos); + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -499,6 +576,9 @@ void helper_rdmsr(CPUX86State *env) } env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EDX] = (uint32_t)(val >> 32); +return; +error: + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } void helper_flush_page(CPUX86State *env, target_ulong addr) From patchwork Fri Jul 19 16:29:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DBA6C3DA70 for ; Fri, 19 Jul 2024 17:35:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUrVP-00044c-SX; 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Fri, 19 Jul 2024 09:29:47 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:26 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-7-whendrik@google.com> Subject: [PATCH v1 6/9] Add CPUID enumeration for RDT From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3e5SaZggKCko8tqzp3uws00sxq.o0y2qy6-pq7qxz0zsz6.03s@flex--whendrik.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wüthrich --- hw/i386/rdt.c | 29 ++++++++++++++ include/hw/i386/rdt.h | 29 ++++++++++++++ target/i386/cpu.c | 91 +++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++ 4 files changed, 154 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 0d0e5751fc..5ad05f996a 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -17,8 +17,18 @@ #define MAX_L2_MASK_COUNT 48 #define MAX_MBA_THRTL_COUNT 31 +/* RDT L3 Allocation features */ +#define CPUID_10_1_EAX_CBM_LENGTH 0xf +#define CPUID_10_1_EBX_CBM 0x0 +#define CPUID_10_1_ECX_CDP 0x0 // to enable, it would be (1U << 2) #define CPUID_10_1_EDX_COS_MAX MAX_L3_MASK_COUNT +/* RDT L2 Allocation features*/ +#define CPUID_10_2_EAX_CBM_LENGTH 0xf +#define CPUID_10_2_EBX_CBM 0x0 #define CPUID_10_2_EDX_COS_MAX MAX_L2_MASK_COUNT +/* RDT MBA features */ +#define CPUID_10_3_EAX_THRTL_MAX 89 +#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2) #define CPUID_10_3_EDX_COS_MAX MAX_MBA_THRTL_COUNT #define TYPE_RDT "rdt" @@ -61,8 +71,27 @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_15_0_edx_l3(void) { return CPUID_15_1_EDX_L3_OCCUPANCY | CPUID_15_1_EDX_L3_TOTAL_BW | CPUID_15_1_EDX_L3_LOCAL_BW; } + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void) { return CPUID_15_1_EDX_L3_TOTAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void) { return CPUID_15_1_EDX_L3_LOCAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void) { return CPUID_15_1_EDX_L3_OCCUPANCY; } + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void) { return CPUID_10_0_EBX_L3_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void) { return CPUID_10_0_EBX_L2_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void) { return CPUID_10_0_EBX_MBA; } + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void) { return CPUID_10_1_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void) { return CPUID_10_1_EBX_CBM; } +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void) { return CPUID_10_1_ECX_CDP; } uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return CPUID_10_1_EDX_COS_MAX; } + +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void) { return CPUID_10_2_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void) { return CPUID_10_2_EBX_CBM; } uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return CPUID_10_2_EDX_COS_MAX; } + +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void) { return CPUID_10_3_EAX_THRTL_MAX; } +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void) { return CPUID_10_3_ECX_LINEAR_RESPONSE; } uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return CPUID_10_3_EDX_COS_MAX; } bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index 51d36822f0..74aba33995 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -4,15 +4,44 @@ #include #include +/* RDT L3 Cache Monitoring Technology */ +#define CPUID_15_0_EDX_L3 (1U << 1) +#define CPUID_15_1_EDX_L3_OCCUPANCY (1U << 0) +#define CPUID_15_1_EDX_L3_TOTAL_BW (1U << 1) +#define CPUID_15_1_EDX_L3_LOCAL_BW (1U << 2) + +/* RDT Cache Allocation Technology */ +#define CPUID_10_0_EBX_L3_CAT (1U << 1) +#define CPUID_10_0_EBX_L2_CAT (1U << 2) +#define CPUID_10_0_EBX_MBA (1U << 3) +#define CPUID_10_0_EDX CPUID_10_0_EBX_L3_CAT | CPUID_10_0_EBX_L2_CAT | CPUID_10_0_EBX_MBA + typedef struct RDTState RDTState; typedef struct RDTStateInstance RDTStateInstance; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +uint32_t rdt_get_cpuid_15_0_edx_l3(void); + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void); + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void); + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void); +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void); +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void); uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void); +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void); uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void); +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void); uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4688d140c2..c61981bf82 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -42,6 +42,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "hw/i386/rdt.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -6629,6 +6630,96 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ break; +#ifndef CONFIG_USER_ONLY + case 0xF: + /* Shared Resource Monitoring Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM)) + break; + assert(cpu->rdt); + /* Non-zero count is ResId */ + switch (count) { + /* Monitoring Resource Type Enumeration */ + case 0: + *edx = env->features[FEAT_RDT_15_0_EDX]; + *ebx = rdt_max_rmid(cpu->rdt); + break; + /* L3 Cache Monitoring Capability Enumeration Data */ + case 1: + /* Upscaling Factor */ + *ebx = 1; + /* MaxRMID */ + *ecx = rdt_max_rmid(cpu->rdt); + /* Set L3 Total BW */ + *edx |= rdt_cpuid_15_1_edx_l3_total_bw_enabled(); + /* Set L3 Local BW */ + *edx |= rdt_cpuid_15_1_edx_l3_local_bw_enabled(); + /* Set L3 Occupancy */ + *edx |= rdt_cpuid_15_1_edx_l3_occupancy_enabled(); + break; + default: + break; + } + break; + case 0x10: + /* Shared Resource Director Technology Allocation Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE)) + break; + assert(cpu->rdt); + /* Non-zero count is ResId */ + switch (count) { + /* Cache Allocation Technology Available Resource Types */ + case 0: + /* Set L3 CAT */ + *ebx |= rdt_cpuid_10_0_ebx_l3_cat_enabled(); + /* Set L2 CAT */ + *ebx |= rdt_cpuid_10_0_ebx_l2_cat_enabled(); + /* Set MBA */ + *ebx |= rdt_cpuid_10_0_ebx_l2_mba_enabled(); + // *edx = env->features[FEAT_RDT_10_0_EBX]; + break; + case 1: + /* Length of capacity bitmask in -1 notation */ + *eax = rdt_get_cpuid_10_1_eax_cbm_length(); + /* Capability bit mask */ + *ebx = rdt_cpuid_10_1_ebx_cbm_enabled(); + /* Code and Data priotitization */ + *ecx |= rdt_cpuid_10_1_ecx_cdp_enabled(); + /* Support for n COS masks (zero-referenced)*/ + *edx = rdt_get_cpuid_10_1_edx_cos_max(); + break; + case 2: + /* Length of capacity bitmask in -1 notation */ + *eax = rdt_get_cpuid_10_2_eax_cbm_length(); + /* Capability bit mask */ + *ebx = rdt_cpuid_10_2_ebx_cbm_enabled(); + /* Support for n COS masks (zero-referenced)*/ + *edx = rdt_get_cpuid_10_2_edx_cos_max(); + break; + case 3: + /* Max throttling value -1 (89 means 90) */ + *eax = rdt_get_cpuid_10_3_eax_thrtl_max(); + /* Linear response of delay values */ + *ecx = rdt_cpuid_10_3_eax_linear_response_enabled(); + /* Max number of CLOS -1 (15 means 16) */ + *edx = rdt_get_cpuid_10_3_edx_cos_max(); + break; + default: + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + break; + } + break; +#endif case 0x1C: if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0b3aca2d02..12a4b989af 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -673,6 +673,7 @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ + FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ FEATURE_WORDS, } FeatureWord; @@ -843,8 +844,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_EBX_INVPCID (1U << 10) /* Restricted Transactional Memory */ #define CPUID_7_0_EBX_RTM (1U << 11) +/* Resource Director Technology Monitoring */ +#define CPUID_7_0_EBX_PQM (1U << 12) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) +/* Resource Director Technology Allocation */ +#define CPUID_7_0_EBX_PQE (1U << 15) /* AVX-512 Foundation */ #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Doubleword & Quadword Instruction */ From patchwork Fri Jul 19 16:29:27 2024 Content-Type: text/plain; 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From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3fZSaZggKCkwAvs1r5wyu22uzs.q204s08-rs9sz121u18.25u@flex--whendrik.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Add RDT features to feature word / TCG. Signed-off-by: Hendrik Wüthrich --- target/i386/cpu.c | 30 ++++++++++++++++++++++++++++-- target/i386/cpu.h | 2 ++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c61981bf82..1cf5e5d5ff 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -864,7 +864,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, CPUID_7_0_EBX_CLFLUSHOPT | \ CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ - CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES | \ + CPUID_7_0_EBX_PQM | CPUID_7_0_EBX_PQE) /* missing: CPUID_7_0_EBX_HLE CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ @@ -900,6 +901,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #define TCG_SGX_12_0_EAX_FEATURES 0 #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 +#define TCG_RDT_15_0_EDX_FEATURES CPUID_15_0_EDX_L3 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1057,7 +1059,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "fsgsbase", "tsc-adjust", "sgx", "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", - NULL, NULL, "mpx", NULL, + "rdt-m", NULL, "mpx", "rdt-a", "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", "pcommit", "clflushopt", "clwb", "intel-pt", "avx512pf", "avx512er", @@ -1607,6 +1609,30 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = TCG_SGX_12_1_EAX_FEATURES, }, + + [FEAT_RDT_10_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + NULL, "l3-cat", "l2-cat", "mba" + }, + .cpuid = { + .eax = 0x10, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + } + }, + [FEAT_RDT_15_0_EDX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [1] = "l3-cmt" + }, + .cpuid = { + .eax = 0xf, + .needs_ecx = true, .ecx = 0, + .reg = R_EDX, + }, + .tcg_features = TCG_RDT_15_0_EDX_FEATURES, + }, }; typedef struct FeatureMask { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 12a4b989af..bf2f3c07a7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -673,7 +673,9 @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ + FEAT_RDT_15_0_EBX, /* CPUID[EAX=0xf,ECX=0].EBX (RDT CMT/MBM) */ FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ + FEAT_RDT_10_0_EBX, /* CPUID[EAX=0x10,ECX=0].EBX (RDT CAT/MBA) */ FEATURE_WORDS, } FeatureWord; From patchwork Fri Jul 19 16:29:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89CFFC3DA5D for ; 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Fri, 19 Jul 2024 09:29:52 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:28 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-9-whendrik@google.com> Subject: [PATCH v1 8/9] Adjust CPUID level for RDT features From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=3gJSaZggKCk8Dyv4u8z1x55x2v.t537v3B-uvCv2454x4B.58x@flex--whendrik.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Adjust minimum CPUID level if RDT monitoring or allocation features are enabled to ensure that CPUID will return them. Signed-off-by: Hendrik Wüthrich --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1cf5e5d5ff..482f980a1f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7590,6 +7590,16 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } + + /* RDT monitoring requires CPUID[0xF] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0xF); + } + + /* RDT allocation requires CPUID[0x10] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x10); + } } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ From patchwork Fri Jul 19 16:29:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13737472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40605C3DA5D for ; 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Fri, 19 Jul 2024 09:29:54 -0700 (PDT) Date: Fri, 19 Jul 2024 16:29:29 +0000 In-Reply-To: <20240719162929.1197154-1-whendrik@google.com> Mime-Version: 1.0 References: <20240719162929.1197154-1-whendrik@google.com> X-Mailer: git-send-email 2.45.2.1089.g2a221341d9-goog Message-ID: <20240719162929.1197154-10-whendrik@google.com> Subject: [PATCH v1 9/9] Adjust level for RDT on full_cpuid_auto_level From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::44a; envelope-from=3gpSaZggKClEF0x6wA13z77z4x.v759x5D-wxEx4676z6D.7Az@flex--whendrik.bounces.google.com; helo=mail-wr1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 19 Jul 2024 13:34:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Make sure that RDT monitoring and allocation features are included in in full_cpuid_auto_level. Signed-off-by: Hendrik Wüthrich --- target/i386/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 482f980a1f..6f5594d3e2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -875,6 +875,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #else #define TCG_7_0_ECX_RDPID 0 #endif + #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ /* CPUID_7_0_ECX_OSPKE is dynamic */ \ CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ @@ -7548,6 +7549,8 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_SVM); x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_15_0_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_10_0_EBX); /* Intel Processor Trace requires CPUID[0x14] */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {