From patchwork Sat Jul 20 09:30:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13737765 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B8AC1B86FD for ; Sat, 20 Jul 2024 09:31:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467876; cv=none; b=pfjYoxmz+ZvyunAB9CHBrKd4JtnCrASmfWKqJbxSMObuiRBlKY2KBh9EBF/jEBMvA2f7KRTEBC/+RRyH/tWXd78Cpr+azQMu2XNgJdjOuUbF18pgQ6ZY7pjw50zAwrZuXVV07bJfWPdLF3WiZWBKrspcTTP2037Upltt2pi60AQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467876; c=relaxed/simple; bh=ERdlLzGa2odaU7i0HYSX4l+QdtrQUmuPDF9e6WPI8e0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G7/btgoYDNvQ0dqsIMKdaAtFukeUnxNeN4Bk6b340IVJElZSgt4IWo3P6Fe3IFpdyimCAQdpSHtMMRF4L1OPKP6CySpWm2rlVdlv3c7LDLS4bzODQDL5Q+6Wl23HkCgKzeVgGsP6+GlKds/SKALksiNdIAF3PAv/0tbojfBKbdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com; spf=none smtp.mailfrom=daynix.com; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b=COMGvs8J; arc=none smtp.client-ip=209.85.216.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=daynix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b="COMGvs8J" Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-2cb5243766dso1518456a91.0 for ; Sat, 20 Jul 2024 02:31:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721467874; x=1722072674; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5yjuBamw9n461E4jaC/9ANa+4rItgiwUD6BgGhyaSGo=; b=COMGvs8Jqt5haRmvsjHQYhb/ALqMHedJ9zy9FaOZWAhYwQj3aMuPVvE1nEHiiExa7R j6fvzVdQjF490721hcrpnSsCFPCRABzc+aoPz9N+goZ4JJpdA+oO59zoEZPQHAYWkY+Q LIHHK6yFUwkOe0tgXlSzuxcOFYd1xjKKuQEzdhJYZUjdytFwHvEUkRkFj8L4ExF92wFg qPQPmlgWm/KiFR7n40cNoYGLkvToQjz7huT2W+/MOh2ULU/683EpUe8p5PYwrO2rlm/E aLYMml9oVNn6WLbCi+r3R0izMWDSSroh4Q0BtLA3YihNVPv/pagM7vFUB+JjRAeCQvny dBNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721467874; x=1722072674; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5yjuBamw9n461E4jaC/9ANa+4rItgiwUD6BgGhyaSGo=; b=SXi7UoVEIj7pVjjK+4+ZClzDxWFMLHdvWHSACTQjEI8/QssQiVwn+/nc/ujl8Eoa5C nkBgpagOWeY+OpG6leYJq8Z7aMjHliy/qyygfd5itwxyz+v2UuZ4bhjLYwIdHvwFjMbE eJ3dHuSQcHPTib03hVwh2hDAKgC2gjQso1mO4l5AY+svKXJGWmeuTx6BcYQ91d7lgZWV Qfn//gYEDHCWlSW3kuY0jVGBrKpU0mZS1JYESvcCeTM9b/Ue2rhyUArctjhPACsdx2pJ nZgv1l7ZoSpcoPO/ao3ZlJF9G2HdRlEkh8DlaEl9HSdvReT3E4XV5d1JmDEIAgJcyyPo pJMA== X-Forwarded-Encrypted: i=1; AJvYcCVJTQIXWOPjprF4hOo4TyLiUh3jGU7ZjIMzTEJBdppr0yj5jt5ALWYsYHcnfMG3R8fLfN5nJsz9Q1pFxCrtPLwkorbT X-Gm-Message-State: AOJu0YyVsgvK2ILZfb1AUKbirhbopZZtJKwo7pkJm23XGBVcU7x4lHj/ x/PZA5LALLjQt+punHdiDxnGDRT72rKUe+4rPTAIwa54rENba1eo3L6zfZjPI78= X-Google-Smtp-Source: AGHT+IHR+NQTRhR3a2TfSAWIUHqlrVOnxn0GDTljibq5mmgHHmG24+/gEcCQ+grdVEK0g9Y/FvpQug== X-Received: by 2002:a17:90b:518e:b0:2c9:8891:e128 with SMTP id 98e67ed59e1d1-2cd1603776amr2182284a91.4.1721467874472; Sat, 20 Jul 2024 02:31:14 -0700 (PDT) Received: from localhost ([157.82.204.122]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2ccf808f08esm3099636a91.36.2024.07.20.02.31.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Jul 2024 02:31:14 -0700 (PDT) From: Akihiko Odaki Date: Sat, 20 Jul 2024 18:30:49 +0900 Subject: [PATCH v4 1/6] target/arm/kvm: Set PMU for host only when available Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240720-pmu-v4-1-2a2b28f6b08f@daynix.com> References: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> In-Reply-To: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 target/arm/kvm.c checked PMU availability but unconditionally set the PMU feature flag for the host CPU model, which is confusing. Set the feature flag only when available. Signed-off-by: Akihiko Odaki --- target/arm/kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 70f79eda33cd..b20a35052f41 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -280,6 +280,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) if (kvm_arm_pmu_supported()) { init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; pmu_supported = true; + features |= 1ULL << ARM_FEATURE_PMU; } if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { @@ -448,7 +449,6 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) features |= 1ULL << ARM_FEATURE_V8; features |= 1ULL << ARM_FEATURE_NEON; features |= 1ULL << ARM_FEATURE_AARCH64; - features |= 1ULL << ARM_FEATURE_PMU; features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; ahcf->features = features; From patchwork Sat Jul 20 09:30:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13737766 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A5EF78283 for ; Sat, 20 Jul 2024 09:31:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467880; cv=none; b=BNM1cFhari+KhAWPQFOFwKr1+9unUvaGFe+YH31xkDUM/WyjdPqWFDx/1gauYDpCOg1RtVfIUk7V1Ox1mAexsNBExyK9x5n/9PQr8rNeelmXfsaNFZvTRiQo56VXo1+ZS3bQK5l3Tl+LncfkG/ucMKIpwe0jnEw99xbZ/l9VlHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467880; c=relaxed/simple; bh=KENOuYqZaiHFs1K/nBKMlxR3X2ehbrO7EpqhimHM6Zs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OnMHIUdxMISv8uZ/xdMhcD5g1/mfdN/K5KNBMkcRguFCwW2TSwSIxi6e2NPnfDOtl2VrruKnOv0dYYAxPSfioa63PflAhWRgoOSa+ZnVXuO+/uR4Qc3O8LQU09WdvMTTZa2GqrgjeH7zeO9Hn7tdE5ZpgF4+ymHmb/Ya6duBV+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com; spf=none smtp.mailfrom=daynix.com; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b=Gk1EPqYU; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=daynix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b="Gk1EPqYU" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1fc587361b6so24665685ad.2 for ; Sat, 20 Jul 2024 02:31:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721467878; x=1722072678; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uuvru8O1Lbu3d3+4LM3J/KSbEI4f7QyyvTpp+vjJrRQ=; b=Gk1EPqYUx6KMFaZECbiGxpHR8qaDmWfXcPOC+xmZd1BSwsgl6C0Kc5PacR2q6Ip4ap MtqGyfQG2VP2wmXyXBcTW/pFftkT6bwssuL/jNOlwFXLQGOwZnLcmuTtE3kWIDnBzuQu y59Db7axNpsgOntrDobvWEI6uvjjuhGJRxo0WG9DZNcihotQYKfl25YmGrx4EeE7HP61 6tTrVFJcT11p1uL5utXrbBEhUQGhrhOnUWJS7Rl833r74TXZl2kyHdm7HTPsWNa+yHl1 1GV5w6mYi7xsdjS6IQ9yO/xbZ6OpcjfvzwdLsdiQF6tLkUNUjs1coote+FnRLC0c3ZLU eDXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721467878; x=1722072678; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uuvru8O1Lbu3d3+4LM3J/KSbEI4f7QyyvTpp+vjJrRQ=; b=mZI5ir1bgrstqKAi8FhykA74R3nGRvLKgjXS2vhOyNgURsld6gi2PVVfXkPzoTqJ1/ 5xLQ7o9J7625hImtLmkY93vOsPw5ezL97P7obGikMKYOv4gL1ciV59iat7PdgLquOjly tFlmdbVhWdqO5jTrE7gJ11qedjqxt0RfwWs9/Z56GN7h/y62/e4jxg2DTMIMmcdoUzMQ jAchERR1PnRUKwRJaEP/IOBLSzK2NCy08KR5Rfq0W6lpKuWQ8MOmI6ApyglysgjVmyFt nNotf89Jv5nV1yXSnRZfMc09xBqAJknQuq+RECuNPmrOC1NCgwB8hy/MqVX8kgOL1NJx jIgQ== X-Forwarded-Encrypted: i=1; AJvYcCUx3wFxzYJaDcew+kZ4ftYwUIVXoWIkghKrk2zGWu9lv0eOoT6Yb4f1TDP2ffAiVcusdKpgDvpNs9BNb7iVG5xRoI/a X-Gm-Message-State: AOJu0YxonPmud9TqFdfvBASxqwXAQiyaGarjj7hkuNL1bFRS5PLd91JN P1k32aFn0m0vBSrY5SqeLGwmEk4aaiWmjTeDAtcqkjklprou6Drw2dqr0zBinRM= X-Google-Smtp-Source: AGHT+IGDxYBQ+UI3zCis37W9PvPyH5SIE5p+oC1cjVEarHMW9QkebJPnPHpAqlSz9NjhoUTUJSYbFQ== X-Received: by 2002:a17:902:c405:b0:1fd:73e6:83b8 with SMTP id d9443c01a7336-1fd745977bamr21122635ad.14.1721467878255; Sat, 20 Jul 2024 02:31:18 -0700 (PDT) Received: from localhost ([157.82.204.122]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-1fd6f28f518sm18251415ad.69.2024.07.20.02.31.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Jul 2024 02:31:17 -0700 (PDT) From: Akihiko Odaki Date: Sat, 20 Jul 2024 18:30:50 +0900 Subject: [PATCH v4 2/6] target/arm/kvm: Do not silently remove PMU Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240720-pmu-v4-2-2a2b28f6b08f@daynix.com> References: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> In-Reply-To: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 kvm_arch_init_vcpu() used to remove PMU when it is not available even if the CPU model needs one. It is semantically incorrect, and may continue execution on a misbehaving host that advertises a CPU model while lacking its PMU. Keep the PMU when the CPU model needs one, and let kvm_arm_vcpu_init() fail if the KVM implementation mismatches with our expectation. Signed-off-by: Akihiko Odaki --- target/arm/kvm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b20a35052f41..849e2e21b304 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1888,13 +1888,8 @@ int kvm_arch_init_vcpu(CPUState *cs) if (!arm_feature(env, ARM_FEATURE_AARCH64)) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; } - if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { - cpu->has_pmu = false; - } if (cpu->has_pmu) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; - } else { - env->features &= ~(1ULL << ARM_FEATURE_PMU); } if (cpu_isar_feature(aa64_sve, cpu)) { assert(kvm_arm_sve_supported()); From patchwork Sat Jul 20 09:30:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13737767 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6829078283 for ; Sat, 20 Jul 2024 09:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467884; cv=none; b=lW/lDz7KRM5gmI/IhjI+Ckiq5oIN4B1dyVYU7nkgtn7SB8s9vlv0kPVrmlf5Iel+fPzpBR5wJNiq20PncYtdSGVFYr5QUKuVtUMwf8CtG3OBKq0ZIkgJcwBZjqvNj3n1rtkSl6kMbXn9vo/pjIEgE+kPKVcLGjGjpqWUuZJTuiQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467884; c=relaxed/simple; bh=tbQF5BcKxA0YVcarKDrPEhr3gUEFDSjtSMkqN4q5EFs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pRGqntVkgj2dWlX6nHoW7nOOBwIJM6CHYvfl6lXWFyv3XIh3X08zbDs+03QJr/pp3vnReXtHGiX7O6XtJHCmfuVp7z54+kBK5pMgg4mfV9HvGyl2cTJ27XSPOonJczpX2Ms6p4PM5mfiwFn1Mqdqpgu26aztUHbqqtuUk9ey+H4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com; spf=none smtp.mailfrom=daynix.com; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b=Po4RNyB0; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=daynix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b="Po4RNyB0" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1fc52394c92so23547585ad.1 for ; Sat, 20 Jul 2024 02:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721467883; x=1722072683; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r7Pn/awe7YFbUwLON8GOovUdtzCktNX5WHOGmuP4ywM=; b=Po4RNyB0/3naYN2Fia5923QIRHDVqrqD+s2C7gFSKls9m/VkJ52e4YCD/8miGgtuVJ Itdk/cii/40RA7doHyDIgWUSbyaUsQsIZn7iBdsfEJOXZinYWYasN4H7WCZ0xceQmZ/S 5LfYjOdq1Rcfc3Yg1926pqiz9Ns5TnUTjOUZog10wLkuyPls8XJSGczkUcrVLzAmxrhD 78oR4l0wRUiuYmQLQM4aYKRCA+BkY58cHlF6H/6ylotDRIH4jJS4TnNaVZ/4nJoQDeQN uypk3wlPIP9sBmxmc7PpH4WR874i2/FzGZgL4DQZpGrBWmZ3bxkJVyuCeBBDX7CCJZVQ 1yCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721467883; x=1722072683; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7Pn/awe7YFbUwLON8GOovUdtzCktNX5WHOGmuP4ywM=; b=wKWCNVZlFQTfc8mhS7J/KrKyg7rJFZdPhKISjthNonJAXkkUJV78yfi6A6m8mkaSjO cPcUh6hghs8FsHSf9Bk9Gtb+0UDbvcV1QwKxOduKZxlcQrcpavuREXbXlwwIa2K9Y6IU //GePPXgjkwQzijD1Ea7YO2HGHMIymPFhz/1MchsM+rCIMFEDm5shETwPoHKgCSdL2gS Yo81Y5LVawiIvv7j0Z8GRshGF7pQ1x5aIzHlXT1vTDVr8DdZErx9K9MI6CF0Fq0V4b52 Bo9+LnraPQmbdacLBfKhOI+7kjFZVO/lXlF4jzqo1beLcvKPRTN8s7EKfUocW/FGpZsz BSnQ== X-Forwarded-Encrypted: i=1; AJvYcCVccVmXXYgRkS5RO6Q/E6kzMZjCg1fOgP5DPZxsXyXIZ8VZaYLczV2+E7noLutL3Fm6wMrUWhLgyV8/gUF92wVJ0D3o X-Gm-Message-State: AOJu0Yyi0u1kmJ/qVdqZ+7r21fPqa7kKIW5jUnbWs3wv76GFLuV6qp4e /XQpFCUkbWj21k05pY8wIx2gjxIcLPOGb06aV/6zF9bxfxvh+UGhglsEobCkMKo= X-Google-Smtp-Source: AGHT+IFuUHFAzQo566bTzAMkFSDEqpnCRbmcEzn8TLq/DlebkV9YSGugyGdb6Hgs68lyvmeUqWCK3A== X-Received: by 2002:a17:902:f682:b0:1fb:9cb0:3e2f with SMTP id d9443c01a7336-1fd74573c4bmr20335395ad.27.1721467882736; Sat, 20 Jul 2024 02:31:22 -0700 (PDT) Received: from localhost ([157.82.204.122]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-1fd6f3181desm18119545ad.128.2024.07.20.02.31.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Jul 2024 02:31:22 -0700 (PDT) From: Akihiko Odaki Date: Sat, 20 Jul 2024 18:30:51 +0900 Subject: [PATCH v4 3/6] target/arm: Always add pmu property for Armv7-A/R+ Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240720-pmu-v4-3-2a2b28f6b08f@daynix.com> References: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> In-Reply-To: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 kvm-steal-time and sve properties are added for KVM even if the corresponding features are not available. Always add pmu property for Armv8. Note that the property is added only for Armv7-A/R+ as QEMU currently emulates PMU only for such versions, and a different version may have a different definition of PMU or may not have one at all. Signed-off-by: Akihiko Odaki --- target/arm/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c239181..c1955a82fb3c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1741,6 +1741,10 @@ void arm_cpu_post_init(Object *obj) if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); + + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); + } } if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { @@ -1770,7 +1774,6 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { cpu->has_pmu = true; - object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); } /* From patchwork Sat Jul 20 09:30:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13737768 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FD6876034 for ; Sat, 20 Jul 2024 09:31:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467888; cv=none; b=na63gk7gont9LF1CMDCqeaneASz73trTYTrclZg2/xF0PNKQEMHsvsRfgvQA4Q5TWU6K57hO1YAYdqW9DhewTI5PoeTPJTfZAP46rZKU6iGKpeO/M2Wu86oiwT6VPF5E88vLlqxhB7miGTIWCIa/At+95bjQ+Z72tWvrVVsqBC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467888; c=relaxed/simple; bh=pFdmGOsXnNL9jY7lXR47yIRG8HPGtYn5D0ALUwzKE78=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aoTiqv9om0fK2GPBwzuRk3vJL6qr+XTQ2fY9Uyz4KDt7X9InpYmosbVFplsVNzBEPVzyEmWmtU357O4lbTxhg3/DxQZ3epE4P1UqL3clx4iUivFBUJfs5N56kY6onLJLOhGOq5oscz4yibAWaF9+qGTCuFxCxGJGt+z8L2swm00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com; spf=none smtp.mailfrom=daynix.com; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b=TSl9s2Mi; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=daynix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b="TSl9s2Mi" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-2caaae31799so1644603a91.0 for ; Sat, 20 Jul 2024 02:31:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721467886; x=1722072686; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zyb9AANp083iaNY8Z+adG9wP/HNnG5GrtOuS/kU6QUk=; b=TSl9s2Mi2xpeaAmd4mxXmbDbz3d9VhuFDTVSuwF4jCG1R+hfiszTuAewHpNH9Hwn+R a4G8Z7frUFNeVLRbJIj+hCu6+jK68WwdQg2fN6n1EQQiYE4Nh5kpUN07m37E1Yb2lURs sG7L7YVKJ+ppLTi+q2z+wxyXi38Y4VaBhT+31RzceiEOI2F2v5qcU2AX6UX5dP29olXc UKD3N7CEBmkdGG/97TRtN/bopy6Q+GCwUGJECbTaSCmYWOuWXDR4ByXZeLabPbR5ntY5 AQr4FlciLUj6ei04wYlWOvw+O8M0z46IwLDa5pOUu+LuwSINSM9LkQFNFLtmhCShw5n3 9VKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721467886; x=1722072686; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zyb9AANp083iaNY8Z+adG9wP/HNnG5GrtOuS/kU6QUk=; b=oNe6i8Sx02sg1bURxUq6Xk+Bwa32V8MmXGZUGSrLgx5aon4vwqyooA1RSDMFiVCjyB U2TfuLWF+Y4vJXBargZj8vwNy/8J5p6YGjU6qE+JGnm0+P3PgU8VHCKgqIGLdOrQOuhT 5xB5Ic9awq9uL9d0wGMD0DV7S7n+1Vewl30GefAsQEnsWqErZo/rAz1hn5/E76GDZX2g YqTS/wLXJ55+g9rXKx9me97kTPLju3DDSTDg0aCUofek6U2L9bcTGVkm+m/sCZLye/2w AwGhxxwJmQl0u2fSh/ah9BS33BsGWiLQYxJWqktC2syE9lmKZT7WkzTGwmDIzX4ILt4y cJ4A== X-Forwarded-Encrypted: i=1; AJvYcCU8+L4S4qQzAcSBQtXWmB/nJT2NmXETLnyLhVV9r4J/Si2/dZ8bkek+zyEUaz1PiLO4tuiR1wEB5EetemMzy3EjnHXZ X-Gm-Message-State: AOJu0YziGadrXFCBm21Q4WtB5ncUK0vlnAJiR8WIEo+sIvypJ0D3Cxbu 614d9jGU7QzcP4OB2F536jDdc1cqqjGezunIa8F8F4cWqwGNMB7jRlJrPgwICN0= X-Google-Smtp-Source: AGHT+IFLK7YAa8KVAxsj8+pIl37nqSE3PlIwtNlg+Ie+K7ixATPTr/4qrNsV0Adtr+FdH2XvbPWsOg== X-Received: by 2002:a17:90a:5993:b0:2c9:5f45:5d26 with SMTP id 98e67ed59e1d1-2cd27432453mr681429a91.19.1721467886441; Sat, 20 Jul 2024 02:31:26 -0700 (PDT) Received: from localhost ([157.82.204.122]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2ccf7c5391bsm3130441a91.24.2024.07.20.02.31.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Jul 2024 02:31:26 -0700 (PDT) From: Akihiko Odaki Date: Sat, 20 Jul 2024 18:30:52 +0900 Subject: [PATCH v4 4/6] hvf: arm: Raise an exception for sysreg by default Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240720-pmu-v4-4-2a2b28f6b08f@daynix.com> References: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> In-Reply-To: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Any sysreg access results in an exception unless defined otherwise so we should raise an exception by default. Signed-off-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 174 +++++++++++++++++++++++++-------------------------- 1 file changed, 85 insertions(+), 89 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index eb090e67a2f8..1a749534fb0d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1199,57 +1199,56 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) return false; } -static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) +static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) { ARMCPU *arm_cpu = ARM_CPU(cpu); CPUARMState *env = &arm_cpu->env; - uint64_t val = 0; switch (reg) { case SYSREG_CNTPCT_EL0: - val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(arm_cpu); - break; + return 0; case SYSREG_PMCR_EL0: - val = env->cp15.c9_pmcr; - break; + *val = env->cp15.c9_pmcr; + return 0; case SYSREG_PMCCNTR_EL0: pmu_op_start(env); - val = env->cp15.c15_ccnt; + *val = env->cp15.c15_ccnt; pmu_op_finish(env); - break; + return 0; case SYSREG_PMCNTENCLR_EL0: - val = env->cp15.c9_pmcnten; - break; + *val = env->cp15.c9_pmcnten; + return 0; case SYSREG_PMOVSCLR_EL0: - val = env->cp15.c9_pmovsr; - break; + *val = env->cp15.c9_pmovsr; + return 0; case SYSREG_PMSELR_EL0: - val = env->cp15.c9_pmselr; - break; + *val = env->cp15.c9_pmselr; + return 0; case SYSREG_PMINTENCLR_EL1: - val = env->cp15.c9_pminten; - break; + *val = env->cp15.c9_pminten; + return 0; case SYSREG_PMCCFILTR_EL0: - val = env->cp15.pmccfiltr_el0; - break; + *val = env->cp15.pmccfiltr_el0; + return 0; case SYSREG_PMCNTENSET_EL0: - val = env->cp15.c9_pmcnten; - break; + *val = env->cp15.c9_pmcnten; + return 0; case SYSREG_PMUSERENR_EL0: - val = env->cp15.c9_pmuserenr; - break; + *val = env->cp15.c9_pmuserenr; + return 0; case SYSREG_PMCEID0_EL0: case SYSREG_PMCEID1_EL0: /* We can't really count anything yet, declare all events invalid */ - val = 0; - break; + *val = 0; + return 0; case SYSREG_OSLSR_EL1: - val = env->cp15.oslsr_el1; - break; + *val = env->cp15.oslsr_el1; + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ - break; + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1276,9 +1275,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ - if (!hvf_sysreg_read_cp(cpu, reg, &val)) { - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; + if (hvf_sysreg_read_cp(cpu, reg, &val)) { + return 0; } break; case SYSREG_DBGBVR0_EL1: @@ -1297,8 +1295,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGBVR13_EL1: case SYSREG_DBGBVR14_EL1: case SYSREG_DBGBVR15_EL1: - val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGBCR0_EL1: case SYSREG_DBGBCR1_EL1: case SYSREG_DBGBCR2_EL1: @@ -1315,8 +1313,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGBCR13_EL1: case SYSREG_DBGBCR14_EL1: case SYSREG_DBGBCR15_EL1: - val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGWVR0_EL1: case SYSREG_DBGWVR1_EL1: case SYSREG_DBGWVR2_EL1: @@ -1333,8 +1331,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGWVR13_EL1: case SYSREG_DBGWVR14_EL1: case SYSREG_DBGWVR15_EL1: - val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGWCR0_EL1: case SYSREG_DBGWCR1_EL1: case SYSREG_DBGWCR2_EL1: @@ -1351,35 +1349,25 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) case SYSREG_DBGWCR13_EL1: case SYSREG_DBGWCR14_EL1: case SYSREG_DBGWCR15_EL1: - val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; - break; + *val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; + return 0; default: if (is_id_sysreg(reg)) { /* ID system registers read as RES0 */ - val = 0; - break; + *val = 0; + return 0; } - cpu_synchronize_state(cpu); - trace_hvf_unhandled_sysreg_read(env->pc, reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; } - trace_hvf_sysreg_read(reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg), - val); - hvf_set_reg(cpu, rt, val); - - return 0; + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_read(env->pc, reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } static void pmu_update_irq(CPUARMState *env) @@ -1503,7 +1491,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) pmu_op_start(env); env->cp15.c15_ccnt = val; pmu_op_finish(env); - break; + return 0; case SYSREG_PMCR_EL0: pmu_op_start(env); @@ -1523,45 +1511,45 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); pmu_op_finish(env); - break; + return 0; case SYSREG_PMUSERENR_EL0: env->cp15.c9_pmuserenr = val & 0xf; - break; + return 0; case SYSREG_PMCNTENSET_EL0: env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); - break; + return 0; case SYSREG_PMCNTENCLR_EL0: env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); - break; + return 0; case SYSREG_PMINTENCLR_EL1: pmu_op_start(env); env->cp15.c9_pminten |= val; pmu_op_finish(env); - break; + return 0; case SYSREG_PMOVSCLR_EL0: pmu_op_start(env); env->cp15.c9_pmovsr &= ~val; pmu_op_finish(env); - break; + return 0; case SYSREG_PMSWINC_EL0: pmu_op_start(env); pmswinc_write(env, val); pmu_op_finish(env); - break; + return 0; case SYSREG_PMSELR_EL0: env->cp15.c9_pmselr = val & 0x1f; - break; + return 0; case SYSREG_PMCCFILTR_EL0: pmu_op_start(env); env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; pmu_op_finish(env); - break; + return 0; case SYSREG_OSLAR_EL1: env->cp15.oslsr_el1 = val & 1; - break; + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ - break; + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1591,10 +1579,10 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) if (!hvf_sysreg_write_cp(cpu, reg, val)) { hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); } - break; + return 0; case SYSREG_MDSCR_EL1: env->cp15.mdscr_el1 = val; - break; + return 0; case SYSREG_DBGBVR0_EL1: case SYSREG_DBGBVR1_EL1: case SYSREG_DBGBVR2_EL1: @@ -1612,7 +1600,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGBVR14_EL1: case SYSREG_DBGBVR15_EL1: env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; - break; + return 0; case SYSREG_DBGBCR0_EL1: case SYSREG_DBGBCR1_EL1: case SYSREG_DBGBCR2_EL1: @@ -1630,7 +1618,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGBCR14_EL1: case SYSREG_DBGBCR15_EL1: env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; - break; + return 0; case SYSREG_DBGWVR0_EL1: case SYSREG_DBGWVR1_EL1: case SYSREG_DBGWVR2_EL1: @@ -1648,7 +1636,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGWVR14_EL1: case SYSREG_DBGWVR15_EL1: env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; - break; + return 0; case SYSREG_DBGWCR0_EL1: case SYSREG_DBGWCR1_EL1: case SYSREG_DBGWCR2_EL1: @@ -1666,20 +1654,18 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_DBGWCR14_EL1: case SYSREG_DBGWCR15_EL1: env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; - break; - default: - cpu_synchronize_state(cpu); - trace_hvf_unhandled_sysreg_write(env->pc, reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; + return 0; } - return 0; + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_write(env->pc, reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } static int hvf_inject_interrupts(CPUState *cpu) @@ -1944,7 +1930,17 @@ int hvf_vcpu_exec(CPUState *cpu) int sysreg_ret = 0; if (isread) { - sysreg_ret = hvf_sysreg_read(cpu, reg, rt); + sysreg_ret = hvf_sysreg_read(cpu, reg, &val); + if (!sysreg_ret) { + trace_hvf_sysreg_read(reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg), + val); + hvf_set_reg(cpu, rt, val); + } } else { val = hvf_get_reg(cpu, rt); sysreg_ret = hvf_sysreg_write(cpu, reg, val); From patchwork Sat Jul 20 09:30:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13737769 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA36347C2 for ; Sat, 20 Jul 2024 09:31:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467893; cv=none; b=UHL+tYucAe6gXPNQ1CY+dzIaNUh50t54yYTKDo5NsZUFehq13bfv+8yBlhclWEpETfrmqZha3Dh9YiF2E65tzlvLjTygPf2P16ijXrx0Ako1rXe4wSjCktURvDeZVXSqLJCewSLOEIPamt6GL1Cdz5An+ZJ9b8uY1C5YOshA9no= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467893; c=relaxed/simple; bh=u7g12Srt7e/9/2tFuU5dbXUVHOQ8y8JmdkVrGzLFbK4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bZJuKyjwbsZ4W5FanVr4Fi62Hjd+j5asNlp576D/7W6aQn4eTfeGANnYgzfjcHjso+l0UnD7MABSXATybg61aUH8UXPan9r2OA221mdtHRPDe6yoauTSshYPu1dXmKMsGFo0D2uof9q/ORIJG26JgfKLARHfeLAPICEi6Quxcmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com; spf=none smtp.mailfrom=daynix.com; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b=Qnxt+0Kf; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=daynix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b="Qnxt+0Kf" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1fc2a194750so26654145ad.1 for ; Sat, 20 Jul 2024 02:31:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721467891; x=1722072691; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=99AglDGYDKt8UyQF0+i2KqD6ZLYCDLBz3EOwXuGJkA8=; b=Qnxt+0KfhcVpKVSiqSqL3RrmzFjTbFoSJ1xnKX1VGkRM4BTjxCuXkebv2exsbTmvdI RW8yeTHw9PVZ7p83K0tHWq8yerH2Dn4h595Lsv7g4RBdr3HXjmNjpaAOmF9SHr1vuFR0 Z4uFg5oiwr7VJ9PfPLeTaVJQrFsTxoI28rbqFcTwoAxPT4OT5CPO6lDQTRWKukfbdkhb x7MPY9SMENzZ9bYj2ZXzNXbXQ2/oDpDQJPw2qsj1pIGjV2fArIjA1WiU8mNcKAUhBlws hapL20Fz5R8qIueCcrt4Kes3SbTjUa1vMjuuIDg1yvyWbUQPS7Q9Wse+n21TMpnpa3TY LD5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721467891; x=1722072691; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=99AglDGYDKt8UyQF0+i2KqD6ZLYCDLBz3EOwXuGJkA8=; b=ux/rJ8RZ0zhQosM7rgJqtftp62DxZvKJDIs1Ia0DgPrChv3jNLziYw+yfoGTqg+ZBn c3tpj11ZdhjpB+j1CM6ahlgyPS1t4iI3l3VnVErA/C7UfINBeCCpeSstRpgMgdSJ79kW mh+GDuZo2jj53v/ImWyUCsf4G81V2nBLaTE4KMFtP238K1PoN4ZT6vck23NvTRKU0r1m GCp36fS64uIyWXJEKRIf/tfWH/Uyr7+/Z5YWXWabF2UDZumMx20IHmEzNwI0Zj0EuoOd AwLxiaXoTdA72tJqcpDCEipH9Yb9AAKM5Ss/jdKALaPFGgczFiCZwsIzL+4Mr1cHFq/9 0L9A== X-Forwarded-Encrypted: i=1; AJvYcCWZCJyYC0aNcdc+5lK3Z1mCuVtAlWEAozmDbzFk3cDeYIOI+1y2PjtiDT71sQ8LExo0m98XXnT2nCnia2OBsOzG8SrG X-Gm-Message-State: AOJu0YyiPNtJhDOT9lkphVKqpXlrigNjL8nAYZbkWvhiDoEVhzolZNWF Z111Du7MceBd8MGI5L71nYIDKPB12Vhv8Kz6nl5WTxeQb0lYZ+TkglgmOyiJAXZfzZzTcDhCLpy LgoQ= X-Google-Smtp-Source: AGHT+IGilupQDoh1YjZT0MqsC5EdkPJxgrupVuH9NgGrPu/6pkbEQMPZjNYjiWTJHABuEd78H+Srqg== X-Received: by 2002:a05:6a20:12cd:b0:1c3:b1b3:75cf with SMTP id adf61e73a8af0-1c4285d386fmr1147019637.14.1721467890772; Sat, 20 Jul 2024 02:31:30 -0700 (PDT) Received: from localhost ([157.82.204.122]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2cb77504fa2sm4228362a91.46.2024.07.20.02.31.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Jul 2024 02:31:30 -0700 (PDT) From: Akihiko Odaki Date: Sat, 20 Jul 2024 18:30:53 +0900 Subject: [PATCH v4 5/6] hvf: arm: Properly disable PMU Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240720-pmu-v4-5-2a2b28f6b08f@daynix.com> References: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> In-Reply-To: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Setting pmu property used to have no effect for hvf so fix it. Signed-off-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 184 +++++++++++++++++++++++++++------------------------ 1 file changed, 97 insertions(+), 87 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 1a749534fb0d..adcdfae0b17f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1204,45 +1204,50 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) ARMCPU *arm_cpu = ARM_CPU(cpu); CPUARMState *env = &arm_cpu->env; + if (arm_feature(env, ARM_FEATURE_PMU)) { + switch (reg) { + case SYSREG_PMCR_EL0: + *val = env->cp15.c9_pmcr; + return 0; + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + *val = env->cp15.c15_ccnt; + pmu_op_finish(env); + return 0; + case SYSREG_PMCNTENCLR_EL0: + *val = env->cp15.c9_pmcnten; + return 0; + case SYSREG_PMOVSCLR_EL0: + *val = env->cp15.c9_pmovsr; + return 0; + case SYSREG_PMSELR_EL0: + *val = env->cp15.c9_pmselr; + return 0; + case SYSREG_PMINTENCLR_EL1: + *val = env->cp15.c9_pminten; + return 0; + case SYSREG_PMCCFILTR_EL0: + *val = env->cp15.pmccfiltr_el0; + return 0; + case SYSREG_PMCNTENSET_EL0: + *val = env->cp15.c9_pmcnten; + return 0; + case SYSREG_PMUSERENR_EL0: + *val = env->cp15.c9_pmuserenr; + return 0; + case SYSREG_PMCEID0_EL0: + case SYSREG_PMCEID1_EL0: + /* We can't really count anything yet, declare all events invalid */ + *val = 0; + return 0; + } + } + switch (reg) { case SYSREG_CNTPCT_EL0: *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(arm_cpu); return 0; - case SYSREG_PMCR_EL0: - *val = env->cp15.c9_pmcr; - return 0; - case SYSREG_PMCCNTR_EL0: - pmu_op_start(env); - *val = env->cp15.c15_ccnt; - pmu_op_finish(env); - return 0; - case SYSREG_PMCNTENCLR_EL0: - *val = env->cp15.c9_pmcnten; - return 0; - case SYSREG_PMOVSCLR_EL0: - *val = env->cp15.c9_pmovsr; - return 0; - case SYSREG_PMSELR_EL0: - *val = env->cp15.c9_pmselr; - return 0; - case SYSREG_PMINTENCLR_EL1: - *val = env->cp15.c9_pminten; - return 0; - case SYSREG_PMCCFILTR_EL0: - *val = env->cp15.pmccfiltr_el0; - return 0; - case SYSREG_PMCNTENSET_EL0: - *val = env->cp15.c9_pmcnten; - return 0; - case SYSREG_PMUSERENR_EL0: - *val = env->cp15.c9_pmuserenr; - return 0; - case SYSREG_PMCEID0_EL0: - case SYSREG_PMCEID1_EL0: - /* We can't really count anything yet, declare all events invalid */ - *val = 0; - return 0; case SYSREG_OSLSR_EL1: *val = env->cp15.oslsr_el1; return 0; @@ -1486,64 +1491,69 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) SYSREG_OP2(reg), val); - switch (reg) { - case SYSREG_PMCCNTR_EL0: - pmu_op_start(env); - env->cp15.c15_ccnt = val; - pmu_op_finish(env); - return 0; - case SYSREG_PMCR_EL0: - pmu_op_start(env); + if (arm_feature(env, ARM_FEATURE_PMU)) { + switch (reg) { + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + env->cp15.c15_ccnt = val; + pmu_op_finish(env); + return 0; + case SYSREG_PMCR_EL0: + pmu_op_start(env); - if (val & PMCRC) { - /* The counter has been reset */ - env->cp15.c15_ccnt = 0; - } + if (val & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } - if (val & PMCRP) { - unsigned int i; - for (i = 0; i < pmu_num_counters(env); i++) { - env->cp15.c14_pmevcntr[i] = 0; + if (val & PMCRP) { + unsigned int i; + for (i = 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] = 0; + } } - } - env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; - env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); + env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; + env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); - pmu_op_finish(env); - return 0; - case SYSREG_PMUSERENR_EL0: - env->cp15.c9_pmuserenr = val & 0xf; - return 0; - case SYSREG_PMCNTENSET_EL0: - env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); - return 0; - case SYSREG_PMCNTENCLR_EL0: - env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); - return 0; - case SYSREG_PMINTENCLR_EL1: - pmu_op_start(env); - env->cp15.c9_pminten |= val; - pmu_op_finish(env); - return 0; - case SYSREG_PMOVSCLR_EL0: - pmu_op_start(env); - env->cp15.c9_pmovsr &= ~val; - pmu_op_finish(env); - return 0; - case SYSREG_PMSWINC_EL0: - pmu_op_start(env); - pmswinc_write(env, val); - pmu_op_finish(env); - return 0; - case SYSREG_PMSELR_EL0: - env->cp15.c9_pmselr = val & 0x1f; - return 0; - case SYSREG_PMCCFILTR_EL0: - pmu_op_start(env); - env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; - pmu_op_finish(env); - return 0; + pmu_op_finish(env); + return 0; + case SYSREG_PMUSERENR_EL0: + env->cp15.c9_pmuserenr = val & 0xf; + return 0; + case SYSREG_PMCNTENSET_EL0: + env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); + return 0; + case SYSREG_PMCNTENCLR_EL0: + env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); + return 0; + case SYSREG_PMINTENCLR_EL1: + pmu_op_start(env); + env->cp15.c9_pminten |= val; + pmu_op_finish(env); + return 0; + case SYSREG_PMOVSCLR_EL0: + pmu_op_start(env); + env->cp15.c9_pmovsr &= ~val; + pmu_op_finish(env); + return 0; + case SYSREG_PMSWINC_EL0: + pmu_op_start(env); + pmswinc_write(env, val); + pmu_op_finish(env); + return 0; + case SYSREG_PMSELR_EL0: + env->cp15.c9_pmselr = val & 0x1f; + return 0; + case SYSREG_PMCCFILTR_EL0: + pmu_op_start(env); + env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; + pmu_op_finish(env); + return 0; + } + } + + switch (reg) { case SYSREG_OSLAR_EL1: env->cp15.oslsr_el1 = val & 1; return 0; From patchwork Sat Jul 20 09:30:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13737770 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D961347C2 for ; Sat, 20 Jul 2024 09:31:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467896; cv=none; b=W8IeMX8vZioNp2QpLPcVVjLRHMW/SxC0rewfCb7BdJEw56opSH9n4UO7BKcYVttnUcM82WXDjAg4ZE9Q2psHUCUGGJ9kRteRwfqoFdsagOrrkGBapyN8PLVBsxJE0yCD6ZjnA6E2x6OM3r25wZkvVzYSH8TJT84TsFJXxJOA6sk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721467896; c=relaxed/simple; bh=DYnqaWjAQ5Swa7SOrX13jfrs0jdvTL9wDFwzo29zQ9U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MqINVxP3+VMDfcvKBs0aHOMEmSsg4Ze08pSv+yQNY6hXtV85e17DyvJoCQkU5d9tS8IhwbzBLFqLippLgQReayLfu+TiwIGT9wtAAcaT56KL2etYL7FaTQWEkM3kRPHk8an1hPM79ej7Rknpwm4AaIg1soeP4moB4BZaq1Jr6g0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com; spf=none smtp.mailfrom=daynix.com; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b=TTbgd7+1; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=daynix.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=daynix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=daynix-com.20230601.gappssmtp.com header.i=@daynix-com.20230601.gappssmtp.com header.b="TTbgd7+1" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-70d01e4f7fcso829442b3a.1 for ; Sat, 20 Jul 2024 02:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1721467894; x=1722072694; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wrhfxyQiCKIug187Kcca0q3LwAZ1kZXZGPDwQT1UwgA=; b=TTbgd7+1e9cfH7smSr5Qsu0a1xhcQcKYwvP8XwTyK4EaLHNi/G5K/V9UZIGj0WU8rg Kw6zyp2HXSj1+rUVMcE/NsqeOodlDmGe5A9EyfI2O7cNpXOdaRA7aQGT4c+Dj3Zkc5hj zYKbxP+WjhcN1OB6Mr2W7nGvTUSEHEfhcUOtrk1Sgm6NyrOC1dwnsZQXLSPMg0zoyYH5 kuw+MFBIpdJnnuopQjF0c+7fAcJcfS4jhrVDmqSn/uxHfRLvBnfutieSg5IO5g10iPwz m3lq5HaKbJU1ZANUGfcnEPQux1WU57tUMWIHY0Z9pJUGFkoYxlwizkrpEsh5yAEftxjx G5ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721467894; x=1722072694; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wrhfxyQiCKIug187Kcca0q3LwAZ1kZXZGPDwQT1UwgA=; b=VLwcGhns+VplRfxML3pZ+GP+/ofRDZVTofmYMxmMRWMIaIzQ963EA6NS0YURpj0BPM rMxU4nAZ3Xdc2T79ekjVRWhV4LqvOv6cyIJVD4YiFFX9PP3TJxLwVk9inVgv8EsJj3Z4 yHV0KepFDMC5OWuOueoFGxWYnW77NtfXUpARm0tVpqQaMZz0bFtZDgo+RIfWvspfo/CC EiTfTN9h+yq6c7g5rIDIpybckIBP08qioAw+Z+5IRcTlQt/rTPZ7IoKKFsBEOSukOK50 +B+xQh3MnDpWpd6SJlYDXzQEadbfnbAGLhXA7B5RIwS6O6fmxB1lurPtVGQXsNj1yKdj gDpA== X-Forwarded-Encrypted: i=1; AJvYcCVlVMPO6LSXiG2WdcjQDQSBpyiLY3t8FFZMmS5HVTBbq9c4MDRyEC2MqMXX95174gZaOCb0VwZ3xT0FFwJAr8VGVgGe X-Gm-Message-State: AOJu0YwGRNcBFY+ort0qgfJUlnf1oZrxTsXLhd/CtbUqHCQ61vCSRj5Q BoYJcHWGYaBZZtwzXWhdP4HgV2jDRKU16in+s/LB3IlqV0E2Ronr/5TvfyoJpxM= X-Google-Smtp-Source: AGHT+IEXOqSyEy2UA66P9jRHggHMp/WMJoRJ7yRzlzsXWfBfVUa9ITQgOCdoVMCmOnpVU5hdmZPN4A== X-Received: by 2002:a05:6a00:1887:b0:70a:fa5d:ad97 with SMTP id d2e1a72fcca58-70d0ef82323mr719873b3a.1.1721467894392; Sat, 20 Jul 2024 02:31:34 -0700 (PDT) Received: from localhost ([157.82.204.122]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-70cff552c39sm2341661b3a.136.2024.07.20.02.31.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Jul 2024 02:31:34 -0700 (PDT) From: Akihiko Odaki Date: Sat, 20 Jul 2024 18:30:54 +0900 Subject: [PATCH v4 6/6] hvf: arm: Do not advance PC when raising an exception Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240720-pmu-v4-6-2a2b28f6b08f@daynix.com> References: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> In-Reply-To: <20240720-pmu-v4-0-2a2b28f6b08f@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini , Cornelia Huck Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 This is identical with commit 30a1690f2402 ("hvf: arm: Do not advance PC when raising an exception") but for writes instead of reads. Fixes: a2260983c655 ("hvf: arm: Add support for GICv3") Signed-off-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index adcdfae0b17f..c1496ad5be9b 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1586,10 +1586,10 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ - if (!hvf_sysreg_write_cp(cpu, reg, val)) { - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + if (hvf_sysreg_write_cp(cpu, reg, val)) { + return 0; } - return 0; + break; case SYSREG_MDSCR_EL1: env->cp15.mdscr_el1 = val; return 0;