From patchwork Sat Jul 20 11:04:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13737792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AC2EC3DA59 for ; Sat, 20 Jul 2024 11:05:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=w8/U6d+p968EovP8vT5UxOg0spebu7g8lnn121bQwlY=; b=0cq8H8sE2U3FSbQTw1Y5lAWYr9 mjirK6InvNeRUhr1AGY6ajKumVxhc3Ifh8rH6aZUc8eBjquGZRmWI04UOo+mt3DEdNnnxIkp2vWXf Zq2zvBRebIHuOLEEkS6tE97pJ/o5nWC49stkgNyEOoPl/N+ysBqq+MK3n2jaYfjNqJX4XQvzpifNu PdY3B8fK9GOXQ/rpxETXPfsVDG4iLN53ctSHuDqr+tfoDFN3L4dPf+rTt9AqKh3X9kgYGOQmuodl/ TqTbKoPBIMtqpSz8FI/aR/xCD4YnNwj/mRDXli0q4H2obySzmxscR27YaQ1TB1c4FBlSvAyZwgBq1 wRSIBOEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sV7uB-00000004yLu-24Q0; Sat, 20 Jul 2024 11:05:35 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sV7to-00000004yHp-0ygk for linux-arm-kernel@lists.infradead.org; Sat, 20 Jul 2024 11:05:14 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46KB4xJA003268; Sat, 20 Jul 2024 06:04:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1721473499; bh=w8/U6d+p968EovP8vT5UxOg0spebu7g8lnn121bQwlY=; h=From:To:CC:Subject:Date; b=Eu9BHq8GUGyrqsy8HNRD1aci2wNzOvsZoISY1ngf90ftDwBNdFVfpZ2ZJODBS4LXD pRyf1AID4F8IGnB8nhBzEIhNMakf7pOgoI9MMo3G5mgT1k5qzX/h2vchEnCUvaY+14 1QWPPS067pW+owbg0u5vBZqeemaMXvTW79LST5C8= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46KB4xqm103162 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 20 Jul 2024 06:04:59 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 20 Jul 2024 06:04:59 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 20 Jul 2024 06:04:59 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46KB4t58050410; Sat, 20 Jul 2024 06:04:56 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH] arm64: dts: ti: k3-j784s4-evm: Use 4 lanes for PCIe0 on EVM Date: Sat, 20 Jul 2024 16:34:55 +0530 Message-ID: <20240720110455.3043327-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240720_040512_458987_BB8896DE X-CRM114-Status: GOOD ( 11.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4 lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM via SERDES1. Since SERDES1 is not being used by any peripheral apart from PCIe0, use all 4 lanes of SERDES1 for PCIe0. Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode") Signed-off-by: Siddharth Vadapalli --- Hello, This patch is based on linux-next tagged next-20240715. Patch has been tested on J784S4-EVM. Logs: https://gist.github.com/Siddharth-Vadapalli-at-TI/2b9b1196ff6b9eac895a7986e5ff4456 NOTE: Patch applies cleanly on Mainline Linux's latest commit 3c3ff7be9729 Merge tag 'powerpc-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index ffa38f41679d..ea27519d7b89 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -1407,10 +1407,11 @@ &serdes1 { serdes1_pcie0_link: phy@0 { reg = <0>; - cdns,num-lanes = <2>; + cdns,num-lanes = <4>; #phy-cells = <0>; cdns,phy-type = ; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, + <&serdes_wiz1 3>, <&serdes_wiz1 4>; }; };