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Mon, 22 Jul 2024 02:19:33 -0700 (PDT) Received: from [192.168.1.191] ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d68fa493sm120765705e9.10.2024.07.22.02.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 02:19:33 -0700 (PDT) From: Rayyan Ansari Date: Mon, 22 Jul 2024 10:18:50 +0100 Subject: [PATCH v2] dt-bindings: PCI: qcom,pcie-sc7280: specify eight interrupts Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240722-sc7280-pcie-interrupts-v2-1-a5414d3dbc64@linaro.org> X-B4-Tracking: v=1; b=H4sIAPkjnmYC/4WNQQ6DIBREr2L+ujSAKNZV79G4AET9SQPkY00b4 91LvUCXbybzZofsCX2GvtqB/IYZYyggLxW4xYTZMxwLg+RScS06lp2WHWfJYanC6oleac2sHWv VNny8WSuhjBP5Cd+n+DEUXjCvkT7nzyZ+6V/lJphgkittJlPbxur7E4OheI00w3AcxxfbzXTHv QAAAA== To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Rayyan Ansari X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2856; i=rayyan.ansari@linaro.org; h=from:subject:message-id; bh=KQQc/V15kavtbOUQ/Osta3RjY3Ph1hkx8TGV7hYTR/M=; b=owGbwMvMwCXmtuJiX/SRuS2Mp9WSGNLmqSjovdnZZn1q57FDmVsMzZIfBHbP8z+858uij9ZHb mRP0v8yo6OUhUGMi0FWTJHlcNOXNa+3Owld2V51CmYOKxPIEAYuTgGYyLPPjAzN3260xPi0339m ycVSMFvrVRK/5n35Ra+qNqkxJSc+LlFiZJjKpTxnxq3wZcuCXEp4TS/oOk/wqb7EdyRy8WZBMdd lszkA X-Developer-Key: i=rayyan.ansari@linaro.org; a=openpgp; fpr=C382F4ACEBB74212D4B77ACA46A8D18E5BC49D84 In the previous commit to this binding, commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema"), the binding was changed to specify one interrupt, as the device tree at that moment in time did not describe the hardware fully. The device tree for sc7280 now specifies eight interrupts, due to commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI interrupts"). As a result, change the bindings to reflect this. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Rayyan Ansari --- Changes in v2: - Fixed formatting of commit message, added r-b tags - Link to v1: https://lore.kernel.org/r/20240718-sc7280-pcie-interrupts-v1-1-2047afa3b5b7@linaro.org --- .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 24 ++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) --- base-commit: 73399b58e5e5a1b28a04baf42e321cfcfc663c2f change-id: 20240718-sc7280-pcie-interrupts-6d34650d9bb2 Best regards, diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 634da24ec3ed..5cf1f9165301 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -53,11 +53,19 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - maxItems: 1 + minItems: 8 + maxItems: 8 interrupt-names: items: - - const: msi + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 resets: maxItems: 1 @@ -137,8 +145,16 @@ examples: dma-coherent; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,