From patchwork Mon Jul 22 16:54:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 071A2C3DA5D for ; Mon, 22 Jul 2024 16:54:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C57810E1D4; Mon, 22 Jul 2024 16:54:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cd0HxgCv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9E27D10E1D4; Mon, 22 Jul 2024 16:54:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667290; x=1753203290; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pjC5XqfSrP0ua0dYCv6CchNoM+i61yBKq9Q6GsROJdE=; b=cd0HxgCvwhU5xHTMd9KyvEJ4lMCw9t986BNlvYzdCHtekHfWMyIf+JFU O/XiMtMTueTdL0etopJAczXKZwlv87m5iuucL/sy6JRF/AuVMTHCEENqG ACIqtKU5fwwZbSjU4TlNAboXutxgrOVTx1Bd2P3Q0h4SdqrB4optI5cPC rlt+mUBYip4QNHk2Oy/E6bM1/CbEe06V8x96s4JBJJuM5nzRSqicxPEMR cFggZNJ2lOrcO7JyT80v4nVYgnx9fDvmETiWnDYmp5CAIgtJ/aRkc5VuE TK/kFNP1RRDAhEIwW14+TgCvuvAPNmblDSos0gbE8y2LIEGh2jMTepVDp Q==; X-CSE-ConnectionGUID: UhndN4iHSzSl+/tvSRyY9A== X-CSE-MsgGUID: v9ecT+icSt2eXpMszDwc1g== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117292" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117292" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:50 -0700 X-CSE-ConnectionGUID: 8xoCcciGTP26MCw5ZrrBLA== X-CSE-MsgGUID: LoXP60nnRSKAA6NAqK8Qvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056189" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:49 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org Subject: [PATCH 01/14] drm/dp_mst: Factor out function to queue a topology probe work Date: Mon, 22 Jul 2024 19:54:50 +0300 Message-ID: <20240722165503.2084999-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a function to queue a work for probing the topology, also used by the next patch. Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak Reviewed-by: Lyude Paul --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index fc2ceae61db2d..b185b3b38bd2f 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -2692,6 +2692,11 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work) drm_kms_helper_hotplug_event(dev); } +static void drm_dp_mst_queue_probe_work(struct drm_dp_mst_topology_mgr *mgr) +{ + queue_work(system_long_wq, &mgr->work); +} + static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, u8 *guid) { @@ -3685,7 +3690,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms /* Write reset payload */ drm_dp_dpcd_write_payload(mgr, 0, 0, 0x3f); - queue_work(system_long_wq, &mgr->work); + drm_dp_mst_queue_probe_work(mgr); ret = 0; } else { @@ -3809,7 +3814,7 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, * state of our in-memory topology back into sync with reality. So, * restart the probing process as if we're probing a new hub */ - queue_work(system_long_wq, &mgr->work); + drm_dp_mst_queue_probe_work(mgr); mutex_unlock(&mgr->lock); if (sync) { From patchwork Mon Jul 22 16:54:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7D87C3DA63 for ; Mon, 22 Jul 2024 16:54:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2769610E1DE; Mon, 22 Jul 2024 16:54:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kRcqS4CP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2332310E1D4; Mon, 22 Jul 2024 16:54:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667292; x=1753203292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AodyJN6SRyMgd7ViejlGYKmejthVAj4PEvqXXIlxLLE=; b=kRcqS4CP7r8F386INc1A1tjEzXpFvQ8aTZh4TUnwJzjs7RkXKoUhbG6P M252QH1BXYb/gttKZ6+ZzTeS7sb8fCRVUbmTP9SK7q8Cs0Ff1peCbJGtY c1OC+BGPDBjzZZVX1FXh7s0JQesvcqWt3bmuiXagjsYLH9dkZjZI+kcH+ 3tkfh9M7Vi9J//OahW4ZpZAWughAZ4M5KEfNst/6Jl7hQZpa2PFfjmMx4 6qGgvg+8B9wtMeWImsXghzGoyOIBm17v+lYkkffcKzpvJ33xo7faWHfFe iSTUFRV1zioZMowVUU1QI3in8jjan7uJUx4xZatUftcahhnEI7BONBsBm w==; X-CSE-ConnectionGUID: 2Da/0DpRTMqeSa7R9X6iHQ== X-CSE-MsgGUID: 4uZ97U9vQm6WY3/dXSKCcw== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117297" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117297" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:51 -0700 X-CSE-ConnectionGUID: EYZGFMl7T7+SEWy7z/m0Aw== X-CSE-MsgGUID: shUHNWt3RUmgG1PEs6NBtQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056196" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:50 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org Subject: [PATCH 02/14] drm/dp_mst: Add a helper to queue a topology probe Date: Mon, 22 Jul 2024 19:54:51 +0300 Message-ID: <20240722165503.2084999-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A follow up i915 patch will need to reprobe the MST topology after the initial probing, add a helper for this. Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 27 +++++++++++++++++++ include/drm/display/drm_dp_mst_helper.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index b185b3b38bd2f..70e4bfc3532e0 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -3728,6 +3728,33 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb); } +/** + * drm_dp_mst_topology_queue_probe - Queue a topology probe + * @mgr: manager to probe + * + * Queue a work to probe the MST topology. Driver's should call this only to + * sync the topology's HW->SW state after the MST link's parameters have + * changed in a way the state could've become out-of-sync. This is the case + * for instance when the link rate between the source and first downstream + * branch device has switched between UHBR and non-UHBR rates. Except of those + * cases - for instance when a sink gets plugged/unplugged to a port - the SW + * state will get updated automatically via MST UP message notifications. + */ +void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) +{ + mutex_lock(&mgr->lock); + + if (drm_WARN_ON(mgr->dev, !mgr->mst_state || !mgr->mst_primary)) + goto out_unlock; + + drm_dp_mst_topology_mgr_invalidate_mstb(mgr->mst_primary); + drm_dp_mst_queue_probe_work(mgr); + +out_unlock: + mutex_unlock(&mgr->lock); +} +EXPORT_SYMBOL(drm_dp_mst_topology_queue_probe); + /** * drm_dp_mst_topology_mgr_suspend() - suspend the MST manager * @mgr: manager to suspend diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index cfe096389d94f..02b037d3a93f7 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -885,6 +885,8 @@ int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr); void drm_dp_mst_dump_topology(struct seq_file *m, struct drm_dp_mst_topology_mgr *mgr); +void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); + void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr); int __must_check drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, From patchwork Mon Jul 22 16:54:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A21EC3DA63 for ; Mon, 22 Jul 2024 16:55:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA9A510E1EB; Mon, 22 Jul 2024 16:54:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KAXg0vds"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8FA1910E1DB; Mon, 22 Jul 2024 16:54:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667293; x=1753203293; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OV88/kwK4YvT9DlYHmoldMp9mSj0Nsri8FX4J1bLmR4=; b=KAXg0vdsW47FXQVDXazRFNErnIyFN7AP7IxJh/dugtYRytTFQeytcpk8 OAQYQkCD+d7R+0Fv3RpwWtw1CROYkw+a9AFUyjDScVFK6NEyp0MAu6h8C aggSR/pen+eEE4eTav8I4E9nQ7LgSxhR10GOsCsHKq9cn4c7c24s9Z8Is FIx1vfF7UkY4eDOqSKavxHmjBNDpXO5GgTuZlKtgpEpYow4heACZaiMcf VXAVtwITt8CUKL54c68DWlm5O98kGrzuenIrHZqKgg2RSO4zvPqGkVc72 JAmAnJQVHs4w3OApNXbAiu7/JSTHa6sezd0bSFCuxru4QaBovXCIvE/Iy Q==; X-CSE-ConnectionGUID: R6xwfpOGR1yTTzyUVYFqGQ== X-CSE-MsgGUID: r9gR8KOdTN65CpJlwfA1cw== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117303" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117303" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:53 -0700 X-CSE-ConnectionGUID: ZR4DAZ4wSKGD409R4uptZg== X-CSE-MsgGUID: vdheB8qHRrGa85wyeJn3CQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056203" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:52 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org Subject: [PATCH 03/14] drm/dp_mst: Simplify the condition when to enumerate path resources Date: Mon, 22 Jul 2024 19:54:52 +0300 Message-ID: <20240722165503.2084999-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In the if (old_ddps != port->ddps || !created) if (port->ddps && !port->input) ret = drm_dp_send_enum_path_resources(); sequence the first if's condition is true if the port exists already (!created) or the port was created anew (hence old_ddps==0) and it was in the plugged state (port->ddps==1). The second if's condition is true for output ports in the plugged state. So the function is called for an output port in the plugged state, regardless if it already existed or not and regardless of the old plugged state. In all other cases port->full_pbn can be zeroed as the port is either an input for which full_pbn is never set, or an output in the unplugged state for which full_pbn was already zeroed previously or the port was just created (with port->full_pbn==0). Simplify the condition, making it clear that the path resources are always enumerated for an output port in the plugged state. Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 70e4bfc3532e0..bcc5bbed9bd04 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -2339,7 +2339,7 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, { struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; struct drm_dp_mst_port *port; - int old_ddps = 0, ret; + int ret; u8 new_pdt = DP_PEER_DEVICE_NONE; bool new_mcs = 0; bool created = false, send_link_addr = false, changed = false; @@ -2372,7 +2372,6 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, */ drm_modeset_lock(&mgr->base.lock, NULL); - old_ddps = port->ddps; changed = port->ddps != port_msg->ddps || (port->ddps && (port->ldps != port_msg->legacy_device_plug_status || @@ -2407,15 +2406,13 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, * Reprobe PBN caps on both hotplug, and when re-probing the link * for our parent mstb */ - if (old_ddps != port->ddps || !created) { - if (port->ddps && !port->input) { - ret = drm_dp_send_enum_path_resources(mgr, mstb, - port); - if (ret == 1) - changed = true; - } else { - port->full_pbn = 0; - } + if (port->ddps && !port->input) { + ret = drm_dp_send_enum_path_resources(mgr, mstb, + port); + if (ret == 1) + changed = true; + } else { + port->full_pbn = 0; } ret = drm_dp_port_set_pdt(port, new_pdt, new_mcs); From patchwork Mon Jul 22 16:54:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C94CC3DA59 for ; Mon, 22 Jul 2024 16:54:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9241510E1E0; Mon, 22 Jul 2024 16:54:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="a1HdLU7b"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id AED1510E1DB for ; Mon, 22 Jul 2024 16:54:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667294; x=1753203294; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=JPp8PTP2yChhejhTJdUg2j0WpQ/6Icg/mLo6vixhSBs=; b=a1HdLU7bniCB0Y8QYaLxs4mX3DL9ODy7DBsWgokuEtoqfc22/2s0cav1 Mz+5UdJTffmNZaBeE5SuqkhoUuGj5lkvtXRfbX1rNWK37/TkgzCCLrvoW dKtGFChChPKzgwFhHXB7iCZ8uigEBce4JNSFEvRrneATtMs3a6BTjiEG8 4kzpUjqnTE2khDbfO3cu8rklMoHrEjKGilmwoHDnOCfk3xJB0bp0vJrwj I2fbjpo5Jbj2l7qszJT1ca3UH8wTxTa3X22uihN5Wd+l1HAdZTMWiVcuK Ua7i05q2YhM3NNrFOdufhFcLZ8USPzUiE0l4CnfF4hY6cBXxMcbZGjf2R Q==; X-CSE-ConnectionGUID: SVwNIyNaQe2RvhxU+hllHw== X-CSE-MsgGUID: jHIaxT+RSQKFLWGzp6QWew== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117306" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117306" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:54 -0700 X-CSE-ConnectionGUID: aAAa8dddQPC7NxrhgaU2Dw== X-CSE-MsgGUID: pV1TzoCcQj+VSm+IUeQEUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056209" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:53 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 04/14] drm/i915/ddi: For an active output call the DP encoder sync_state() only for DP Date: Mon, 22 Jul 2024 19:54:53 +0300 Message-ID: <20240722165503.2084999-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If the DDI encoder output is enabled in HDMI mode there is no point in calling intel_dp_sync_state(), as in that case the DPCD initialization will fail - as expected - with AUX timeouts. Prevent calling the hook in this case. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a07aca96e5517..11ee4406dce8f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4172,7 +4172,8 @@ static void intel_ddi_sync_state(struct intel_encoder *encoder, intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), crtc_state); - if (intel_encoder_is_dp(encoder)) + if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || + (!crtc_state && intel_encoder_is_dp(encoder))) intel_dp_sync_state(encoder, crtc_state); } From patchwork Mon Jul 22 16:54:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C4AFC3DA5D for ; Mon, 22 Jul 2024 16:55:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C0CFB10E1ED; Mon, 22 Jul 2024 16:55:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TP7RMKn9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31CFF10E1DB for ; Mon, 22 Jul 2024 16:54:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667296; x=1753203296; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ibRd6IcLzu6+IZ2fOcdgkyFtQsOTwGMz2s92I5PzfRg=; b=TP7RMKn9a2D1h/yqAsNiGzRGMbf04qYvgZ+DxE6dqegutfKvuRg1bUl9 nyWiShyx67y5pKlOKLBW0mDblUwJPvCMYWNVbYle0+rwMrJUjDklIhxKn OFF6471DPWw6/jxqA9pUL+fKYlO6SyIp6YJi7sIi826ALlfO6Ar/ATZ+T hgXPRaq01XSqC/Uqs+NGvqIgaKq5vINKO7RztpeculKzVvN2gUDdwEiHW BrgLbevOAe0nfrII+sDx2Uel3+QRKZFBmAvs/Skw0chw4dJQmgobQpT1C h62pGK3+gw+W0QJEFUoFOUSIFlDAF/z8B0rQFUUIvIBj0W7doNRpQzSSv A==; X-CSE-ConnectionGUID: 6l97EAqcRTa1Nu53leuPTQ== X-CSE-MsgGUID: S/1jGi1PS9+6qJcoY8xQ5g== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117311" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117311" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:56 -0700 X-CSE-ConnectionGUID: 1s9fjM71TbOM7lt4bT66vA== X-CSE-MsgGUID: j8LvtPB/R1Sukajp6RV07g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056214" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:55 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 05/14] drm/i915/dp: Initialize the link parameters during HW readout Date: Mon, 22 Jul 2024 19:54:54 +0300 Message-ID: <20240722165503.2084999-6-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Initialize the DP link parameters during HW readout. These need to be up-to-date at least for the MST topology probing, which depends on the link rate and lane count programmed in DPCD. A follow-up patch will program the DPCD values to reflect the maximum link parameters before the first MST topology probing, but should do so only if the link is disabled (link_trained==false). Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1e43e32e05199..421e970b3c180 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3352,8 +3352,11 @@ void intel_dp_sync_state(struct intel_encoder *encoder, intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); - if (crtc_state) + if (crtc_state) { intel_dp_reset_link_params(intel_dp); + intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); + intel_dp->link_trained = true; + } } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, From patchwork Mon Jul 22 16:54:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 328AFC3DA7E for ; Mon, 22 Jul 2024 16:55:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CAF510E206; Mon, 22 Jul 2024 16:55:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Tl/im3ME"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6010810E1EB for ; Mon, 22 Jul 2024 16:54:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667297; x=1753203297; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WDhRqAA1BLJ+qqOGHe/pej/QgVbmRx+DcrgvjNzglvo=; b=Tl/im3MEYF667N0lCBSGQtjvLgK8EP4UbZ0VWy3cuViwYrMdfW4BjBHO lVoaTkOXA2ReLPCxr+yJ1JPtyCpMVFESu3fxExJqqtbSCi82MqV2LxzqM X6NY40MdxEBBCqpwHEG6nu4PlLOpDzqdA9NoWuhbMta7DGFFPS+8+CAIF ND1Ouee+jaM0btb6Ew7EA0OSkkXfCofO2XqmMUwrKBLR358k9oQND6h6V 0RBlyU3ALks5PN3MhL5RQ02rJx7DjEeXsHqs+dRdqgzKFW0Z/5mTpNky8 FpSvyh9AIfR/hn/neiMLvF6UfMX/Kf5Iti8kGsFhGV0YgtgtAEoVJKDTm Q==; X-CSE-ConnectionGUID: 2IJCQYP6TIGNmp/VBQfQ6g== X-CSE-MsgGUID: lK4oabm3SdyZfIzotsDYQQ== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117312" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117312" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:57 -0700 X-CSE-ConnectionGUID: /zwjYVaZSW6OFf1uY9iI3Q== X-CSE-MsgGUID: gXXObsVuQEeTmHaRByvTOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056222" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:56 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry uevent for a commit Date: Mon, 22 Jul 2024 19:54:55 +0300 Message-ID: <20240722165503.2084999-7-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There are multiple failure cases a modeset-retry uevent can be sent for a link (TBT tunnel BW allocation failure, unrecoverable link training failure), a follow-up patch adding the handling for a new case where the DP MST payload allocation fails. The uevent is the same in all cases, sent to all the connectors on the link, so in case of multiple failures there is no point in sending a separate uevent for each failure; prevent this, sending only a single modeset-retry uevent for a commit. Signed-off-by: Imre Deak Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a9d2acdc51a4a..3501125c55158 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1754,6 +1754,7 @@ struct intel_dp { u8 lane_count; u8 sink_count; bool link_trained; + bool needs_modeset_retry; bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 421e970b3c180..0882dddd97206 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2876,6 +2876,11 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); int i; + if (intel_dp->needs_modeset_retry) + return; + + intel_dp->needs_modeset_retry = true; + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); @@ -3009,6 +3014,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, { memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp->link_trained = false; + intel_dp->needs_modeset_retry = false; intel_dp->link_rate = link_rate; intel_dp->lane_count = lane_count; } From patchwork Mon Jul 22 16:54:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E683C3DA59 for ; Mon, 22 Jul 2024 16:55:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 508E410E1F2; Mon, 22 Jul 2024 16:55:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Y0CqHwgf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65A5410E1ED for ; Mon, 22 Jul 2024 16:54:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667298; x=1753203298; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WBPwzQOzOG6FOkRFxFUwKOcrkAyYgUMAhUW84hqm8eM=; b=Y0CqHwgfETRFz3HNV6gS4El2qOB8w4PuDQVtIo2dZ4XbERhoPjDe6Yvv 87VwdMfXyPTv0eSSFq5j4UDfX2rtq+T8YYXeU+gGxLvhjR9bWoPMZQM7q wIGBPbuuJAeTd60yNDJ6Hl8HAXEXot1RBt3SlO3zLm+Up59PnO2jo3C7t YDA7NTSzPnHKyJlRhYZBeshYD0IxagtD6dYNjZptfU40mdl3deCV4l2hR r5yAU6VMYxSsngg75Dag7elPbX47LfLDi2XtEVhtLGPPrxD+EJDxim2Js N8NKjITmGmB0rKq+IetRMhrZO6nicnp8ZczWSCiZW4qzktlR/Pmp+ZzHn w==; X-CSE-ConnectionGUID: sm01fXNUQRGkQc35K9DxSA== X-CSE-MsgGUID: mRa7Ix15Qb20aXjs3FdZXw== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117314" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117314" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:58 -0700 X-CSE-ConnectionGUID: XW7BrC8CS+S9e4Fv5MLIRA== X-CSE-MsgGUID: keO+6eJ0R06diNL1KqmUAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056230" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:57 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce the link parameters Date: Mon, 22 Jul 2024 19:54:56 +0300 Message-ID: <20240722165503.2084999-8-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A follow-up patch will add an alternative way to reduce the link parameters in BW order on MST links, prepare for that here. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- .../drm/i915/display/intel_dp_link_training.c | 39 +++++++++++++++---- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 58dea87a9fa28..57536ae200b77 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1193,6 +1193,36 @@ static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) return current_lane_count >> 1; } +static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int *new_link_rate, int *new_lane_count) +{ + int link_rate; + int lane_count; + + lane_count = crtc_state->lane_count; + link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); + if (link_rate < 0) { + lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); + link_rate = intel_dp_max_common_rate(intel_dp); + } + + if (lane_count < 0) + return false; + + *new_link_rate = link_rate; + *new_lane_count = lane_count; + + return true; +} + +static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, + int *new_link_rate, int *new_lane_count) +{ + return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, + new_link_rate, new_lane_count); +} + static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -1206,14 +1236,7 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } - new_lane_count = crtc_state->lane_count; - new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); - if (new_link_rate < 0) { - new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); - new_link_rate = intel_dp_max_common_rate(intel_dp); - } - - if (new_lane_count < 0) + if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) return -1; if (intel_dp_is_edp(intel_dp) && From patchwork Mon Jul 22 16:54:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC026C3DA59 for ; Mon, 22 Jul 2024 16:55:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C154110E1DB; Mon, 22 Jul 2024 16:55:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G7Bs9tej"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E30E10E1F9 for ; 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22 Jul 2024 09:54:59 -0700 X-CSE-ConnectionGUID: 72RlV1XdSjy1UimYU3rAAA== X-CSE-MsgGUID: eINodMYWSr6QrXXMcF6weQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056234" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:58 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 08/14] drm/i915/dp: Add helpers to set link training mode, BW parameters Date: Mon, 22 Jul 2024 19:54:57 +0300 Message-ID: <20240722165503.2084999-9-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add helpers to set the link mode and BW parameters. These are required by a follow-up patch setting the parameters for a disabled link. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- .../drm/i915/display/intel_dp_link_training.c | 34 +++++++++++++------ .../drm/i915/display/intel_dp_link_training.h | 6 ++++ 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 57536ae200b77..214c8858b8a94 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -21,6 +21,8 @@ * IN THE SOFTWARE. */ +#include + #include "i915_drv.h" #include "intel_display_types.h" #include "intel_dp.h" @@ -703,26 +705,28 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, return true; } -static void -intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) { u8 link_config[2]; - link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; - link_config[1] = intel_dp_is_uhbr(crtc_state) ? + link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; + link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); } -static void -intel_dp_update_link_bw_set(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state, - u8 link_bw, u8 rate_select) +static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { - u8 lane_count = crtc_state->lane_count; + intel_dp_link_training_set_mode(intel_dp, + crtc_state->port_clock, crtc_state->vrr.flipline); +} - if (crtc_state->enhanced_framing) +void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, + int link_bw, int rate_select, int lane_count, + bool enhanced_framing) +{ + if (enhanced_framing) lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; if (link_bw) { @@ -746,6 +750,14 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp, } } +static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + u8 link_bw, u8 rate_select) +{ + intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, + crtc_state->enhanced_framing); +} + /* * Prepare link training by configuring the link parameters. On DDI platforms * also enable the port here. diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 42e7fc6cb171a..2066b91467622 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -16,6 +16,12 @@ struct intel_dp; int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]); int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp); +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, + int link_rate, bool is_vrr); +void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, + int link_bw, int rate_select, int lane_count, + bool enhanced_framing); + void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, From patchwork Mon Jul 22 16:54:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0C88C3DA59 for ; Mon, 22 Jul 2024 16:55:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCF9610E209; Mon, 22 Jul 2024 16:55:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O4onqYIR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8855B10E204 for ; Mon, 22 Jul 2024 16:55:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667300; x=1753203300; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=KMzCVimy50sKj3PEFpY2hO4GeA65WR1GNHUD4MQm64s=; b=O4onqYIRHcxxCJV7BdRFXY23MQ7kj0FaAqDOpEVpNfWh3c8FbHn0fu0q 2eFltmjleYXROzZDItJQKSVvz3CCWtbEhLZpN+m+u9pLy87mJ/A9mk9FT TxSjz41Apug87RHVaa8f2cu2Mqg2VxycuIolwp/KDPJpqwHWJKJ25srhM LewvUzc+JM1sdjpMtxMHccrDflqPg9htjUFdWIL/5r0vhj1SrLge2AI0D CrPxE+/bcM6dlHK/EGYOArr2ZfTcySpYEsYruILkj12hLnuXCja9fPzp8 6ZzAIbP/3sIdsUsGsFnObWwBiKkyqBu6oFQ0walmfZ6gNAC9CrRV3q5Aj A==; X-CSE-ConnectionGUID: 0O3cF513Ru20bkaEgQNBig== X-CSE-MsgGUID: 4T79AXjaT7eoptyRxsDaVA== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117316" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117316" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:00 -0700 X-CSE-ConnectionGUID: qGfXe8sKTxWuIZ2MSl2naA== X-CSE-MsgGUID: AjvoGccvSYSFelLmqrxvvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056247" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:54:59 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 09/14] drm/i915/dp_mst: Reduce the link parameters in BW order after LT failures Date: Mon, 22 Jul 2024 19:54:58 +0300 Message-ID: <20240722165503.2084999-10-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On MST links - at least for some MST branch devices - the list of modes returned to users on an enabled link depends on the current link rate/lane count parameters (besides the DPRX link capabilities, any MST branch BW limit and the maximum link parameters reduced after LT failures). In particular the MST branch BW limit may depend on the link rate/lane count parameters programmed to DPCD. After an LT failure and limiting the maximum link parameters accordingly, users should see a mode list reflecting these new limits. However with the current fallback order this isn't ensured, as the new limit could allow for modes requiring a higher link BW, but these modes will be filtered out due to the enabled link's lower link BW. Ensure that the mode list changes in a consistent way after a link training failure and reducing the link parameters by changing the fallback order on MST links to happen in BW order. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- .../drm/i915/display/intel_display_types.h | 12 ++ drivers/gpu/drm/i915/display/intel_dp.c | 111 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 43 ++++++- 4 files changed, 166 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3501125c55158..51e2151315977 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1778,6 +1778,18 @@ struct intel_dp { int common_rates[DP_MAX_SUPPORTED_RATES]; struct { /* TODO: move the rest of link specific fields to here */ + /* common rate,lane_count configs in bw order */ + int num_configs; +#define INTEL_DP_MAX_LANE_COUNT 4 +#define INTEL_DP_MAX_SUPPORTED_LANE_COUNTS (ilog2(INTEL_DP_MAX_LANE_COUNT) + 1) +#define INTEL_DP_LANE_COUNT_EXP_BITS order_base_2(INTEL_DP_MAX_SUPPORTED_LANE_COUNTS) +#define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS) +#define INTEL_DP_MAX_LINK_CONFIGS (DP_MAX_SUPPORTED_RATES * \ + INTEL_DP_MAX_SUPPORTED_LANE_COUNTS) + struct intel_dp_link_config { + u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS; + u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS; + } configs[INTEL_DP_MAX_LINK_CONFIGS]; /* Max lane count for the current link */ int max_lane_count; /* Max rate for the current link */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0882dddd97206..d3529c5836393 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -634,6 +635,114 @@ int intel_dp_rate_index(const int *rates, int len, int rate) return -1; } +static int intel_dp_link_config_rate(struct intel_dp *intel_dp, + const struct intel_dp_link_config *lc) +{ + return intel_dp_common_rate(intel_dp, lc->link_rate_idx); +} + +static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) +{ + return 1 << lc->lane_count_exp; +} + +static int intel_dp_link_config_bw(struct intel_dp *intel_dp, + const struct intel_dp_link_config *lc) +{ + return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), + intel_dp_link_config_lane_count(lc)); +} + +static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) +{ + struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ + const struct intel_dp_link_config *lc_a = a; + const struct intel_dp_link_config *lc_b = b; + int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); + int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); + + if (bw_a != bw_b) + return bw_a - bw_b; + + return intel_dp_link_config_rate(intel_dp, lc_a) - + intel_dp_link_config_rate(intel_dp, lc_b); +} + +static void link_config_swap(void *a, void *b, int size, const void * __always_unused p) +{ + struct intel_dp_link_config *lc_a = a; + struct intel_dp_link_config *lc_b = b; + + swap(*lc_a, *lc_b); +} + +static void intel_dp_link_config_init(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_dp_link_config *lc; + int num_common_lane_counts; + int i; + int j; + + if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) + return; + + num_common_lane_counts = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; + + if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_counts > + ARRAY_SIZE(intel_dp->link.configs))) + return; + + intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_counts; + + lc = &intel_dp->link.configs[0]; + for (i = 0; i < intel_dp->num_common_rates; i++) { + for (j = 0; j < num_common_lane_counts; j++) { + lc->lane_count_exp = j; + lc->link_rate_idx = i; + + lc++; + } + } + + sort_r(intel_dp->link.configs, intel_dp->link.num_configs, + sizeof(intel_dp->link.configs[0]), + link_config_cmp_by_bw, link_config_swap, + intel_dp); +} + +void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + const struct intel_dp_link_config *lc; + + if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs)) + idx = 0; + + lc = &intel_dp->link.configs[idx]; + + *link_rate = intel_dp_link_config_rate(intel_dp, lc); + *lane_count = intel_dp_link_config_lane_count(lc); +} + +int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) +{ + int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, + link_rate); + int lane_count_exp = ilog2(lane_count); + int i; + + for (i = 0; i < intel_dp->link.num_configs; i++) { + const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; + + if (lc->lane_count_exp == lane_count_exp && + lc->link_rate_idx == link_rate_idx) + return i; + } + + return -1; +} + static void intel_dp_set_common_rates(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -652,6 +761,8 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp) intel_dp->common_rates[0] = 162000; intel_dp->num_common_rates = 1; } + + intel_dp_link_config_init(intel_dp); } static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 9be539edf817b..1b9aaddd8c35c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -107,6 +107,8 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp); int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); int intel_dp_common_rate(struct intel_dp *intel_dp, int index); int intel_dp_rate_index(const int *rates, int len, int rate); +int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count); +void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); void intel_dp_reset_link_params(struct intel_dp *intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 214c8858b8a94..0c8e0d6437b5b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1170,6 +1170,41 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, return true; } +static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int *new_link_rate, int *new_lane_count) +{ + int link_rate; + int lane_count; + int i; + + i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); + for (i--; i >= 0; i--) { + intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); + + if ((intel_dp->link.force_rate && + intel_dp->link.force_rate != link_rate) || + (intel_dp->link.force_lane_count && + intel_dp->link.force_lane_count != lane_count)) + continue; + + /* TODO: Make switching from UHBR to non-UHBR rates work. */ + if (drm_dp_is_uhbr_rate(crtc_state->port_clock) != + drm_dp_is_uhbr_rate(link_rate)) + continue; + + break; + } + + if (i < 0) + return false; + + *new_link_rate = link_rate; + *new_lane_count = lane_count; + + return true; +} + static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) { int rate_index; @@ -1231,8 +1266,12 @@ static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int *new_link_rate, int *new_lane_count) { - return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, - new_link_rate, new_lane_count); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) + return reduce_link_params_in_bw_order(intel_dp, crtc_state, + new_link_rate, new_lane_count); + else + return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, + new_link_rate, new_lane_count); } static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, From patchwork Mon Jul 22 16:54:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E362C3DA7F for ; Mon, 22 Jul 2024 16:55:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4337A10E1F9; Mon, 22 Jul 2024 16:55:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="II36GZH1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9765310E1F6 for ; Mon, 22 Jul 2024 16:55:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667301; x=1753203301; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ImSkBiCSvLyiuE4j0ITbJNQsWMLAcatqYLV7fL+hwSE=; b=II36GZH1VRR+AF4wvYUQx5ujR7WfHBrAifCLv5yeM5rqDAyctNwFqDmn bJrI2DkxUrIh22SX1lBnMHkfmBxIKuE+JiDPFyOcVQJ6nMLlOa5szfTl3 EgfWy/qpU/hRWTocwUhdSC7tCi39JEi3fKk8fH6N2WJ0QYf5pZY6poUTl /PtrWmine8/HEkkF94F7KcrA2WCPXAWPcMfhuX1zK5xrOYfeG7U9nAj8X Q2Y+6UTraxCrtPcF+NClAjYnGtSCSEqG/C6Ng0w0hkK1byV/PaVeVy0vU TwfugQFhngRYJnSxJ1aubsAjXeDlWiX25s8PkuL4qjIjWXwzxJCuAxKA8 A==; X-CSE-ConnectionGUID: 6PiGFlkVQH+Pgl8ysC0vAA== X-CSE-MsgGUID: 8+JzNp2cRcWMfJFmAleoCQ== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117317" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117317" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:01 -0700 X-CSE-ConnectionGUID: fzKagjIeSSuBtDQfRscX2w== X-CSE-MsgGUID: aSM1eoBRRyK+w92WXFrfXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056248" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:00 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/14] drm/i915/dp_mst: Configure MST after the link parameters are reset Date: Mon, 22 Jul 2024 19:54:59 +0300 Message-ID: <20240722165503.2084999-11-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The MST topology probing depends on the maximum link parameters - programmed to DPCD if required by a follow-up patch - so make sure these parameters are up-to-date before configuring and probing the MST topology. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d3529c5836393..1c6d1db1d2690 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6025,13 +6025,13 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_detect_sdp_caps(intel_dp); - intel_dp_mst_configure(intel_dp); - if (intel_dp->reset_link_params) { intel_dp_reset_link_params(intel_dp); intel_dp->reset_link_params = false; } + intel_dp_mst_configure(intel_dp); + intel_dp_print_rates(intel_dp); if (intel_dp->is_mst) { From patchwork Mon Jul 22 16:55:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C281C3DA5D for ; Mon, 22 Jul 2024 16:55:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3CACB10E204; Mon, 22 Jul 2024 16:55:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AihNMC+1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id D18CC10E1F7 for ; Mon, 22 Jul 2024 16:55:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667302; x=1753203302; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=pM8xlaGElT6CoZ5y8PbDxo021uRP644NZGDCgzjE3o8=; b=AihNMC+1tOwaPsSuAj7+8Di49s6H4CVzxxrwHUr5BUbPu1WIopWKHwDT OkX/MWAV7gaQmdl+Re0HU8oKN5V6NYigTTYZ2K605x7+nvdllyF/dWZjO nhBZyaWKIe6M+zstTZhWQQFH34XzHNhq9ON+lYvYs6zw/kmLXDtQDKewC kfjgHPSnuXLK9ExojZuNJ/iqJ/RPw8/dYg+bQ9js+YBBTiCXyyJZkLc7m lkUHCI8uBmrSSm0J5sxXC6Xp0117mALKO29usNFgHZv+ZkmC9qC4GmY20 KdCtNL9LHeqycIlDelvfeHA47ye4JdzQfQRwluSV1KHZ+2R55a6UHentx A==; X-CSE-ConnectionGUID: MEz1+qJ3SAueK1JlEpnkPQ== X-CSE-MsgGUID: Ut2IN0OmR5eoCzuQn96HPw== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117319" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117319" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:02 -0700 X-CSE-ConnectionGUID: Z4EKBMoERdGpur9bhn8g2w== X-CSE-MsgGUID: vyQZFh7OT2KGPmL1Eb1Btw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056270" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:01 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/14] drm/i915/dp_mst: Queue modeset-retry after a failed payload BW allocation Date: Mon, 22 Jul 2024 19:55:00 +0300 Message-ID: <20240722165503.2084999-12-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If the MST payload allocation failed, enabling the output also failed most probably, so send a uevent accordinly requesting the user to retry the modeset. While at it remove the driver specific debug message, there is already one printed by drm_dp_add_payload_part1(). Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 27ce5c3f5951e..57f29906fa28f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1158,8 +1158,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, drm_atomic_get_mst_payload_state(mst_state, connector->port)); if (ret < 0) - drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n", - connector->base.name, ret); + intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config); /* * Before Gen 12 this is not done as part of @@ -1223,6 +1222,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, enum transcoder trans = pipe_config->cpu_transcoder; bool first_mst_stream = intel_dp->active_mst_links == 1; struct intel_crtc *pipe_crtc; + int ret; drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); @@ -1254,8 +1254,11 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, if (first_mst_stream) intel_ddi_wait_for_fec_status(encoder, pipe_config, true); - drm_dp_add_payload_part2(&intel_dp->mst_mgr, - drm_atomic_get_mst_payload_state(mst_state, connector->port)); + ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr, + drm_atomic_get_mst_payload_state(mst_state, + connector->port)); + if (ret < 0) + intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config); if (DISPLAY_VER(dev_priv) >= 12) intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans), From patchwork Mon Jul 22 16:55:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E426AC3DA59 for ; Mon, 22 Jul 2024 16:55:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6115710E173; Mon, 22 Jul 2024 16:55:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EYI9LrAN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1750110E1ED for ; Mon, 22 Jul 2024 16:55:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667304; x=1753203304; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WeTWIIMdekcp5V2ZJNs4Z5Ia8y1xBuDyQb6qZw2cTEA=; b=EYI9LrANUBi/b4I+QPAsWWD2NKl0HSS+y34+8NKtq3COFKf0/m9vm314 ajzc0JTZQxEDawctCgYKTdjbI7zg/qV3F55f8eJWONLZVNfhAcyZcU7wa kGKhEhgpfaAmC2ePuAYywOQT5GB7koh2R42FaNX1DfDrz8K8sd8xtHIT+ lI59P0gy6ff1Fhil8gUZBcgsXhnkQ2EQpg3rmT/BYrHPOxqeClXsiIRmS ZFzxnRnGgoZl+M047WWqg0ewa7K0Hg6rPPTg+RaSKYjKipSMDpSwmN5cn HRtqsJC9WmmMZdKfC+CadACsqZ1lqLXAl8XIU5ptbfsm5Cj+yY5bCF7Se g==; X-CSE-ConnectionGUID: 0NePiBQ0TTmDPeJgnXC20w== X-CSE-MsgGUID: 1VuNvDzmQIOVCiFaZgSWhg== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117322" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117322" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:03 -0700 X-CSE-ConnectionGUID: pFz95YDgQ+CxkTN6uAlZnw== X-CSE-MsgGUID: kH3EdTHnRveX4yOlT6FdCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056315" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:03 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 12/14] drm/i915/dp_mst: Reprobe the MST topology after a link parameter change Date: Mon, 22 Jul 2024 19:55:01 +0300 Message-ID: <20240722165503.2084999-13-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The MST link BW reported by branch devices via the ENUM_PATH_RESOURCES message depends on the channel coding and link rate/lane count parameters programmed to DPCD. This is the case at least for some branch devices, while for others the reported BW is independent of the link parameters. In any case the DP standard requires the branch device to adjust the returned value to both account for the different way the BW for FEC is accounted for (included in the returned value for non-UHBR and not included for UHBR rates) and to limit the returned value to the (trained) link BW between the source and first downstreaam branch device, see DP v2.0/v2.1 Figure 2-94, DP v2.1 5.9.7. Presumedly this is also the reason why the standard requires the DPCD link rate/lane count values being up-to-date before sending the ENUM_PATH_RESOURCES message, see DP v2.1 2.14.9.4. Based on the above reprobe the MST topology after the link is retrained with new link parameters to make sure that the MST link BW tracked in the MST topology state (via each topology port's full_pbn value) is up-to-date. The next patch will make sure that the MST link BW is also kept up-to-date if the link is disabled. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- .../drm/i915/display/intel_display_types.h | 8 +++++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 32 ++++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 51e2151315977..afd8329e3ed6e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1794,6 +1794,14 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + /* + * Link parameters for which the MST topology was probed. + * Tracking these ensures that the MST path resources are + * re-enumerated whenever the link is retrained with new link + * parameters, as required by the DP standard. + */ + int mst_probed_lane_count; + int mst_probed_rate; int force_lane_count; int force_rate; bool retrain_disabled; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1c6d1db1d2690..0771e4c6357ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3134,6 +3134,8 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.mst_probed_lane_count = 0; + intel_dp->link.mst_probed_rate = 0; intel_dp->link.retrain_disabled = false; intel_dp->link.seq_train_failures = 0; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 57f29906fa28f..19c8b6878b030 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1113,6 +1113,33 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, to_intel_crtc(pipe_config->uapi.crtc)); } +static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp, + int link_rate, int lane_count) +{ + return intel_dp->link.mst_probed_rate == link_rate && + intel_dp->link.mst_probed_lane_count == lane_count; +} + +static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp, + int link_rate, int lane_count) +{ + intel_dp->link.mst_probed_rate = link_rate; + intel_dp->link.mst_probed_lane_count = lane_count; +} + +static void intel_mst_reprobe_topology(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + if (intel_mst_probed_link_params_valid(intel_dp, + crtc_state->port_clock, crtc_state->lane_count)) + return; + + drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr); + + intel_mst_set_probed_link_params(intel_dp, + crtc_state->port_clock, crtc_state->lane_count); +} + static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, @@ -1149,10 +1176,13 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, intel_dp_sink_enable_decompression(state, connector, pipe_config); - if (first_mst_stream) + if (first_mst_stream) { dig_port->base.pre_enable(state, &dig_port->base, pipe_config, NULL); + intel_mst_reprobe_topology(intel_dp, pipe_config); + } + intel_dp->active_mst_links++; ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, From patchwork Mon Jul 22 16:55:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B495C3DA59 for ; Mon, 22 Jul 2024 16:55:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E79110E1F6; Mon, 22 Jul 2024 16:55:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dxWcTpmM"; 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d="scan'208";a="23117326" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:04 -0700 X-CSE-ConnectionGUID: veTw3wNBSgSw6BtCK/3P4A== X-CSE-MsgGUID: Y1sNnH6MQP2Rp3YccobsSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056323" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:04 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 13/14] drm/i915/dp_mst: Ensure link parameters are up-to-date for a disabled link Date: Mon, 22 Jul 2024 19:55:02 +0300 Message-ID: <20240722165503.2084999-14-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As explained in the previous patch, the MST link BW reported by branch devices during topology probing/path resources enumeration depends on the link parameters programmed to DPCD to be up-to-date. After a sink is plugged this is not ensured, as those DPCD values start out zeroed. The target link parameters (for a subsequent modeset) are the maximum that is supported, so make sure these maximum values are programmed before the topology probing. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 31 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp_mst.h | 1 + 3 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0771e4c6357ba..41f5d82ca75d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4262,6 +4262,9 @@ intel_dp_mst_configure(struct intel_dp *intel_dp) intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; + if (intel_dp->is_mst) + intel_dp_mst_prepare_probe(intel_dp); + drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); /* Avoid stale info on the next detect cycle. */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 19c8b6878b030..faee7af0a8a48 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -43,6 +43,7 @@ #include "intel_dp_hdcp.h" #include "intel_dp_mst.h" #include "intel_dp_tunnel.h" +#include "intel_dp_link_training.h" #include "intel_dpio_phy.h" #include "intel_hdcp.h" #include "intel_hotplug.h" @@ -2031,3 +2032,33 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, return false; } + +/** + * intel_dp_mst_prepare_probe - Prepare an MST link for topology probing + * @intel_dp: DP port object + * + * Prepare an MST link for topology probing, programming the target + * link parameters to DPCD. This step is a requirement of the enumaration + * of path resources during probing. + */ +void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp) +{ + int link_rate = intel_dp_max_link_rate(intel_dp); + int lane_count = intel_dp_max_lane_count(intel_dp); + u8 rate_select; + u8 link_bw; + + if (intel_dp->link_trained) + return; + + if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count)) + return; + + intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select); + + intel_dp_link_training_set_mode(intel_dp, link_rate, false); + intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count, + drm_dp_enhanced_frame_cap(intel_dp->dpcd)); + + intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count); +} diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h index 8ca1d599091c6..fba76454fa67f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h @@ -27,5 +27,6 @@ int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state, struct intel_link_bw_limits *limits); bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, struct intel_crtc *crtc); +void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp); #endif /* __INTEL_DP_MST_H__ */ From patchwork Mon Jul 22 16:55:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13738961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 592E9C3DA63 for ; Mon, 22 Jul 2024 16:55:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B41BC10E1F7; Mon, 22 Jul 2024 16:55:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gWr4wsD5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0BA4710E1FD for ; Mon, 22 Jul 2024 16:55:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721667306; x=1753203306; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=F/v/RYPyAZ3OtoFi2SCp0vtMC6r17mysIizevYNQVLI=; b=gWr4wsD5zfH5pVH4AOdUanCxZ034jBpGWGgGcOeB1BRCubKRHGY49PwO S6PqFxzEwQgHleosjoex/28NB1eHeoYdpfZyG6bVKEq8Oz0vFECUYsCQb 8/UR6to4fFKPT/Wcd4+6X67AAshfMrZPiOWyv1aC44V+ZvppyyUucyxg6 d9ANcDJNWBS4bqW8zGjE9aY0FpGYDTsbT1HJnFJDnwNrwt12l5XnYSrd/ bDzXKDePR8/vJuSTcdqClOSjBF8Eb23OJIqVuvCedMiHceCzQmJSzuko+ 8KsBosomxQFKbiIYd8Ue+dvCuvlCHxYS/V7qFoKif7jNsBeasV0yfKZr/ g==; X-CSE-ConnectionGUID: OrFRLau3Sq2rVfSeNRSs0Q== X-CSE-MsgGUID: 8+oPbfh3Q5+dUxeeVOI/jw== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="23117331" X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="23117331" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:05 -0700 X-CSE-ConnectionGUID: 4s9ewpHoSjK7u3JT8tUqww== X-CSE-MsgGUID: O//u4lvvQGuKxXH3T5TDnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,228,1716274800"; d="scan'208";a="57056341" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2024 09:55:05 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 14/14] drm/i915/dp_mst: Enable LT fallback between UHBR/non-UHBR link rates Date: Mon, 22 Jul 2024 19:55:03 +0300 Message-ID: <20240722165503.2084999-15-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722165503.2084999-1-imre.deak@intel.com> References: <20240722165503.2084999-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable switching between UHBR and non-UHBR link rates on MST links when reducing the link parameters after an LT failure. Signed-off-by: Imre Deak Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 0c8e0d6437b5b..270080b2735f2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1188,11 +1188,6 @@ static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, intel_dp->link.force_lane_count != lane_count)) continue; - /* TODO: Make switching from UHBR to non-UHBR rates work. */ - if (drm_dp_is_uhbr_rate(crtc_state->port_clock) != - drm_dp_is_uhbr_rate(link_rate)) - continue; - break; }