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Tue, 23 Jul 2024 05:15:51 -0400 (EDT) From: Jiaxun Yang Date: Tue, 23 Jul 2024 17:15:44 +0800 Subject: [PATCH] MIPS: Loongson64: Set timer mode in cpu-probe Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240723-loongson-exttimer-v1-1-974bef8c2f88@flygoat.com> X-B4-Tracking: v=1; b=H4sIAL90n2YC/x3MQQqAIBBA0avErBPULKOrRAvLyQZKQyWC6O5Jy 7f4/4GEkTDBUD0Q8aJEwReIuoJlM94hI1sMkkvFtWzYHoJ3KXiGd850YGRCzapHbWxrOyjdGXG l+3+O0/t+FyovMmMAAAA= To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1810; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=mROYaCllljLDe6KGxHnovReLJUhId6M0dmLIG9l0n0Q=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrT5JccPX0q4anrDnd+rS4NbSdEunVU2c31PSSKvkZfhu j0TL5R3lLIwiHExyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwETCPzIynLda4ezFki39vTZP vzDtEHvtlo8H+9aHJrt2OLbNuPHmBcP/yODzyZanJK/I1uTMP/PveFoaZ+SUmtlxqfFLnvAHHbT hAgA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Loongson64 C and G processors have EXTIMER feature which is conflicting with CP0 counter. Although the processor resets in EXTIMER disabled & INTIMER enabled mode, which is compatible with MIPS CP0 compare, firmware may attempt to enable EXTIMER and interfere CP0 compare. Set timer mode back to MIPS compatible mode to fix booting on systems with such firmware before we have an actual driver for EXTIMER. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang --- Please take this patch via fixes (or second 6.11 PR) tree so it can reach stable faster. Thansks! --- arch/mips/kernel/cpu-probe.c | 4 ++++ 1 file changed, 4 insertions(+) --- base-commit: dee7f101b64219f512bb2f842227bd04c14efe30 change-id: 20240723-loongson-exttimer-14b48e7ad5d6 Best regards, diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index bda7f193baab..af7412549e6e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1724,12 +1724,16 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ + change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, + LOONGSON_CONF6_INTIMER); break; case PRID_IMP_LOONGSON_64G: __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3a"); set_isa(c, MIPS_CPU_ISA_M64R2); decode_cpucfg(c); + change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, + LOONGSON_CONF6_INTIMER); break; default: panic("Unknown Loongson Processor ID!");