From patchwork Tue Jul 23 11:20:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86A71C3DA63 for ; Tue, 23 Jul 2024 11:21:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 022F910E56F; Tue, 23 Jul 2024 11:21:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jrIIRYuD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA5A510E5B7 for ; Tue, 23 Jul 2024 11:21:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721733691; x=1753269691; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JGqZlLASKOiUpSGJmG2JheBwcGaqDp6yUy/4Dd817zo=; b=jrIIRYuDigpFK/K2rw9u1ZZoJjoPBTSrv5mqlyQFIkjjazLqYG+UAQIu IacmwY1sli20WN3HdIQKRt9vbA3AGcn+u0l0i8XqU7OPuQs/lgz7C2QOv dAE8UZ8itnjKRTtkL8lerwjFnulegn+m7lacf1YidOP3foee017Yt2XdB frIgLLd4XfMgNUG6vSOxJBEz7pFQtoNIxdumStKFBe4Hqvv0rzV8YflYk vQ1BY07imoMqntshUUH+WntLfk4TQIoXCBr1qV+bdbuKTAaeezD+BgiIv iT1vLNo4MpZT4KpwhNrAxOLWVi0fp5gRoku+g35VhSLakEdF0NdYvHfQU Q==; X-CSE-ConnectionGUID: DExndnByQTycaSemlVUS2A== X-CSE-MsgGUID: I/GVcHyLQbK8xHt8OTIAqg== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="19225368" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="19225368" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:26 -0700 X-CSE-ConnectionGUID: 6TK4kVWkSpGuUcudshnFHg== X-CSE-MsgGUID: d7FiloBwRTOerSxc9nAcFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267413" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:25 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 1/9] drm/i915/gt: Refactor uabi engine class/instance list creation Date: Tue, 23 Jul 2024 13:20:38 +0200 Message-ID: <20240723112046.123938-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For the upcoming changes we need a cleaner way to build the list of uabi engines. Suggested-by: Tvrtko Ursulin Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 ++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 833987015b8b..11cc06c0c785 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -203,7 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 void intel_engines_driver_register(struct drm_i915_private *i915) { - u16 name_instance, other_instance = 0; + u16 class_instance[I915_LAST_UABI_ENGINE_CLASS + 2] = { }; struct legacy_ring ring = {}; struct list_head *it, *next; struct rb_node **p, *prev; @@ -214,6 +214,8 @@ void intel_engines_driver_register(struct drm_i915_private *i915) prev = NULL; p = &i915->uabi_engines.rb_node; list_for_each_safe(it, next, &engines) { + u16 uabi_class; + struct intel_engine_cs *engine = container_of(it, typeof(*engine), uabi_list); @@ -222,15 +224,14 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes)); engine->uabi_class = uabi_classes[engine->class]; - if (engine->uabi_class == I915_NO_UABI_CLASS) { - name_instance = other_instance++; - } else { - GEM_BUG_ON(engine->uabi_class >= - ARRAY_SIZE(i915->engine_uabi_class_count)); - name_instance = - i915->engine_uabi_class_count[engine->uabi_class]++; - } - engine->uabi_instance = name_instance; + + if (engine->uabi_class == I915_NO_UABI_CLASS) + uabi_class = I915_LAST_UABI_ENGINE_CLASS + 1; + else + uabi_class = engine->uabi_class; + + GEM_BUG_ON(uabi_class >= ARRAY_SIZE(class_instance)); + engine->uabi_instance = class_instance[uabi_class]++; /* * Replace the internal name with the final user and log facing @@ -238,11 +239,15 @@ void intel_engines_driver_register(struct drm_i915_private *i915) */ engine_rename(engine, intel_engine_class_repr(engine->class), - name_instance); + engine->uabi_instance); - if (engine->uabi_class == I915_NO_UABI_CLASS) + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) continue; + GEM_BUG_ON(uabi_class >= + ARRAY_SIZE(i915->engine_uabi_class_count)); + i915->engine_uabi_class_count[uabi_class]++; + rb_link_node(&engine->uabi_node, prev, p); rb_insert_color(&engine->uabi_node, &i915->uabi_engines); From patchwork Tue Jul 23 11:20:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75C10C3DA63 for ; Tue, 23 Jul 2024 11:21:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAD2010E568; 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X-CSE-ConnectionGUID: Fguvna04SKy5S/4iuHgo5w== X-CSE-MsgGUID: adaqfvrnT6+cRyRxNhm7hw== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="19225377" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="19225377" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:30 -0700 X-CSE-ConnectionGUID: 0QJeYbZoT0OhK5HDl51KPw== X-CSE-MsgGUID: 0RRvxTSRQhGoIuaUDcqqOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267433" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:29 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 2/9] drm/i915/gt: Rename "cslises" with "cslice_mask" Date: Tue, 23 Jul 2024 13:20:39 +0200 Message-ID: <20240723112046.123938-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" drm/i915/gt: Rename "cslises" variable to clarify its purpose The "cslises" variable stores the mask of the CCS engines after calculating the fused ones and before setting the CCS mode. Since it represents a mask and not the number of CCS slices, rename it to reflect its actual purpose to avoid confusion. No functional changes intended. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 3b740ca25000..ea908dbec2ab 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -889,7 +889,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) * Store the number of active cslices before * changing the CCS engine configuration */ - gt->ccs.cslices = CCS_MASK(gt); + gt->ccs.cslice_mask = CCS_MASK(gt); /* Mask off all the CCS engine */ info->engine_mask &= ~GENMASK(CCS3, CCS0); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 3c62a44e9106..109b13b4017d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -19,7 +19,7 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { - if (gt->ccs.cslices & BIT(cslice)) + if (gt->ccs.cslice_mask & BIT(cslice)) /* * If available, assign the cslice * to the first available engine... diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index cfdd2ad5e954..3c9fae53871a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -212,7 +212,7 @@ struct intel_gt { * Mask of the non fused CCS slices * to be used for the load balancing */ - intel_engine_mask_t cslices; + intel_engine_mask_t cslice_mask; } ccs; /* From patchwork Tue Jul 23 11:20:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A224C3DA49 for ; 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X-CSE-ConnectionGUID: /QVHKN52RiO6PxGROMVGBg== X-CSE-MsgGUID: gTFCxsllS9mchsf8XDbIfg== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="19225388" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="19225388" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:35 -0700 X-CSE-ConnectionGUID: BLwFTl+nRQSzW4b0y1MiNg== X-CSE-MsgGUID: q7NfEsb5RcOKXy4/gTdA4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267439" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:34 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 3/9] drm/i915/gt: Move CCS mode mask creation to intel_ccs_mode.c Date: Tue, 23 Jul 2024 13:20:40 +0200 Message-ID: <20240723112046.123938-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In anticipation of upcoming patches, it is more convenient to move the CCS mode mask creation to the intel_ccs_mode.c file, which serves as a placeholder for all CCS engine settings. No functional changes intended. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 50 --------------------- drivers/gpu/drm/i915/gt/intel_gt.c | 3 ++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 46 +++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 + 4 files changed, 50 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index ea908dbec2ab..8011df30023e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -812,32 +812,6 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); } -static void engine_mask_apply_compute_fuses(struct intel_gt *gt) -{ - struct drm_i915_private *i915 = gt->i915; - struct intel_gt_info *info = >->info; - int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; - unsigned long ccs_mask; - unsigned int i; - - if (GRAPHICS_VER(i915) < 11) - return; - - if (hweight32(CCS_MASK(gt)) <= 1) - return; - - ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, - ss_per_ccs); - /* - * If all DSS in a quadrant are fused off, the corresponding CCS - * engine is not available for use. - */ - for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) { - info->engine_mask &= ~BIT(_CCS(i)); - gt_dbg(gt, "ccs%u fused off\n", i); - } -} - /* * Determine which engines are fused off in our particular hardware. * Note that we have a catch-22 situation where we need to be able to access @@ -855,7 +829,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) GEM_BUG_ON(!info->engine_mask); engine_mask_apply_media_fuses(gt); - engine_mask_apply_compute_fuses(gt); /* * The only use of the GSC CS is to load and communicate with the GSC @@ -874,29 +847,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) info->engine_mask &= ~BIT(GSC0); } - /* - * Do not create the command streamer for CCS slices beyond the first. - * All the workload submitted to the first engine will be shared among - * all the slices. - * - * Once the user will be allowed to customize the CCS mode, then this - * check needs to be removed. - */ - if (IS_DG2(gt->i915)) { - u8 first_ccs = __ffs(CCS_MASK(gt)); - - /* - * Store the number of active cslices before - * changing the CCS engine configuration - */ - gt->ccs.cslice_mask = CCS_MASK(gt); - - /* Mask off all the CCS engine */ - info->engine_mask &= ~GENMASK(CCS3, CCS0); - /* Put back in the first CCS engine */ - info->engine_mask |= BIT(_CCS(first_ccs)); - } - return info->engine_mask; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index a6c69a706fd7..55546482355b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -17,6 +17,7 @@ #include "intel_engine_regs.h" #include "intel_ggtt_gmch.h" #include "intel_gt.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_buffer_pool.h" #include "intel_gt_clock_utils.h" #include "intel_gt_debugfs.h" @@ -136,6 +137,8 @@ int intel_gt_init_mmio(struct intel_gt *gt) intel_sseu_info_init(gt); intel_gt_mcr_init(gt); + intel_gt_ccs_mode_init(gt); + return intel_engines_init_mmio(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 109b13b4017d..06d9d1a94317 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -6,8 +6,54 @@ #include "i915_drv.h" #include "intel_gt.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_print.h" #include "intel_gt_regs.h" +void intel_gt_ccs_mode_init(struct intel_gt *gt) +{ + struct intel_gt_info *info = >->info; + unsigned long fused_mask; + int ss_per_ccs; + unsigned int i; + u8 first_ccs; + + /* Calculate the slices considering the fused engines */ + ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; + fused_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, + ss_per_ccs); + + /* Remove the fused engines from the engine_mask */ + for_each_clear_bit(i, &fused_mask, I915_MAX_CCS) { + info->engine_mask &= ~BIT(_CCS(i)); + gt_dbg(gt, "ccs%u fused off\n", i); + } + + /* + * Store the number of active cslices before + * changing the CCS engine configuration + */ + gt->ccs.cslice_mask = CCS_MASK(gt); + + /* + * Normally only DG2 platforms have more than one CCS, + * no need to change the ccs balance settings all the GPU's. + */ + if (!IS_DG2(gt->i915)) + return; + + /* + * As a default behavior, do not create the command streamer for CCS + * slices beyond the first. All the workload submitted to the first + * engine will be shared among all the slices. + */ + first_ccs = __ffs(CCS_MASK(gt)); + + /* Mask off all the CCS engine */ + info->engine_mask &= ~GENMASK(CCS3, CCS0); + /* Put back in the first CCS engine */ + info->engine_mask |= BIT(_CCS(first_ccs)); +} + unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 55547f2ff426..a8b513c43a4f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -9,5 +9,6 @@ struct intel_gt; unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ From patchwork Tue Jul 23 11:20:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE86BC3DA63 for ; Tue, 23 Jul 2024 11:21:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB90410E571; Tue, 23 Jul 2024 11:21:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="A8XwDXXz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3444010E570 for ; Tue, 23 Jul 2024 11:21:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721733700; x=1753269700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GIxIzUMkkyTcSzCr175q/V9fSwMKeXmPuZql8pvhYf0=; b=A8XwDXXzOlVxAJqCxtXjkC1lTROKS0y9yggIkPMcF9WXK6/WqVZ3Ftq7 zzkRzkFMuT2obPkbmExegB/moW8n66xMFJbMeNwjDiHVijgH2JrZ2pTFG cDzHV4n3mjb9vYkJe6YRVgTlfD5Mwznln5EoP0Nb/U05GKhAuPmQX7nTq FQwFQqLYclK36ru4a9hhORuBPisb0dnM8n+FWUPww9ZGNYEij3vw1Ko3E S84QbZIuI3+fysw/LM3DYfrg5/iZEwEzzJPediMtfvmA+5zcdWc/uKSXs Uwp6REJpZcB7SuHat/g5gPkhm4JlUn+w/H8Gxe9+bXPJizZbPLJbd3Qd6 g==; X-CSE-ConnectionGUID: /xGIVLGDTreSwWdCABLC2A== X-CSE-MsgGUID: P4+z11g2RSCGbRctJibIxA== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="19225397" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="19225397" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:39 -0700 X-CSE-ConnectionGUID: TPM9tb5xSQuNQtIKgaBsRg== X-CSE-MsgGUID: MfWE6VS6QB2QoXHO7bpXOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267446" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:38 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 4/9] drm/i915/gt: Expose the number of total CCS slices Date: Tue, 23 Jul 2024 13:20:41 +0200 Message-ID: <20240723112046.123938-5-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement a sysfs interface to show the number of available CCS slices. The displayed number does not take into account the CCS balancing mode. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 23 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 2 ++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 06d9d1a94317..0710e55d37d7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,6 +8,7 @@ #include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" +#include "intel_gt_sysfs.h" void intel_gt_ccs_mode_init(struct intel_gt *gt) { @@ -83,3 +84,25 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) return mode; } + +static ssize_t num_cslices_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 num_slices; + + num_slices = hweight32(gt->ccs.cslice_mask); + + return sysfs_emit(buff, "%u\n", num_slices); +} +static DEVICE_ATTR_RO(num_cslices); + +void intel_gt_sysfs_ccs_init(struct intel_gt *gt) +{ + int err; + + err = sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr); + if (err) + gt_dbg(gt, "failed to create sysfs num_cslices files\n"); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index a8b513c43a4f..b9ce29055857 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -9,6 +9,7 @@ struct intel_gt; unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_sysfs_ccs_init(struct intel_gt *gt); void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 33cba406b569..895eedc402ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "i915_sysfs.h" #include "intel_gt.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_sysfs.h" #include "intel_gt_sysfs_pm.h" @@ -101,6 +102,7 @@ void intel_gt_sysfs_register(struct intel_gt *gt) goto exit_fail; intel_gt_sysfs_pm_init(gt, >->sysfs_gt); + intel_gt_sysfs_ccs_init(gt); return; From patchwork Tue Jul 23 11:20:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1CC5C3DA70 for ; Tue, 23 Jul 2024 11:21:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B54910E572; Tue, 23 Jul 2024 11:21:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Q6AW910v"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE14310E570 for ; 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23 Jul 2024 04:21:43 -0700 X-CSE-ConnectionGUID: YKLPnNKhSRGAFqPS1QBg6A== X-CSE-MsgGUID: 181q2l3BQF+zcPMZDcrs9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267456" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:42 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 5/9] drm/i915/gt: Move the CCS mode variable to a global position Date: Tue, 23 Jul 2024 13:20:42 +0200 Message-ID: <20240723112046.123938-6-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Store the CCS mode value in the intel_gt->ccs structure to make it available for future instances that may need to change its value. Name it mode_reg_val because it holds the value that will be written into the CCS_MODE register, determining the CCS balancing and, consequently, the number of engines generated. Create a mutex to control access to the mode_reg_val variable. No functional changes intended. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 10 +++++++--- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 12 ++++++++++++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++--- 4 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 0710e55d37d7..8acb9ee5b511 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -18,6 +18,8 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) unsigned int i; u8 first_ccs; + mutex_init(>->ccs.mutex); + /* Calculate the slices considering the fused engines */ ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; fused_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, @@ -55,14 +57,16 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) info->engine_mask |= BIT(_CCS(first_ccs)); } -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) +void intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); + lockdep_assert_held(>->ccs.mutex); + if (!IS_DG2(gt->i915)) - return 0; + return; /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { @@ -82,7 +86,7 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - return mode; + gt->ccs.mode_reg_val = mode; } static ssize_t num_cslices_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index b9ce29055857..5793c4178bd9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,7 +8,7 @@ struct intel_gt; -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_apply_ccs_mode(struct intel_gt *gt); void intel_gt_sysfs_ccs_init(struct intel_gt *gt); void intel_gt_ccs_mode_init(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 3c9fae53871a..ef803ace41a3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -207,12 +207,24 @@ struct intel_gt { [MAX_ENGINE_INSTANCE + 1]; enum intel_submission_method submission_method; + /* + * Track fixed mapping between CCS engines and compute slices. + * + * In order to w/a HW that has the inability to dynamically load + * balance between CCS engines and EU in the compute slices, we have to + * reconfigure a static mapping on the fly. + * + * The mode variable is set by the user and sets the balancing mode, + * i.e. how the CCS streams are distributed amongs the slices. + */ struct { /* * Mask of the non fused CCS slices * to be used for the load balancing */ + struct mutex mutex; intel_engine_mask_t cslice_mask; + u32 mode_reg_val; } ccs; /* diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 09a287c1aedd..379b3dde3bbd 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2713,7 +2713,6 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; - u32 mode; if (!IS_DG2(gt->i915)) return; @@ -2730,8 +2729,10 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 */ - mode = intel_gt_apply_ccs_mode(gt); - wa_masked_en(wal, XEHP_CCS_MODE, mode); + mutex_lock(>->ccs.mutex); + intel_gt_apply_ccs_mode(gt); + wa_masked_en(wal, XEHP_CCS_MODE, gt->ccs.mode_reg_val); + mutex_unlock(>->ccs.mutex); } /* From patchwork Tue Jul 23 11:20:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9103DC3DA49 for ; Tue, 23 Jul 2024 11:21:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 207A310E570; Tue, 23 Jul 2024 11:21:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eUWOHN46"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECFD510E575 for ; Tue, 23 Jul 2024 11:21:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721733708; x=1753269708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9YlkTmjXmS2ih1LWTRbuSVKX879XrjCADknwlyh6fYI=; b=eUWOHN460yyoZ63fgnDmxTx4gggp4nvbDKoHWx6ZqTGDW0pH6q2V1IYA Jqey5TdYpu85q0VMJWQ0UPSEuKWBPFAHjvKSD8BTut041ml+Y+0r3B0y4 KLpkUV3095a8IVeGvSH2XpAGLKa8T2qPDNk0fjjPHyHd5Itedr7TNpm+1 tj9X8pOXZWUssUjCuiwhtCOSAcEyPRcpOdK0dBI0BYLq1CLcD714Arel7 btMPtprhdLJaE3rakzsJSiBw/t7Yb+ubXfT814iBRuYxWbm3JrTck6Rgq doOXWPu6Wtniok5q5vThSl9xL0CSK6aTSQJyYN3cFQZhoOF+2x+gSPVoT Q==; X-CSE-ConnectionGUID: FEJfF8mDSym1MnSWierrvw== X-CSE-MsgGUID: HxgIfMplQ1KKVzkuAFjNUg== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="19225420" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="19225420" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:47 -0700 X-CSE-ConnectionGUID: k+n9qgwCTCO0b3x65CFsNw== X-CSE-MsgGUID: z1O7yDVbS3uAoOp9e7As5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267473" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:46 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 6/9] drm/i915/gt: Add sysfs cleanup function for engines Date: Tue, 23 Jul 2024 13:20:43 +0200 Message-ID: <20240723112046.123938-7-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Engines and their properties are exposed in: /sys/class/drm/cardX/engine/ These files are cleaned up when the driver is removed. However, when the presence of engines starts changing dynamically, we need a function to clean up the existing ones. Store the engine-related objects (kobj and kobj_defaults) in the 'intel_engine_cs' structure, and store the main directory's object (sysfs_engines) in the 'drm_i915_private' structure. No functional changes intended at this point, as this function does not have users yet. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++ drivers/gpu/drm/i915/gt/sysfs_engines.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/gt/sysfs_engines.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + 5 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 8011df30023e..92043ad19409 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -716,6 +716,8 @@ void intel_engines_free(struct intel_gt *gt) kfree(engine); gt->engine[id] = NULL; } + + memset(gt->engine_class, 0, sizeof(gt->engine_class)); } static diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index ba55c059063d..a0f2f5c08388 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -388,6 +388,9 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + struct kobject *kobj; + struct kobject *kobj_defaults; + struct intel_engine_tlb_inv tlb_inv; /* diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index 021f51d9b456..a38c1732848e 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -479,6 +479,8 @@ static void add_defaults(struct kobj_engine *parent) if (intel_engine_has_preempt_reset(ke->engine) && sysfs_create_file(&ke->base, &preempt_timeout_def.attr)) return; + + parent->engine->kobj_defaults = &ke->base; } void intel_engines_add_sysfs(struct drm_i915_private *i915) @@ -506,6 +508,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) if (!dir) return; + i915->sysfs_engine = dir; + for_each_uabi_engine(engine, i915) { struct kobject *kobj; @@ -526,6 +530,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) add_defaults(container_of(kobj, struct kobj_engine, base)); + engine->kobj = kobj; + if (0) { err_object: kobject_put(kobj); @@ -536,3 +542,15 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) } } } + +void intel_engines_remove_sysfs(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + + for_each_uabi_engine(engine, i915) { + kobject_put(engine->kobj_defaults); + kobject_put(engine->kobj); + } + + kobject_put(i915->sysfs_engine); +} diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.h b/drivers/gpu/drm/i915/gt/sysfs_engines.h index 9546fffe03a7..09293a010025 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.h +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.h @@ -9,5 +9,6 @@ struct drm_i915_private; void intel_engines_add_sysfs(struct drm_i915_private *i915); +void intel_engines_remove_sysfs(struct drm_i915_private *i915); #endif /* INTEL_ENGINE_SYSFS_H */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d7723dd11c80..1bdf9a0115c1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -320,6 +320,7 @@ struct drm_i915_private { struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; + struct kobject *sysfs_engine; /* Quick lookup of media GT (current platforms only have one) */ struct intel_gt *media_gt; From patchwork Tue Jul 23 11:20:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F12ABC3DA63 for ; Tue, 23 Jul 2024 11:22:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1630210E57A; Tue, 23 Jul 2024 11:22:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hQC7VA8H"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C44010E576 for ; Tue, 23 Jul 2024 11:21:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721733712; x=1753269712; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=92VWHF3jjQ0LOFu8mc0SRcS87YTw7CHWrn3kZhJ5/FA=; b=hQC7VA8HfiWreV/TvPcwikFQ7yLI0YVsWomWLlefzCfYclyhd/MMrKBw gML8FjhDlItJybosLJLc1AMkFTaVHAMqMmsNIOHxvuEJ1DM8Ty1Quy+dM Y8VPdzGUy8KSAePgq9U5uZ5aIyIMo/g1kDASZOiy/5fDMwnQterz/D1tt F2PoYwPgEjTR9v34ePoM7/4wljh/J9JuwIYYj7hivz8HQQTf8pnD0eeRv MKoB92tgYhvn7oYe+AW59YMlBj0hYqTvkKtk2ywAJ7PfZpkBnM0xDqV2Z ZiRuKGftC5KhUVaf6cmGOCuX73kMFjQr4w9aQG4klTIz257WrMOq+CDEp Q==; X-CSE-ConnectionGUID: SddrJFpvSP6OxOv9CTTw+A== X-CSE-MsgGUID: cenneS2wTMutJGG0ew06/A== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="19225439" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="19225439" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:52 -0700 X-CSE-ConnectionGUID: o7tpuAKQReeoH0HN0VtTGw== X-CSE-MsgGUID: j2SHw3xlQyeswae4iyyyUg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52267486" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:51 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 7/9] drm/i915/gt: Allow the creation of multi-mode CCS masks Date: Tue, 23 Jul 2024 13:20:44 +0200 Message-ID: <20240723112046.123938-8-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Until now, we have only set CCS mode balancing to 1, which means that only one compute engine is exposed to the user. The stream of compute commands submitted to that engine is then shared among all the dedicated execution units. This is done by calling the 'intel_gt_apply_ccs_mode(); function. With this change, the aforementioned function takes an additional parameter called 'mode' that specifies the desired mode to be set for the CCS engines balancing. The mode parameter can have the following values: - mode = 0: CCS load balancing mode 1 (1 CCS engine exposed) - mode = 1: CCS load balancing mode 2 (2 CCS engines exposed) - mode = 3: CCS load balancing mode 4 (4 CCS engines exposed) This allows us to generate the appropriate register value to be written to CCS_MODE, configuring how the exposed engine streams will be submitted to the execution units. No functional changes are intended yet, as no mode higher than '0' is currently being set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 78 ++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 3 files changed, 65 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 8acb9ee5b511..0d733b3e8df3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -4,7 +4,6 @@ */ #include "i915_drv.h" -#include "intel_gt.h" #include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" @@ -57,33 +56,80 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) info->engine_mask |= BIT(_CCS(first_ccs)); } -void intel_gt_apply_ccs_mode(struct intel_gt *gt) +void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) { + unsigned long cslices_mask = gt->ccs.cslice_mask; + u32 mode_val = 0; + int ccs_id; int cslice; - u32 mode = 0; - int first_ccs = __ffs(CCS_MASK(gt)); + u32 m = mode; lockdep_assert_held(>->ccs.mutex); if (!IS_DG2(gt->i915)) return; - /* Build the value for the fixed CCS load balancing */ - for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { - if (gt->ccs.cslice_mask & BIT(cslice)) - /* - * If available, assign the cslice - * to the first available engine... - */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs); + /* + * The mode has two bit dedicated for each engine + * that will be used for the CCS balancing algorithm: + * + * BIT | CCS slice + * ------------------ + * 0 | CCS slice + * 1 | 0 + * ------------------ + * 2 | CCS slice + * 3 | 1 + * ------------------ + * 4 | CCS slice + * 5 | 2 + * ------------------ + * 6 | CCS slice + * 7 | 3 + * ------------------ + * + * When a CCS slice is not available, then we will write 0x7, + * oterwise we will write the user engine id which load will + * be forwarded to that slice. + * + * The possible configurations are: + * + * 1 engine (ccs0): + * slice 0, 1, 2, 3: ccs0 + * + * 2 engines (ccs0, ccs1): + * slice 0, 2: ccs0 + * slice 1, 3: ccs1 + * + * 4 engines (ccs0, ccs1, ccs2, ccs3): + * slice 0: ccs0 + * slice 1: ccs1 + * slice 2: ccs2 + * slice 3: ccs3 + */ + ccs_id = __ffs(cslices_mask); - else + for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { + if (!(cslices_mask & BIT(cslice))) { /* - * ... otherwise, mark the cslice as - * unavailable if no CCS dispatches here + * If not available, mark the slice as unavailable + * and no task will be dispatched here. */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, XEHP_CCS_MODE_CSLICE_MASK); + continue; + } + + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, ccs_id); + + if (!m) { + m = mode; + ccs_id = __ffs(cslices_mask); + continue; + } + + m--; + ccs_id = find_next_bit(&cslices_mask, I915_MAX_CCS, ccs_id + 1); } gt->ccs.mode_reg_val = mode; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 5793c4178bd9..c60bfdb54e37 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -6,9 +6,9 @@ #ifndef __INTEL_GT_CCS_MODE_H__ #define __INTEL_GT_CCS_MODE_H__ -struct intel_gt; +#include "intel_gt.h" -void intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode); void intel_gt_sysfs_ccs_init(struct intel_gt *gt); void intel_gt_ccs_mode_init(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 379b3dde3bbd..8770bde646eb 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2730,7 +2730,7 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * assign all slices to a single CCS. We will call it CCS mode 1 */ mutex_lock(>->ccs.mutex); - intel_gt_apply_ccs_mode(gt); + intel_gt_apply_ccs_mode(gt, 0); wa_masked_en(wal, XEHP_CCS_MODE, gt->ccs.mode_reg_val); mutex_unlock(>->ccs.mutex); } From patchwork Tue Jul 23 11:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6F9AC3DA49 for ; Tue, 23 Jul 2024 11:22:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C5FF10E577; Tue, 23 Jul 2024 11:22:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KbEQhKI3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C39A10E57B for ; Tue, 23 Jul 2024 11:21:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721733717; x=1753269717; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pBeeglo8AqdAtTf8iMeYXHtwA4aGKKhVHJG/MxxCA80=; b=KbEQhKI3Kz+EqRjKNmSfzoHXAfM7DD2FmO/JJ/RL80Du58hXjd4dnTMx zg1yBJoyKVrkzBwCFPhE3pwFe8A9WgcbJhfVinQMYvq5btyoyWs7CwOY6 PmX/LBaobiyd+jZv0FdAnFutioTVBJPZwux6PlqwTOBXIi9SiaGhc38Bw 2EaywCcvb5KCrAdnlkGLHXqYavVaUW/lYgYNNWMcr5mtBWSPcBYzhjZ93 IwxQ5vdO9HBRiBcV0XWaUJTUdOGCph/hZmsGZJn2GUf5DBYM02XhRFDG7 C6JmvBx4vGbuK8GBLwWwVUZFH8GgKd77P5/XkLaVFATh0qCuMYsmHuCzn g==; X-CSE-ConnectionGUID: Pw9UE60rSEyHnZkqxJq85Q== X-CSE-MsgGUID: 3Uc2ROI1SmKAMSLIdhrjqQ== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="18965155" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="18965155" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:57 -0700 X-CSE-ConnectionGUID: 6G/NpyI0TGGmUCl0CokfFA== X-CSE-MsgGUID: tk+zA/FKTjuKyOJTUJ4CAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52814812" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:21:55 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 8/9] drm/i915/gt: Allow the user to change the CCS mode through sysfs Date: Tue, 23 Jul 2024 13:20:45 +0200 Message-ID: <20240723112046.123938-9-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Create the 'ccs_mode' file under /sys/class/drm/cardX/gt/gt0/ccs_mode This file allows the user to read and set the current CCS mode. - Reading: The user can read the current CCS mode, which can be 1, 2, or 4. This value is derived from the current engine mask. - Writing: The user can set the CCS mode to 1, 2, or 4, depending on the desired number of exposed engines and the required load balancing. The interface will return -EBUSY if other clients are connected to i915, or -EINVAL if an invalid value is set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 108 ++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 0d733b3e8df3..7773a04981a4 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -4,10 +4,27 @@ */ #include "i915_drv.h" +#include "intel_engine_user.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_pm.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" +#include "i915_perf.h" +#include "sysfs_engines.h" + +static void engine_update_mask(struct intel_gt *gt, u32 ccs_mode) +{ + unsigned long ccs_mask = gt->ccs.cslice_mask; + struct intel_gt_info *info = >->info; + int i; + + /* Mask off all the CCS engines */ + info->engine_mask &= ~GENMASK(CCS3, CCS0); + + for_each_set_bit(i, &ccs_mask, I915_MAX_CCS) + info->engine_mask |= BIT(_CCS(i)); +} void intel_gt_ccs_mode_init(struct intel_gt *gt) { @@ -148,6 +165,86 @@ static ssize_t num_cslices_show(struct device *dev, } static DEVICE_ATTR_RO(num_cslices); +static ssize_t ccs_mode_show(struct device *dev, + struct device_attribute *attr, char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 ccs_mode; + + ccs_mode = hweight32(CCS_MASK(gt)); + + return sysfs_emit(buff, "%u\n", ccs_mode); +} + +static ssize_t ccs_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + int num_cslices = hweight32(gt->ccs.cslice_mask); + struct intel_engine_cs *engine; + enum intel_engine_id id; + intel_wakeref_t wakeref; + ssize_t ret; + u32 val; + + /* + * We don't want to change the CCS + * mode while someone is using the GT + */ + if (intel_gt_pm_is_awake(gt)) + return -EBUSY; + + ret = kstrtou32(buff, 0, &val); + if (ret) + return ret; + + /* + * As of now possible values to be set are 1, 2, 4, + * up to the maximum number of available slices + */ + if ((!val) || (val > num_cslices) || (num_cslices % val)) + return -EINVAL; + + /* + * Nothing to do if the requested setting + * is the same as the current one + */ + if (val == hweight32(CCS_MASK(gt))) + return count; + + /* Recreate engine exposure */ + intel_engines_remove_sysfs(gt->i915); + + mutex_lock(>->ccs.mutex); + intel_gt_apply_ccs_mode(gt, val - 1); + mutex_unlock(>->ccs.mutex); + + wakeref = intel_runtime_pm_get(gt->uncore->rpm); + + i915_perf_fini(gt->i915); + intel_engines_release(gt); + intel_engines_free(gt); + + mutex_lock(>->ccs.mutex); + engine_update_mask(gt, val); + mutex_unlock(>->ccs.mutex); + + intel_engines_init_mmio(gt); + i915_perf_init(gt->i915); + intel_engines_init(gt); + + gt->i915->uabi_engines = RB_ROOT; + intel_engines_driver_register(gt->i915); + + intel_runtime_pm_put(gt->uncore->rpm, wakeref); + + intel_engines_add_sysfs(gt->i915); + + return count; +} +static DEVICE_ATTR_RW(ccs_mode); + void intel_gt_sysfs_ccs_init(struct intel_gt *gt) { int err; @@ -155,4 +252,15 @@ void intel_gt_sysfs_ccs_init(struct intel_gt *gt) err = sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr); if (err) gt_dbg(gt, "failed to create sysfs num_cslices files\n"); + + /* + * Do not create the ccs_mode file for non DG2 platforms + * because they don't need it as they have only one CCS engine + */ + if (!IS_DG2(gt->i915)) + return; + + err = sysfs_create_file(>->sysfs_gt, &dev_attr_ccs_mode.attr); + if (err) + gt_dbg(gt, "failed to create sysfs ccs_mode files\n"); } From patchwork Tue Jul 23 11:20:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13739942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3AE3C3DA63 for ; Tue, 23 Jul 2024 11:22:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 33C2310E578; Tue, 23 Jul 2024 11:22:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TWJNBSjD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 14DBB10E57D for ; Tue, 23 Jul 2024 11:22:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721733722; x=1753269722; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=My1eKJlOqoONfqwGbzmsKY/Kbpabs5JNodHFdHUj7lI=; b=TWJNBSjD6YuvU7vb9PzgIwF8AD7+gn4ErpWv4MW82opRqk/wHZJMyP/d UZgKWFERurMFZjL/bSTg2TZrEysw3jbHi3NGg46gyoRICrwSfw4FtVcq7 umh2Sxx+CSteRCJ+0qXbdmK0rYpmOyvPmEdmqj8sJFK9mkLnAnO6CE4iH QjUqbRz6vaOqdKDyECNd0inmKQDNegSyIfcYYAafFVlJEZvpPwniZMxwW nzpowxJlW4RFsQZNoHhVsxPQZOZC1vmvgB09FoEjjLsOP7ZT07rAqOcKa QmVsK1Fm4Njp9787aVlvyM4FlS+81EXOM75r90LJOvktAxUEjg1wqWSle w==; X-CSE-ConnectionGUID: BTaibsXKTaOotR+x/jEKkA== X-CSE-MsgGUID: 7i6yTia8Q7KhweJYR/F7gA== X-IronPort-AV: E=McAfee;i="6700,10204,11141"; a="18965162" X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="18965162" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:22:02 -0700 X-CSE-ConnectionGUID: Jhq9Mw6QR/O6JdF17bQoLg== X-CSE-MsgGUID: d0/4NUTqTMChLEb0PQCmBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,230,1716274800"; d="scan'208";a="52814838" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.52]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2024 04:22:00 -0700 From: Andi Shyti To: intel-gfx Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH 9/9] drm/i915/gt: Document CCS mode load balancing Date: Tue, 23 Jul 2024 13:20:46 +0200 Message-ID: <20240723112046.123938-10-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723112046.123938-1-andi.shyti@linux.intel.com> References: <20240723112046.123938-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add documentation for how to set the static CCS load balancing. Signed-off-by: Andi Shyti --- Documentation/gpu/i915.rst | 3 ++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 56 +++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index ad59ae579237..7e4f0d5a4cec 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -341,6 +341,9 @@ for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation. +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_sysfs.c + :doc: CCS load balancing + Locking Guidelines ------------------ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 7773a04981a4..2babd91d4c0e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -165,6 +165,62 @@ static ssize_t num_cslices_show(struct device *dev, } static DEVICE_ATTR_RO(num_cslices); +/** + * DOC: CCS Load Balancing + * + * CCS load balancing involves distributing the commands submitted to the + * compute engine across the various CCS slices. + * + * The initial design was aimed at automatic load balancing, but it was found + * that static load balancing performed better. Static load balancing allows + * users to set the desired balancing mode, also referred to as "CCS mode." This + * approach enables users to determine how the CCS workload is distributed + * among the slices. + * + * The possible modes for CCS balancing depend on the total number of slices, + * which currently does not exceed 4, and applies to DG2 and ATS-M platforms. + * (PVC also has more than 1 CCS engine, but the mode is set through an + * execbuffer setting.) + * + * Given a maximum mode of 4, the CCS mode can be set to 1, 2, or 4. Each mode + * corresponds to the number of CCS engines exposed to userspace, and the load + * is balanced as follows: + * + * CCS mode 1: + * - slices 0, 1, 2, 3: ccs0 + * + * CCS mode 2: + * - slice 0, 2: ccs0 + * - slice 1, 3: ccs1 + * + * CCS mode 4: + * - slice 0: ccs0 + * - slice 1: ccs1 + * - slice 2: ccs2 + * - slice 3: ccs3 + * + * At boot time, the default mode set is '1'. + * + * Two interfaces are generated for the CCS engine: + * + * - ccs_mode: This read-write interface, generated only for DG2 and ATSM, + * shows the current CCS mode when read and sets the CCS mode when written to. + * + * Setting the CCS mode is only possible when no one is using i915, i.e., + * when no client is keeping the interface open. This is to ensure a + * consistent engine topology view among different clients and to guarantee + * that no task is impacted by a runtime CCS mode change. + * + * Writing to this interface can fail, returning the following error codes: + * + * - -EINVAL for attempting to set an invalid mode: when the mode is '0', + * exceeds the number of available slices, or is not a power of 2. + * + * - -EBUSY when other clients are attached to i915. + * + * - num_cslices, read-only: Shows the maximum number of slices and, + * consequently, the highest mode that can be set. + */ static ssize_t ccs_mode_show(struct device *dev, struct device_attribute *attr, char *buff) {