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Tue, 23 Jul 2024 12:38:52 +0000 From: Andrei Stefanescu To: Chester Lin , Matthias Brugger , Ghennadi Procopciuc , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , Andrei Stefanescu Subject: [PATCH] arm64: dts: s32g: add the pinctrl node Date: Tue, 23 Jul 2024 15:37:20 +0300 Message-ID: <20240723123720.1088067-1-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 X-ClientProxiedBy: AM0PR02CA0096.eurprd02.prod.outlook.com (2603:10a6:208:154::37) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|GVXPR04MB10993:EE_ X-MS-Office365-Filtering-Correlation-Id: 190798a6-e55f-4c53-5a48-08dcab146832 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|7416014|376014|1800799024|366016|921020|38350700014; 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Signed-off-by: Andrei Stefanescu --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 51 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 53 +++++++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index fc19ae2e8d3b..b31f6857640b 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -159,5 +159,56 @@ gic: interrupt-controller@50800000 { interrupt-controller; #interrupt-cells = <3>; }; + + pinctrl: pinctrl@4009c240 { + compatible = "nxp,s32g2-siul2-pinctrl"; + /* MSCR0-MSCR101 registers on siul2_0 */ + reg = <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + status = "okay"; + + jtag_pins: jtag_pins { + jtag_grp0 { + pinmux = <0x0>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + + jtag_grp1 { + pinmux = <0x11>; + slew-rate = <166>; + }; + + jtag_grp2 { + pinmux = <0x40>; + input-enable; + bias-pull-down; + slew-rate = <166>; + }; + + jtag_grp3 { + pinmux = <0x23c0>, + <0x23d0>, + <0x2320>; + }; + + jtag_grp4 { + pinmux = <0x51>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index c1b08992754b..7a8c6c943706 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2023 NXP + * Copyright 2021-2024 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -218,6 +218,57 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts = ; }; + + pinctrl: pinctrl@4009c240 { + compatible = "nxp,s32g2-siul2-pinctrl"; + /* MSCR0-MSCR101 registers on siul2_0 */ + reg = <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + status = "okay"; + + jtag_pins: jtag_pins { + jtag_grp0 { + pinmux = <0x0>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + + jtag_grp1 { + pinmux = <0x11>; + slew-rate = <166>; + }; + + jtag_grp2 { + pinmux = <0x40>; + input-enable; + bias-pull-down; + slew-rate = <166>; + }; + + jtag_grp3 { + pinmux = <0x23c0>, + <0x23d0>, + <0x2320>; + }; + + jtag_grp4 { + pinmux = <0x51>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + }; + }; }; timer {