From patchwork Tue Jul 23 13:25:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Paneer Selvam, Arunpravin" X-Patchwork-Id: 13740002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B9E2C3DA63 for ; Tue, 23 Jul 2024 13:26:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47D9B10E5CF; Tue, 23 Jul 2024 13:26:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.b="kDn+Fn5L"; dkim-atps=neutral Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2052.outbound.protection.outlook.com [40.107.96.52]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0958810E5C5; Tue, 23 Jul 2024 13:25:48 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DetdoJ8hnN/5uSR0K86/XCjwdCcr/sf/uU/8UrbSrj1/Obyb/w1A0yM3VXCCuMSXHCt/9nq6R5m9KLuFEyJoWtF9/PEkseWKZC199O8KOxDoB7WIF7wve5hiruClsJdQgyDxv02DZl+p59JxrMxRro8ErsQDwhVdCXYThhMSsWY70H01vsju8INecxx63TvwZXoyH501bs/wjUwy4qddrrtYlMGmwhNsg3b9LJ340egd8XXBezTyZNBVViqIINq95asNuK13OOzlcmXFKdAvXbUY1TA4QYfQ2f8RuFAHoheimWsMfmAV0xG0kgDNrmYfLCnPtitcDBU+i7inQYZsNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=b6UoF1zGqtVrNRypomsBMEF/otGkLEyqVBmoP+knsu4=; b=CZ/kyJaoiQPQgxPPA/mKoCyT57BBcfXRcXJa95t6iwpfAGtvvW/fwKq17sicx4m7xsCWsEb8KNFphovc3iyk1wM5R7ewWY4ygjQzXPQuQWuCpqDbPD2/uDroBwtNPTBc9mahXkZpH4OB7PrueNMUX9Qgz1nfZmRtXsOPU3txt1tCO26g5FnIy44XyyON3SDFgX5nowmxGwZe81Gh7bBY5HJZXJ14NyqVkM2bsWJiLSubsL9pLe/TVaxYlt1JUZ/Ay2+kem0IP1BozRCTDXTAHfLnLvRSzDGPrPo43NwJYExIVUjFO+F71B6iyJL1w4qVwjLJJ38BFVJ34L2cU90reQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b6UoF1zGqtVrNRypomsBMEF/otGkLEyqVBmoP+knsu4=; b=kDn+Fn5LGAtk4hdiNnbHMurfzUdRrpdd6l0f22LukKSWwD8NWMCs3LnlmqfOcB1JQN33wUwQ53gbcr+++IdihiiVVdER8vbG2yhez0kR0nAnTUumeR+lmf0ift4t7ZJLxosQlD9HP6ZlLxQ5WFZSdQklhdTXVfxOKWAa7r+eGeU= Received: from MW3PR05CA0010.namprd05.prod.outlook.com (2603:10b6:303:2b::15) by CH3PR12MB8936.namprd12.prod.outlook.com (2603:10b6:610:179::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.16; Tue, 23 Jul 2024 13:25:45 +0000 Received: from CO1PEPF000044FC.namprd21.prod.outlook.com (2603:10b6:303:2b:cafe::ed) by MW3PR05CA0010.outlook.office365.com (2603:10b6:303:2b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.18 via Frontend Transport; Tue, 23 Jul 2024 13:25:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044FC.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.5 via Frontend Transport; Tue, 23 Jul 2024 13:25:44 +0000 Received: from amd-X570-AORUS-ELITE.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 23 Jul 2024 08:25:42 -0500 From: Arunpravin Paneer Selvam To: , , , CC: , , , , Arunpravin Paneer Selvam Subject: [PATCH v7 1/2] drm/buddy: Add start address support to trim function Date: Tue, 23 Jul 2024 18:55:24 +0530 Message-ID: <20240723132525.31294-1-Arunpravin.PaneerSelvam@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FC:EE_|CH3PR12MB8936:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d81a51e-9ccf-4841-d7f3-08dcab1af53c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?Tetp+coKccjOSinbTVWC1tuZeTnk2AY?= =?utf-8?q?bx6Qqk2Qaepu3mbByBv0die6rXw9LoysVlWqMC0nr2SecXeoMz17q0VlsHJp4e6CA?= =?utf-8?q?YlBROz7JD5Vjl1QJUWXhJ5jcIDH6AnLxgva+Xu+WJK2mHn3DRJ0dkZnNfquDov9S2?= =?utf-8?q?zFm6KbayEEEhNHaGjIZj6TnVsrcJSVQr15B/hnK5zVjBRjmhmXY16OSj3HasEiENw?= =?utf-8?q?xYhEn9ghVTn549au80DqF9/LB6LkyaFl7edbcySYYSh7ekG7laGMPXokEVXOB3ruM?= =?utf-8?q?gFPllhz57JDzYTus4DMOjpi9VsmHtfWxdiFZfplzPVcDnVPbachIjNynXhY35pqfO?= =?utf-8?q?CnNJCQ66DNwz/siOV77+TJ243GaziBvj6cceXJ6tjAtacejYtTAIHzoP4m+po/3DF?= =?utf-8?q?xF06uor+KQrqGM5jDiC9OGzN32RoSfyF/Ue0q7C0x0gTgNYokAKQ/WGTani1nRWhT?= =?utf-8?q?0WqtpUv6b/7Z4rD39Xt9D2SXRIdCqrIp3PWM0V3hmNvPRyps8ID2wWkJx2damMoK4?= =?utf-8?q?0wsHCciJbkpfWiSZkbc/rtwamdviJqumNRoo2+fjiUtd3pYQngmxitReCota7fxRa?= =?utf-8?q?8rtOE6hwY/ly0IJRRBrpIh7Npn7h/UFYkpvLjCiNVnx7XGTF0qCm5a0Og3IPVx1WA?= =?utf-8?q?cYdHiQtFj4ssJQ/ZVWBAIK8PsFl8Js2SsDJq+lsl7vXzuYhC1SCTP39kVlr/FHlJg?= =?utf-8?q?aucZo5ji5Z3NksS1X7bffD1VqwePuWDT24H6E3oEJrGF2CVZIyyiYazEhsldfgL8K?= =?utf-8?q?/O4UdWINxlpItFkcb+IGZnzjxKPwsKDRzfU2DhJ9im+/W0cRNIWeSz2yODSjG9kOb?= =?utf-8?q?Y/KxX+MriWylEXoHc2rVLaLjVNKvLRFdi21kZjOg/GsM7uLxW5rzig3TlKUSdj+9p?= =?utf-8?q?2PZhaSvNqjECpcikLUXe3W20aaTa+0EDrrpMlStqAEhhYeCeb8pF9RoecrYv1huaP?= =?utf-8?q?H6WnBvVfRAwfHoR65g0Ven+eInWiZwgKP5JeniEm9I8wIyBZQ8Pfm0yzkCoFWlj0l?= =?utf-8?q?KWjtRaY71bDB0o5wVPvvAQfgHCS+rqMmjoW17Wq10uO5CS4H6bI6520chawqEr1ki?= =?utf-8?q?laOv668+3aGMAnz/RxTYFv6kVu0TnoiXgTHh3j3kFrY3JSGniZ0wqHNW+Gb8f2284?= =?utf-8?q?jV3I9iC06PF0b6uLqqRq8o6g3ZiFT79pdOFePkm34B9WJiwCAr2HMchrxV5CIn8vM?= =?utf-8?q?Hcv1RuCw/rxt8QGlcI/11rs+TqpZVKKUUT23u+q9hsfNzrigbbI4G5gjT7jsFI7F9?= =?utf-8?q?7Lxb5vlNbcEiFoZ01lmTMJoI5qeLW4IZlAa9oxqwP52drxxYdbEo7Cthx+3SYaEy1?= =?utf-8?q?9UHjVVTfsKRkZ+p4N/116HEiPnDxgbxkmUQHpqW50Jc2vAbC8QuG9JduowyKaR6mR?= =?utf-8?q?HsqRjFJB74J?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 13:25:44.8860 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d81a51e-9ccf-4841-d7f3-08dcab1af53c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8936 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" - Add a new start parameter in trim function to specify exact address from where to start the trimming. This would help us in situations like if drivers would like to do address alignment for specific requirements. - Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this flag to disable the allocator trimming part. This patch enables the drivers control trimming and they can do it themselves based on the application requirements. v1:(Matthew) - check new_start alignment with min chunk_size - use range_overflows() Signed-off-by: Arunpravin Paneer Selvam Acked-by: Alex Deucher Acked-by: Christian König Reviewed-by: Matthew Auld --- drivers/gpu/drm/drm_buddy.c | 25 +++++++++++++++++++++++-- drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 2 +- include/drm/drm_buddy.h | 2 ++ 3 files changed, 26 insertions(+), 3 deletions(-) base-commit: b27d70e1042bf6a31ba7e5acf58b61c9cd28f95b diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index 6a8e45e9d0ec..103c185bb1c8 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -851,6 +851,7 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, * drm_buddy_block_trim - free unused pages * * @mm: DRM buddy manager + * @start: start address to begin the trimming. * @new_size: original size requested * @blocks: Input and output list of allocated blocks. * MUST contain single block as input to be trimmed. @@ -866,11 +867,13 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, * 0 on success, error code on failure. */ int drm_buddy_block_trim(struct drm_buddy *mm, + u64 *start, u64 new_size, struct list_head *blocks) { struct drm_buddy_block *parent; struct drm_buddy_block *block; + u64 block_start, block_end; LIST_HEAD(dfs); u64 new_start; int err; @@ -882,6 +885,9 @@ int drm_buddy_block_trim(struct drm_buddy *mm, struct drm_buddy_block, link); + block_start = drm_buddy_block_offset(block); + block_end = block_start + drm_buddy_block_size(mm, block); + if (WARN_ON(!drm_buddy_block_is_allocated(block))) return -EINVAL; @@ -894,6 +900,20 @@ int drm_buddy_block_trim(struct drm_buddy *mm, if (new_size == drm_buddy_block_size(mm, block)) return 0; + new_start = block_start; + if (start) { + new_start = *start; + + if (new_start < block_start) + return -EINVAL; + + if (!IS_ALIGNED(new_start, mm->chunk_size)) + return -EINVAL; + + if (range_overflows(new_start, new_size, block_end)) + return -EINVAL; + } + list_del(&block->link); mark_free(mm, block); mm->avail += drm_buddy_block_size(mm, block); @@ -904,7 +924,6 @@ int drm_buddy_block_trim(struct drm_buddy *mm, parent = block->parent; block->parent = NULL; - new_start = drm_buddy_block_offset(block); list_add(&block->tmp_link, &dfs); err = __alloc_range(mm, &dfs, new_start, new_size, blocks, NULL); if (err) { @@ -1066,7 +1085,8 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, } while (1); /* Trim the allocated block to the required size */ - if (original_size != size) { + if (!(flags & DRM_BUDDY_TRIM_DISABLE) && + original_size != size) { struct list_head *trim_list; LIST_HEAD(temp); u64 trim_size; @@ -1083,6 +1103,7 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, } drm_buddy_block_trim(mm, + NULL, trim_size, trim_list); diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c index fe3779fdba2c..423b261ea743 100644 --- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c +++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c @@ -150,7 +150,7 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man, } while (remaining_size); if (place->flags & TTM_PL_FLAG_CONTIGUOUS) { - if (!drm_buddy_block_trim(mm, vres->base.size, &vres->blocks)) + if (!drm_buddy_block_trim(mm, NULL, vres->base.size, &vres->blocks)) size = vres->base.size; } diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h index 2a74fa9d0ce5..9689a7c5dd36 100644 --- a/include/drm/drm_buddy.h +++ b/include/drm/drm_buddy.h @@ -27,6 +27,7 @@ #define DRM_BUDDY_CONTIGUOUS_ALLOCATION BIT(2) #define DRM_BUDDY_CLEAR_ALLOCATION BIT(3) #define DRM_BUDDY_CLEARED BIT(4) +#define DRM_BUDDY_TRIM_DISABLE BIT(5) struct drm_buddy_block { #define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) @@ -155,6 +156,7 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, unsigned long flags); int drm_buddy_block_trim(struct drm_buddy *mm, + u64 *start, u64 new_size, struct list_head *blocks); From patchwork Tue Jul 23 13:25:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Paneer Selvam, Arunpravin" X-Patchwork-Id: 13740001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86CD0C3DA70 for ; Tue, 23 Jul 2024 13:26:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7E9C10E5C6; Tue, 23 Jul 2024 13:26:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.b="o8z8NEwh"; dkim-atps=neutral Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2065.outbound.protection.outlook.com [40.107.100.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id DD8C910E5C6; Tue, 23 Jul 2024 13:25:51 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iNWr0v0e7262PsPIzi6w33gnJxU8TRIwZvgKTmJg2hHp2Fyay5vP0Pb5kDuYi2iTEyhBkdk2hs/L5QUhI43PyBTCed9tOfaQBFx8fYuWxuWA+KuCmHhnI02skD5RNxnz1w/y60tRiuddR7F7SvYRqyjcyxuvUb6JjOSDlmaHbZ+ahRet0SuTBm9PB11kkOkF1KtqwWYQhbD8nPN6Jo9BtmU+6wHycymsapDTxol0VYXez8Qr38netbauzH4RgXO0ES6rYlu3pqukyyxAg3oHgY8UU/DqwEJRqz08TktKYdrS4WsVwwlz9InmUNAQbfMLF7edjpKWkMcPNiVQl3YYDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EZCEu7Vf195YsZG39RAsGzWEbwU7TQLeZ6GI9mRDxgU=; b=AV5V+Hkr6nJ9QfujLQbhOP7EU4wETc3su39mrUx+j4ON0t2X4GY/sWa3BJdRjW9LOGLssIJzC94K0Pl4TixFgHgSQQnu63kP/TXwV/wCRW8uLa1lHU71uVka1FJnDeu6I1Z68LfHd2YD/2IxUqxxa/W8tkOkAOKKIgEr1LUHPETbDIpP94uBK5SMvwODcOyGwrFCFF1kP5SltKFc6WuZEkjwXxZdP5nJFfpMUkDXVMVmpfu8AcqRs87RXpvUHjr2NCa/dw2MHCJxhoj6LhTNRbSDdoIhEYpOkIEnUJqxiCkhEEF7c1rR9gwJapjK6Pb97fRDGBX40545YwD3hY0tjQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EZCEu7Vf195YsZG39RAsGzWEbwU7TQLeZ6GI9mRDxgU=; b=o8z8NEwhBJY5WhO02vFhbkW7s4CNXB6yj6Ij4nzaJUMhrh1NYw0xlubmC/Alljb5j1U3x7OLDMrdbx4DIRl2UxpVdSd3CU7l9AuBCE0FPJ1LZsjQf9Xe3sNsVX3Jxa8mXsvDUKIm5+3rMSLvXhcZciPsWm8aShHTLIbLpJ3KeKM= Received: from MW3PR06CA0015.namprd06.prod.outlook.com (2603:10b6:303:2a::20) by SN7PR12MB7251.namprd12.prod.outlook.com (2603:10b6:806:2ab::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7762.35; Tue, 23 Jul 2024 13:25:48 +0000 Received: from CO1PEPF000044F7.namprd21.prod.outlook.com (2603:10b6:303:2a:cafe::b1) by MW3PR06CA0015.outlook.office365.com (2603:10b6:303:2a::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.20 via Frontend Transport; Tue, 23 Jul 2024 13:25:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F7.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.5 via Frontend Transport; Tue, 23 Jul 2024 13:25:48 +0000 Received: from amd-X570-AORUS-ELITE.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 23 Jul 2024 08:25:44 -0500 From: Arunpravin Paneer Selvam To: , , , CC: , , , , Arunpravin Paneer Selvam , Frank Min Subject: [PATCH v7 2/2] drm/amdgpu: Add address alignment support to DCC buffers Date: Tue, 23 Jul 2024 18:55:25 +0530 Message-ID: <20240723132525.31294-2-Arunpravin.PaneerSelvam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240723132525.31294-1-Arunpravin.PaneerSelvam@amd.com> References: <20240723132525.31294-1-Arunpravin.PaneerSelvam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|SN7PR12MB7251:EE_ X-MS-Office365-Filtering-Correlation-Id: dde841cc-163e-46cc-4ab1-08dcab1af73d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?q?TKLmGT6s5zMplh0q0bsKJp68UA80k0m?= =?utf-8?q?Novd8R9/K4ZgSshK4RQlTzM6+FPmX28ZWrt/oW/7v6gLmOkRpDBsz8Ub3yJ3lKvaR?= =?utf-8?q?8GUdV6aYBpGl6jDNj/mY1tWD/Iejz2Ma7jyZ4zF2bjAnrZaPNJXyGqu1vxb9K4TTR?= =?utf-8?q?7YXo1XYbH7ds4zhn2JL55uVytTWoAivD9p+aUbwm4eNjjprzhc55e+Hmp0oQETd2j?= =?utf-8?q?QEJj28PIrsCvhWXuFs6uyhWqPcPE3rCXyIE35bvGD5jvT4Q1vL5VhLVJLE2hbQKou?= =?utf-8?q?ZVlDRrqgYuAVj2q7bIpTpnexP1jrE5IARbbNR/qfW9ZMKpVtZBBcpNGus/pdaVwIT?= =?utf-8?q?oFWcGTBfNOSyxJNVAVYqekaDKg0STv/uufRSlKTNXaT3LV+Tz7T8ne/8AYX3QSGmo?= =?utf-8?q?eEeja3QWq0DiCVoqOyvSvPFIF0YJ82Y5pzuAz1X0WVtfYZjpjmV2rVbsCPYqdphTA?= =?utf-8?q?m/btQhNwYuIrGlGpyibC7TVVcn7PFfLTS/+xSy8o92g4b4DsZL02mjRIcekpU0W9x?= =?utf-8?q?lXzOCwoUsQh7t+xCpkI08F09gEZt0n98wJ33O0O5EcHxm0CYGt+SpUZh3gyJCaj/C?= =?utf-8?q?S5adP58hv6JITifsHIgn6sXYHf25v9AFmfwyd6NRRD2Fg/mX0te2ofCUvF9Z50522?= =?utf-8?q?67jNa/k41UlWm47OFMWxQ+fWV+YRlO12cNEzXI0Xi4RX2Zjx5ZO3DzZB7j9cko8Ew?= =?utf-8?q?LX0gd5yJH5DoqbPCvtefN5cfXLDy8sy2p+mbUO36ObpUFrt6WHaXNjERHwMiQeeJr?= =?utf-8?q?JZdZtu50m+14oviGmbsmPNe6okgf4+oFCfdfcJJPSZwry1Jv5IZswKbV5z3xGXuhe?= =?utf-8?q?+ESL/kxeyHEedeqDlbxYgXogBGtkDNexFv2BtLupTbl0kPMt32CdOwLBvAxQ0t6PK?= =?utf-8?q?z2qU/6HkgNrucdSLbQBqb6dJmYoGlk+sZMSoCmtxyafk2Wq+M8AovRBDIuryvOp1p?= =?utf-8?q?IukiXKs+0oJpnYIyYyXP0JJAG3HWXfwRGEt7SQt2VYgCHq3SMpcw6BfUF/3AFseSL?= =?utf-8?q?N/JdFGRES4aKKFqwc6GJKY/XTgXY1SODXdpr3eGHp4eY2b3XWNQ6/pYR95/4MD/Gb?= =?utf-8?q?f26WgNAc5aPn+2lIUEnfUKl6QGhYiYFH2xun8hv06jlrHJP0zFlnELpUoYExg4H6o?= =?utf-8?q?sDN0UPQ8RqQTkD/uzB7zjHsnI2jBxWm/faWVoOKUGVV2BQ/vjsmmUDnToUAawR/NJ?= =?utf-8?q?dRC3yXy8KEyD3w7oEcbbDDyyXgUnEIycsECMdqaYqihorpF+Hrh6EuwrTQdaH5jAZ?= =?utf-8?q?iFQEuZrj4Wps00dL/fkwvjKm40OkYJfQwHTKnjl9lYD/W5AUUoA8ImzzCSAkssITz?= =?utf-8?q?wKVaw0MbPrgByEFn3h5exHMmwqD6C5HlNrmOKCeEQbQXSe7Apq1W4q+CNzFsBkwjq?= =?utf-8?q?p6jyGzutoDH?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 13:25:48.3381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dde841cc-163e-46cc-4ab1-08dcab1af73d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7251 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add address alignment support to the DCC VRAM buffers. v2: - adjust size based on the max_texture_channel_caches values only for GFX12 DCC buffers. - used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only for DCC buffers. - roundup non power of two DCC buffer adjusted size to nearest power of two number as the buddy allocator does not support non power of two alignments. This applies only to the contiguous DCC buffers. v3:(Alex) - rewrite the max texture channel caches comparison code in an algorithmic way to determine the alignment size. v4:(Alex) - Move the logic from amdgpu_vram_mgr_dcc_alignment() to gmc_v12_0.c and add a new gmc func callback for dcc alignment. If the callback is non-NULL, call it to get the alignment, otherwise, use the default. v5:(Alex) - Set the Alignment to a default value if the callback doesn't exist. - Add the callback to amdgpu_gmc_funcs. v6: - Fix checkpatch warning reported by Intel CI. v7:(Christian) - remove the AMDGPU_GEM_CREATE_GFX12_DCC flag and keep a flag that checks the BO pinning and for a specific hw generation. v8:(Christian) - move this check into gmc_v12_0_get_dcc_alignment. Signed-off-by: Arunpravin Paneer Selvam Acked-by: Alex Deucher Acked-by: Christian König Reviewed-by: Frank Min --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29 ++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 19 +++++++++++++ 3 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index febca3130497..654d0548a3f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -156,6 +156,8 @@ struct amdgpu_gmc_funcs { uint64_t addr, uint64_t *flags); /* get the amount of memory used by the vbios for pre-OS console */ unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); + /* get the DCC buffer alignment */ + u64 (*get_dcc_alignment)(struct amdgpu_device *adev); enum amdgpu_memory_partition (*query_mem_partition_mode)( struct amdgpu_device *adev); @@ -363,6 +365,10 @@ struct amdgpu_gmc { (adev)->gmc.gmc_funcs->override_vm_pte_flags \ ((adev), (vm), (addr), (pte_flags)) #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) +#define amdgpu_gmc_get_dcc_alignment(_adev) ({ \ + typeof(_adev) (adev) = (_adev); \ + ((adev)->gmc.gmc_funcs->get_dcc_alignment((adev))); \ +}) /** * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index f91cc149d06c..c6609f4ac3d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -450,12 +450,12 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, const struct ttm_place *place, struct ttm_resource **res) { + u64 size, remaining_size, lpfn, fpfn, adjust_dcc_size = 0; struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct amdgpu_device *adev = to_amdgpu_device(mgr); struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); u64 vis_usage = 0, max_bytes, min_block_size; struct amdgpu_vram_mgr_resource *vres; - u64 size, remaining_size, lpfn, fpfn; struct drm_buddy *mm = &mgr->mm; struct drm_buddy_block *block; unsigned long pages_per_block; @@ -511,7 +511,14 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, /* Allocate blocks in desired range */ vres->flags |= DRM_BUDDY_RANGE_ALLOCATION; + if (adev->gmc.gmc_funcs->get_dcc_alignment) + adjust_dcc_size = amdgpu_gmc_get_dcc_alignment(adev); + remaining_size = (u64)vres->base.size; + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) { + remaining_size = roundup_pow_of_two(remaining_size + adjust_dcc_size); + vres->flags |= DRM_BUDDY_TRIM_DISABLE; + } mutex_lock(&mgr->lock); while (remaining_size) { @@ -521,8 +528,11 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, min_block_size = mgr->default_page_size; size = remaining_size; - if ((size >= (u64)pages_per_block << PAGE_SHIFT) && - !(size & (((u64)pages_per_block << PAGE_SHIFT) - 1))) + + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) + min_block_size = size; + else if ((size >= (u64)pages_per_block << PAGE_SHIFT) && + !(size & (((u64)pages_per_block << PAGE_SHIFT) - 1))) min_block_size = (u64)pages_per_block << PAGE_SHIFT; BUG_ON(min_block_size < mm->chunk_size); @@ -553,6 +563,19 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, } mutex_unlock(&mgr->lock); + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) { + struct drm_buddy_block *dcc_block; + u64 dcc_start; + + dcc_block = amdgpu_vram_mgr_first_block(&vres->blocks); + /* Adjust the start address for DCC buffers only */ + dcc_start = + roundup(amdgpu_vram_mgr_block_start(dcc_block), adjust_dcc_size); + drm_buddy_block_trim(mm, &dcc_start, + (u64)vres->base.size, + &vres->blocks); + } + vres->base.start = 0; size = max_t(u64, amdgpu_vram_mgr_blocks_size(&vres->blocks), vres->base.size); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index fd3ac483760e..093f72eb6dfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -542,6 +542,24 @@ static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) return 0; } +static u64 gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) +{ + u64 max_tex_channel_caches, alignment; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && + amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) + return 0; + + max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; + if (is_power_of_2(max_tex_channel_caches)) + alignment = (max_tex_channel_caches / SZ_4) * max_tex_channel_caches; + else + alignment = roundup_pow_of_two(max_tex_channel_caches) * + max_tex_channel_caches; + + return (u64)alignment * SZ_1K; +} + static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, @@ -551,6 +569,7 @@ static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { .get_vm_pde = gmc_v12_0_get_vm_pde, .get_vm_pte = gmc_v12_0_get_vm_pte, .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, + .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, }; static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev)