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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00005FFC.mail.protection.outlook.com (10.167.243.228) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Tue, 23 Jul 2024 17:36:14 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 23 Jul 2024 12:36:11 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH 1/5] i3c: mipi-i3c-hci: Add MIPI0100 ACPI ID to the I3C Support List Date: Tue, 23 Jul 2024 23:05:34 +0530 Message-ID: <20240723173538.3493935-2-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> References: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00005FFC:EE_|MW5PR12MB5599:EE_ X-MS-Office365-Filtering-Correlation-Id: c6beedfd-f2a2-4667-9d4c-08dcab3df36e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 17:36:14.3672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6beedfd-f2a2-4667-9d4c-08dcab3df36e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5599 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240723_103625_457271_D45F4668 X-CRM114-Status: GOOD ( 12.31 ) X-Mailman-Approved-At: Tue, 23 Jul 2024 16:46:54 -0700 X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The current driver code lacks the necessary plumbing for ACPI IDs, preventing the mipi-i3c-hci driver from being loaded on x86 platforms that advertise I3C ACPI support. This update adds the MIPI0100 ACPI ID to the list of supported IDs. Signed-off-by: Shyam Sundar S K --- MIPI0100 is the ACPI ID as defined in the MIPI I3C DisCo specification. drivers/i3c/master/mipi-i3c-hci/core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index d7e966a25583..dbc8c38bd962 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -826,12 +826,18 @@ static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); +static const struct acpi_device_id i3c_hci_acpi_match[] = { + {"MIPI0100"}, + {} +}; + static struct platform_driver i3c_hci_driver = { .probe = i3c_hci_probe, .remove_new = i3c_hci_remove, .driver = { .name = "mipi-i3c-hci", .of_match_table = of_match_ptr(i3c_hci_of_match), + .acpi_match_table = i3c_hci_acpi_match, }, }; module_platform_driver(i3c_hci_driver); From patchwork Tue Jul 23 17:35:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 13740477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C693FC52CD8 for ; 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Tue, 23 Jul 2024 12:36:14 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH 2/5] i3c: mipi-i3c-hci: Add a quirk to set PIO mode Date: Tue, 23 Jul 2024 23:05:35 +0530 Message-ID: <20240723173538.3493935-3-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> References: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006002:EE_|SA3PR12MB8045:EE_ X-MS-Office365-Filtering-Correlation-Id: 106f0d17-761f-4c69-c49b-08dcab3df4cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: CO60OEqPNSBJhpX1v7jbkuuWj+QL1sGMF5WfiUBw8tGJZcuzCj52KlJepEUI12lqgmphNq9T0H6JxqHr2YoHooAquxEdUwoOB+29VM4R/1LfSM+OECkODSW4PRO3kothMqPmZH159rxdWZQtZZMpZxTNsERTg9Y28x0g2VpGsKb6J1inGluVa4hb+wOA2nBFs+edTLUiqkeF9XkzUu0fuyTb4nCrMy3jsg1mGa7PxPTz4xkNHO3kM2RbbnQ0c51YM6fLAQV+eqYy+ZT9+hDmMNnKeVDMIyNJuQUB3KGu7x5HWCckAoJfYu/i/iGr73snbL8Pij3MPmvQjDPwnds15YpvFCPk1xpXtj0lIuwHdOzY4MVhoO8Y+N8Y2iBgMfgj8BcrfjHIXCX3bH2+GpVi8IkIJrbzAToEPoyz3Md+woZ4TwHKQBLHDbXhY9DhOW+gwHuvigRsLEj04KiY+aZofOXz7gusa3+pPDb/yWdN8e3FErXD+4zk26B8Pg68WtkgIm0dO0abV8vphrZ21Sl4aRz9mA2QGPi45oC/QChMXhdOr9HEIPq+y34MmlawD1ld4JHu0MvMj0AFf695PvpWDt/Eq0JB9xr+OvlEtrIureFK2bJ0RxKoqNBQJ4FbdRjK9Y2AFOWDj8L6OYM6oc/fJMzYnQEuJoyUFPK8zOuV15IU2KRDaff6PhAd5R8tBIk7aPaQKOcOxfIgC/Hb/AuPYQkmSdw34OgLmEu3BKPnNtFk+xHrpPus6L/dr8jcOV/Pq/9jds9qP6G986P/IkroW7KhHb32U2UaRuhEd08FOC1+FWL3R1aGQ9bVkE9Nixb9kssg4dqwICoawWQ65q75YkX7HZXINXbie0+hUOVPzPtgL1khk75RAKsa2Z7V0wf6nGr0/ARIF1stvNyhV80hiVFJ4GdGCiZb1wPqo5uSRzMN0UiJjDAFBccsqXjgERbfR3MpvR5TwSngHH0aoMv8K91plVnIEF0WbsJOrV3J3wnu1lXW9uyg3LTA0989sVURw4aHsVhAQad0vNuGSANdXjvPB+EktdkpEp5k4YknRrzC2N12wjXBGsHxbYM26nQm8iKuJ5nz5cp7VFhIes4O5hztWFH4JLGlmhFsa+wp0SAUNZ7lPai84e+s2TFoNx6RKiywpM115n85EhAcov6tdm5LOWwGG9YVx5+DFKcDhN3QSXotkORi50spyxAjegNoljXQ5G1iJLk9pakAq7C7CKpNwEo5SxA8zkiSXzo37LXH1CF1bdmfsNJVwtXoETaXK+GL2umIoo1k02IYxi/KC6na9wrYvkV5JNNhdjTDY/e8Jdxwhm+4RU1uU5k20kV1tG4ieISnuFjXIOwYUormkvBeABDpWnGnx9n35oyczD8GwGKurPpqw5h9qf33Mw8RWAZ7bccDuZUJ8e5x33wIQTJ0tFmlx7Xl/9Ki109VHNFKQeWb1s5HXrqW3T6qa4/U X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 17:36:16.7465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 106f0d17-761f-4c69-c49b-08dcab3df4cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006002.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8045 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240723_103627_541632_EC3AF413 X-CRM114-Status: GOOD ( 17.46 ) X-Mailman-Approved-At: Tue, 23 Jul 2024 16:46:54 -0700 X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The AMD HCI controller currently only supports PIO mode but exposes DMA rings to the OS, which leads to the controller being configured in DMA mode. To address this, add a quirk to avoid configuring the controller in DMA mode and default to PIO mode. Additionally, introduce a generic quirk infrastructure to the mipi-i3c-hci driver to facilitate seamless future quirk additions. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/Makefile | 3 ++- drivers/i3c/master/mipi-i3c-hci/core.c | 15 ++++++++++++++- drivers/i3c/master/mipi-i3c-hci/hci.h | 3 +++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile index a658e7b8262c..1f8cd5c48fde 100644 --- a/drivers/i3c/master/mipi-i3c-hci/Makefile +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci.o mipi-i3c-hci-y := core.o ext_caps.o pio.o dma.o \ cmd_v1.o cmd_v2.o \ - dat_v1.o dct_v1.o + dat_v1.o dct_v1.o \ + hci_quirks.o diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index dbc8c38bd962..8bb422ab1d01 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -33,6 +33,7 @@ #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) #define HCI_VERSION 0x00 /* HCI Version (in BCD) */ +#define HCI_VERSION_V1 0x100 /* MIPI HCI Version number V1.0 */ #define HC_CONTROL 0x04 #define HC_CONTROL_BUS_ENABLE BIT(31) @@ -745,6 +746,14 @@ static int i3c_hci_init(struct i3c_hci *hci) return -EINVAL; } + /* Initialize quirks for AMD platforms */ + amd_i3c_hci_quirks_init(hci); + + regval = reg_read(HCI_VERSION); + + if (hci->quirks & HCI_QUIRK_AMD_PIO_MODE) + hci->RHS_regs = NULL; + /* Try activating DMA operations first */ if (hci->RHS_regs) { reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); @@ -760,7 +769,11 @@ static int i3c_hci_init(struct i3c_hci *hci) /* If no DMA, try PIO */ if (!hci->io && hci->PIO_regs) { reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); - if (!(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { + /* + * HC_CONTROL_PIO_MODE bit not present in HC_CONTROL register w.r.t V1.0 + * specification. So skip checking PIO_MODE bit status + */ + if (regval != HCI_VERSION_V1 && !(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { dev_err(&hci->master.dev, "DMA mode is stuck\n"); ret = -EIO; } else { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index f94d95e024be..046b65d43e63 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -135,6 +135,7 @@ struct i3c_hci_dev_data { /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ +#define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ /* global functions */ @@ -142,4 +143,6 @@ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); +void amd_i3c_hci_quirks_init(struct i3c_hci *hci); + #endif From patchwork Tue Jul 23 17:35:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 13740474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02211C3DA64 for ; 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Tue, 23 Jul 2024 12:36:16 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH 3/5] i3c: mipi-i3c-hci: Relocate helper macros to HCI header file Date: Tue, 23 Jul 2024 23:05:36 +0530 Message-ID: <20240723173538.3493935-4-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> References: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00005FFE:EE_|DS0PR12MB9448:EE_ X-MS-Office365-Filtering-Correlation-Id: b7355927-4f2d-4427-ce95-08dcab3df63f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: I+pNieW8Xjo+pGMav/dVwTECNIYWiBctUdxxv8AyTshUy0b/ibe54UibJrN7wFrQY2pLJ850UoopWnkvDH9DLrTBPg2ys8EkRjdYlenUg+cZsKM4K6qjJyQlCQtBh8f4gg2VjlH7JIwoeZRQgQYMESZtK4xTYTSSkSt56nVQJUXRgUgoztDxUQxSOMf6Lyu4g0TVZoQzBRjC2kWgzIuZLtNnam0UqPyVGLQR2KglwR7qiMQlYkr6emhJq4b3wMrvVO+qp3VldRxU7axNxsN7qnr6+aeuz+fA0SqEeTZxPhdwrC2oVrVBNc+cDVuy6uXUfyALyzvW+6WkLRf5J8xzKLfb8fVD1skNUbu6FsfV7lZnKan/vDeZFqIrbjKi3HWgZl/KZGu2z6jOIDQQIxkYIpoObzkRa6BxFXUSpimlsauxChYzfXb4d9Q1LgxwWHyVIxGL0KocrYNw2H99AABkprbqrrAl/1uQbdYldeJMswlqOYLepffjr7GJKnwiLR+oTOQDgEAZSsvlZynl0Sr1AkblOQnKzfBmwk49t6xMoT8JMcVVEwsFIDDdkgoskASidDFZEpM2l3LWLSQAltyVn+9R+6768YK4uuSrDdcgkeIlGV51Y9LijhheAFAEI4pZWBZPaEDkY9szmUFfyEpdUhvUCmo9JrjnG6X1EMgWuKiDslmRAEYpY8aAB4h7rqKsnLU+dx6xdpE4QraZMEKezNUK7ztnaMTWfhslRnqFFOec8nOsyUmRZEBh132P+cZe8DfGelzrdROftmNy3srLlO5UBTQcq+PXpUeGIdBrRDqyG+K8EB20/MeM4K0V9tUacW5gbeBM1PrjnpUUWY4PCrXuBUhXVJKweIXQA/mWh6D1CPB8shKZhCamrka7zjXAVFO7YxA0iRTrRil8UBy45XjmggjQGviacw5IPtNSStE7bIXmDuI9P1nRxEwIoaI9dShIDxC5BJ/NbwsK5sPbHGezHIwIC2Nq649LFnirfuzoszSuAipfB6DnXYyE+WmrMSlk66xgdB+2m0XFWTOuDAaLbIp0VCCUJCttglGDBDqSSC5Jh9UX/WVJYqOw0wIM5I3lokASlrBPLJxafxzb9F1PPAcDYu0052SpXAdBtfupVjkmjNiJrGeE1Tk/ytUH3XOMStY7g+J5c/fGOVpKPVqcJP0psc6iWxwnep8DXafrR5oQLdhq/KbL3VoKnlZvhdNQMJ/ESRlI2blMdkqqM6+Br1Z5wJKLQaZlzcG7ap5mYSHPi+JFflZOVYC/25FI3fgAwSvKUXLjf5ijUyZoCY3iu76yLPwI5+oCPwW4LABrdiI7DLyXUlyJmnA6xsBxbS6hZ/KPW8ghdtgDxazgWEtyLzlH7FmBM17E3RMxRKxLs5QllR0s6joyvLX7JDhZfKescCFmbQo7V7qG1c/WYMCO8n+LQltx/K8d1OjoCcMg4ErTbdQ0TkwN/hvn1Fqt X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 17:36:19.1874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7355927-4f2d-4427-ce95-08dcab3df63f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9448 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240723_103625_370948_CF7332A4 X-CRM114-Status: GOOD ( 10.18 ) X-Mailman-Approved-At: Tue, 23 Jul 2024 16:46:54 -0700 X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The reg_* helper macros are currently limited to core.c. Moving them to hci.h will allow their functionality to be utilized in other files outside of core.c. Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 5 ----- drivers/i3c/master/mipi-i3c-hci/hci.h | 4 ++++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index 8bb422ab1d01..ae5b1a144506 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -27,11 +27,6 @@ * Host Controller Capabilities and Operation Registers */ -#define reg_read(r) readl(hci->base_regs + (r)) -#define reg_write(r, v) writel(v, hci->base_regs + (r)) -#define reg_set(r, v) reg_write(r, reg_read(r) | (v)) -#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) - #define HCI_VERSION 0x00 /* HCI Version (in BCD) */ #define HCI_VERSION_V1 0x100 /* MIPI HCI Version number V1.0 */ diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index 046b65d43e63..56361adbcc14 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -26,6 +26,10 @@ #define W2_BIT_(x) BIT((x) - 64) #define W3_BIT_(x) BIT((x) - 96) +#define reg_read(r) readl(hci->base_regs + (r)) +#define reg_write(r, v) writel(v, hci->base_regs + (r)) +#define reg_set(r, v) reg_write(r, reg_read(r) | (v)) +#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) struct hci_cmd_ops; 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To address this, a quirk is added to configure the clock rate to 9 MHz as a workaround, with proportional adjustments to the Open-Drain (OD) and Push-Pull (PP) values. Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 4 ++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 + drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 41 ++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index ae5b1a144506..9fc142ca7532 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -784,6 +784,10 @@ static int i3c_hci_init(struct i3c_hci *hci) return ret; } + /* Configure OD and PP timings for AMD platforms */ + if (hci->quirks & HCI_QUIRK_AMD_OD_PP_TIMING) + amd_set_od_pp_timing(hci); + return 0; } diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index 56361adbcc14..f4ec6dcb2ecf 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -140,6 +140,7 @@ struct i3c_hci_dev_data { /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ +#define HCI_QUIRK_AMD_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ /* global functions */ @@ -148,5 +149,6 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_i3c_hci_quirks_init(struct i3c_hci *hci); +void amd_set_od_pp_timing(struct i3c_hci *hci); #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c new file mode 100644 index 000000000000..9d8c5eedc8cc --- /dev/null +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD SOC I3C HCI quirks + * + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Authors: Shyam Sundar S K + * Guruvendra Punugupati + */ + +#include +#include "hci.h" + +/* Timing registers */ +#define HCI_SCL_I3C_OD_TIMING 0x214 +#define HCI_SCL_I3C_PP_TIMING 0x218 +#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230 + +/* Timing values to configure 9MHz frequency */ +#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf +#define AMD_SCL_I3C_PP_TIMING 0x00160016 + +void amd_i3c_hci_quirks_init(struct i3c_hci *hci) +{ + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { + hci->quirks |= HCI_QUIRK_AMD_PIO_MODE; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 17:36:24.0741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d264888-4d9e-4d22-d84d-08dcab3df92b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9107 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240723_103632_676357_2583CFC3 X-CRM114-Status: GOOD ( 14.05 ) X-Mailman-Approved-At: Tue, 23 Jul 2024 16:46:54 -0700 X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The current driver sets the response buffer threshold value to 1 (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD I3C controller only generates interrupts when the response buffer threshold value is set to 0 (1 DWORD). Therefore, a quirk is added to set the response buffer threshold value to 0. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 4 ++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 12 ++++++++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index 9fc142ca7532..2da00a5b590b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -148,6 +148,10 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m) if (ret) return ret; + /* Set RESP_BUF_THLD to 0(n) to get 1(n+1) response */ + if (hci->quirks & HCI_QUIRK_AMD_RESP_BUF_THLD) + amd_set_resp_buf_thld(hci); + reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL)); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index f4ec6dcb2ecf..07b90a68ec5e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -141,6 +141,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ #define HCI_QUIRK_AMD_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ +#define HCI_QUIRK_AMD_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ /* global functions */ @@ -150,5 +151,6 @@ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_i3c_hci_quirks_init(struct i3c_hci *hci); void amd_set_od_pp_timing(struct i3c_hci *hci); +void amd_set_resp_buf_thld(struct i3c_hci *hci); #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c index 9d8c5eedc8cc..503c81c504f1 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c @@ -20,11 +20,14 @@ #define AMD_SCL_I3C_OD_TIMING 0x00cf00cf #define AMD_SCL_I3C_PP_TIMING 0x00160016 +#define QUEUE_THLD_CTRL 0xD0 + void amd_i3c_hci_quirks_init(struct i3c_hci *hci) { if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { hci->quirks |= HCI_QUIRK_AMD_PIO_MODE; hci->quirks |= HCI_QUIRK_AMD_OD_PP_TIMING; + hci->quirks |= HCI_QUIRK_AMD_RESP_BUF_THLD; } } @@ -39,3 +42,12 @@ void amd_set_od_pp_timing(struct i3c_hci *hci) data |= W0_MASK(18, 16); reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data); } + +void amd_set_resp_buf_thld(struct i3c_hci *hci) +{ + u32 data; + + data = reg_read(QUEUE_THLD_CTRL); + data = data & ~W0_MASK(15, 8); + reg_write(QUEUE_THLD_CTRL, data); +}