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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2024 07:13:24.0325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e55ff4f-6f96-48d0-d149-08dcabb01b63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8773 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240724_001333_256157_E3447F0F X-CRM114-Status: GOOD ( 13.36 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The current driver code lacks the necessary plumbing for ACPI IDs, preventing the mipi-i3c-hci driver from being loaded on x86 platforms that advertise I3C ACPI support. This update adds the MIPI0100 ACPI ID to the list of supported IDs. Signed-off-by: Shyam Sundar S K --- MIPI0100 is the ACPI ID as defined in the MIPI I3C DisCo specification. drivers/i3c/master/mipi-i3c-hci/core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index d7e966a25583..dbc8c38bd962 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -826,12 +826,18 @@ static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); +static const struct acpi_device_id i3c_hci_acpi_match[] = { + {"MIPI0100"}, + {} +}; + static struct platform_driver i3c_hci_driver = { .probe = i3c_hci_probe, .remove_new = i3c_hci_remove, .driver = { .name = "mipi-i3c-hci", .of_match_table = of_match_ptr(i3c_hci_of_match), + .acpi_match_table = i3c_hci_acpi_match, }, }; module_platform_driver(i3c_hci_driver); From patchwork Wed Jul 24 07:12:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 13740631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D743BC3DA61 for ; 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Wed, 24 Jul 2024 02:13:23 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH v2 2/5] i3c: mipi-i3c-hci: Add a quirk to set PIO mode Date: Wed, 24 Jul 2024 12:42:42 +0530 Message-ID: <20240724071245.3833404-3-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240724071245.3833404-1-Shyam-sundar.S-k@amd.com> References: <20240724071245.3833404-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D4:EE_|CH3PR12MB8457:EE_ X-MS-Office365-Filtering-Correlation-Id: bb992048-68c9-4448-162d-08dcabb01d4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: VJBMgBf1R/dEFLY/chanA4yoRH4Xgiib3/eLejmEjqybDxVWsRh5cgXgSjEttK2yuDn7Cv/amU52z73HuZEcLgw9MnDJQN6fTZU1xlpbqVyFpLTH4MxR3qqoTpXIINTzm+16qMB2P/COHKmgdcTCPNCAzfpvMcBj4VI3Kq0f4MN/vHRgLl6LoTwAhUO3vCmNRXO5YFKh7s/1DLFo31bTkHI0hjioy4HZPeV4N1MV4hFomdVp8FHgVOIuutG1+eyEpXi8WCrue0xbZUvi37FnbgNwuMJhw/8VhjCalcvCmZEzqJkVbA4yRfJwExVI06zooVi2nP5cPEp7LFBGIqkxIhFTdIcxQAYG/Ijh/BfcELh96eeJ/OLS99aBKFM3bdZy10GbJYrMOfeqXdjWYGZGh6CVFDqHp04k80vZdB9kT5d9ivZKlXPkcukzaNLSXz/Lpm1MraOmyWgbggSQgi3vxPVSzGvoarnJ8KdtDxri65oj9flEQbF6fBWpyNuFRoDQVqcnVDG2ZTEB3Ojj/vUNCWP0/3FJpECXVwDwd3+Qdl7dx+uPFY2KxAomIAysqgpHGRRfZgQZpwibNjDef8jJjlr1TlrT/sCnQQEpbJOOeUUcgBg4AQ8Iah+25aWdHi2dWwDb4Y4ANafJeY1cC99KFy12dPwVc9qr+d7kV7+OqeYX7+uhQJ6lIPsD5Gc6+UFHZI6Jj8sntbfyc+ox2jSk0VKTt/XvzXleQy1WVHk98A6otC9SvYJBjEtH9iwgrIbSOY08Mea6mHebIcFmZqAKbelfUQi14ZSmyjNYtW3ISnu1vcxBswGUWqoLNAeE0qZpBDaIN4t+nNmz1yQeZZjgKF6UpIROeta0KDHkmo8XlSr91oFZ3k5JzQ/Xv6KxERkaqiHm4uRSFiAosMbaA400MQRyp1wg1eWgshfnTrNXK+Xe8XuAluZtD83FQ0w9Mp0AA42u7nk0Igj1+1hc7PzMlHeT8UDGNPsDFq+8mHUOKpvdQDOXNKZCl6hsG4o+AdxdbucWgUFlSMyT2ahrxywo8bEFWjZlPuBicxpwYK3+beCcQxyn5vNcmqJ+hX9OStUaIz/h+vSHJWGdWacZOFIVsojXLV626qHk30zF185cCi9DMopnXq4h4A4ma5kuE7h4UIRFZ+80BIS0ExX8fNMQC5HjhTSSaMTdL2SDFJPFtmI5NvaZ16r4zZQXHHu2p1rC+IcjLCGl8PSkGRNi9DPSYfvdPckoTi5zRrrrn3vrMZ6LmRwaJ9n84un5Am+UkbL/JMJJ8hHwkNWcPUOAxmiQs3CgJC6/xgqHN5SZ56RQsPGZr54/pYPFywlEc8Hk0lwujW2m3P5SEZ5moY9roGWKiZULWjjqAAkwLumTdPORlTZZ+UWxHwr49Xj4zffWQ8nkYM51PH6tpF59KMX2pN4TQVTVmmmf1CE1n+c9Co1lOthI8MEn0YvpUHCr95yx/p7E X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2024 07:13:27.2390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb992048-68c9-4448-162d-08dcabb01d4d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8457 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240724_001332_535919_6BCED09E X-CRM114-Status: GOOD ( 18.53 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The AMD HCI controller currently only supports PIO mode but exposes DMA rings to the OS, which leads to the controller being configured in DMA mode. To address this, add a quirk to avoid configuring the controller in DMA mode and default to PIO mode. Additionally, introduce a generic quirk infrastructure to the mipi-i3c-hci driver to facilitate seamless future quirk additions. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/Makefile | 3 ++- drivers/i3c/master/mipi-i3c-hci/core.c | 15 ++++++++++++++- drivers/i3c/master/mipi-i3c-hci/hci.h | 3 +++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile index a658e7b8262c..1f8cd5c48fde 100644 --- a/drivers/i3c/master/mipi-i3c-hci/Makefile +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci.o mipi-i3c-hci-y := core.o ext_caps.o pio.o dma.o \ cmd_v1.o cmd_v2.o \ - dat_v1.o dct_v1.o + dat_v1.o dct_v1.o \ + hci_quirks.o diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index dbc8c38bd962..8bb422ab1d01 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -33,6 +33,7 @@ #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) #define HCI_VERSION 0x00 /* HCI Version (in BCD) */ +#define HCI_VERSION_V1 0x100 /* MIPI HCI Version number V1.0 */ #define HC_CONTROL 0x04 #define HC_CONTROL_BUS_ENABLE BIT(31) @@ -745,6 +746,14 @@ static int i3c_hci_init(struct i3c_hci *hci) return -EINVAL; } + /* Initialize quirks for AMD platforms */ + amd_i3c_hci_quirks_init(hci); + + regval = reg_read(HCI_VERSION); + + if (hci->quirks & HCI_QUIRK_AMD_PIO_MODE) + hci->RHS_regs = NULL; + /* Try activating DMA operations first */ if (hci->RHS_regs) { reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); @@ -760,7 +769,11 @@ static int i3c_hci_init(struct i3c_hci *hci) /* If no DMA, try PIO */ if (!hci->io && hci->PIO_regs) { reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); - if (!(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { + /* + * HC_CONTROL_PIO_MODE bit not present in HC_CONTROL register w.r.t V1.0 + * specification. So skip checking PIO_MODE bit status + */ + if (regval != HCI_VERSION_V1 && !(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { dev_err(&hci->master.dev, "DMA mode is stuck\n"); ret = -EIO; } else { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index f94d95e024be..046b65d43e63 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -135,6 +135,7 @@ struct i3c_hci_dev_data { /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ +#define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ /* global functions */ @@ -142,4 +143,6 @@ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); +void amd_i3c_hci_quirks_init(struct i3c_hci *hci); + #endif From patchwork Wed Jul 24 07:12:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 13740633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B66C0C3DA70 for ; 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Wed, 24 Jul 2024 02:13:26 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH v2 3/5] i3c: mipi-i3c-hci: Relocate helper macros to HCI header file Date: Wed, 24 Jul 2024 12:42:43 +0530 Message-ID: <20240724071245.3833404-4-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240724071245.3833404-1-Shyam-sundar.S-k@amd.com> References: <20240724071245.3833404-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D2:EE_|CH3PR12MB8512:EE_ X-MS-Office365-Filtering-Correlation-Id: 90ebb878-3235-4f9c-b86c-08dcabb01e7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2024 07:13:29.2485 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90ebb878-3235-4f9c-b86c-08dcabb01e7f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8512 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240724_001336_107874_0CB72456 X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The reg_* helper macros are currently limited to core.c. Moving them to hci.h will allow their functionality to be utilized in other files outside of core.c. Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 6 ------ drivers/i3c/master/mipi-i3c-hci/hci.h | 5 +++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index 8bb422ab1d01..ca9d4e2c80e6 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -27,11 +26,6 @@ * Host Controller Capabilities and Operation Registers */ -#define reg_read(r) readl(hci->base_regs + (r)) -#define reg_write(r, v) writel(v, hci->base_regs + (r)) -#define reg_set(r, v) reg_write(r, reg_read(r) | (v)) -#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) - #define HCI_VERSION 0x00 /* HCI Version (in BCD) */ #define HCI_VERSION_V1 0x100 /* MIPI HCI Version number V1.0 */ diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index 046b65d43e63..8e5af4e55de1 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -10,6 +10,7 @@ #ifndef HCI_H #define HCI_H +#include /* Handy logging macro to save on line length */ #define DBG(x, ...) pr_devel("%s: " x "\n", __func__, ##__VA_ARGS__) @@ -26,6 +27,10 @@ #define W2_BIT_(x) BIT((x) - 64) #define W3_BIT_(x) BIT((x) - 96) +#define reg_read(r) readl(hci->base_regs + (r)) +#define reg_write(r, v) writel(v, hci->base_regs + (r)) +#define reg_set(r, v) reg_write(r, reg_read(r) | (v)) +#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) struct hci_cmd_ops; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2024 07:13:32.2930 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b9eb17d-80ec-4f67-300f-08dcabb0205c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7114 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240724_001338_113094_223367C4 X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The AMD HCI controller is currently unstable at 12.5 MHz. To address this, a quirk is added to configure the clock rate to 9 MHz as a workaround, with proportional adjustments to the Open-Drain (OD) and Push-Pull (PP) values. Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 4 ++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 + drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 43 ++++++++++++++++++++ 3 files changed, 49 insertions(+) create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index ca9d4e2c80e6..3320e6331c86 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -783,6 +783,10 @@ static int i3c_hci_init(struct i3c_hci *hci) return ret; } + /* Configure OD and PP timings for AMD platforms */ + if (hci->quirks & HCI_QUIRK_AMD_OD_PP_TIMING) + amd_set_od_pp_timing(hci); + return 0; } diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index 8e5af4e55de1..06a4d54a5a02 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -141,6 +141,7 @@ struct i3c_hci_dev_data { /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ +#define HCI_QUIRK_AMD_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ /* global functions */ @@ -149,5 +150,6 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_i3c_hci_quirks_init(struct i3c_hci *hci); +void amd_set_od_pp_timing(struct i3c_hci *hci); #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c new file mode 100644 index 000000000000..6ce08f9c92a8 --- /dev/null +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * I3C HCI quirks + * + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Authors: Shyam Sundar S K + * Guruvendra Punugupati + */ + +#include +#include "hci.h" + +/* Timing registers */ +#define HCI_SCL_I3C_OD_TIMING 0x214 +#define HCI_SCL_I3C_PP_TIMING 0x218 +#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230 + +/* Timing values to configure 9MHz frequency */ +#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf +#define AMD_SCL_I3C_PP_TIMING 0x00160016 + +void amd_i3c_hci_quirks_init(struct i3c_hci *hci) +{ +#if defined(CONFIG_X86) + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { + hci->quirks |= HCI_QUIRK_AMD_PIO_MODE; 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Wed, 24 Jul 2024 07:13:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D1.mail.protection.outlook.com (10.167.242.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Wed, 24 Jul 2024 07:13:35 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 24 Jul 2024 02:13:31 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH v2 5/5] i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold Date: Wed, 24 Jul 2024 12:42:45 +0530 Message-ID: <20240724071245.3833404-6-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240724071245.3833404-1-Shyam-sundar.S-k@amd.com> References: <20240724071245.3833404-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D1:EE_|IA0PR12MB8931:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d07a187-95d6-4136-1ea8-08dcabb021ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2024 07:13:35.0274 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d07a187-95d6-4136-1ea8-08dcabb021ef X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8931 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240724_001341_372803_77B593B8 X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The current driver sets the response buffer threshold value to 1 (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD I3C controller only generates interrupts when the response buffer threshold value is set to 0 (1 DWORD). Therefore, a quirk is added to set the response buffer threshold value to 0. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 4 ++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 12 ++++++++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index 3320e6331c86..eef5059177f1 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -147,6 +147,10 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m) if (ret) return ret; + /* Set RESP_BUF_THLD to 0(n) to get 1(n+1) response */ + if (hci->quirks & HCI_QUIRK_AMD_RESP_BUF_THLD) + amd_set_resp_buf_thld(hci); + reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL)); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index 06a4d54a5a02..58c3643c6390 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -142,6 +142,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ #define HCI_QUIRK_AMD_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ +#define HCI_QUIRK_AMD_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ /* global functions */ @@ -151,5 +152,6 @@ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_i3c_hci_quirks_init(struct i3c_hci *hci); void amd_set_od_pp_timing(struct i3c_hci *hci); +void amd_set_resp_buf_thld(struct i3c_hci *hci); #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c index 6ce08f9c92a8..954cba95e4a4 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c @@ -20,12 +20,15 @@ #define AMD_SCL_I3C_OD_TIMING 0x00cf00cf #define AMD_SCL_I3C_PP_TIMING 0x00160016 +#define QUEUE_THLD_CTRL 0xD0 + void amd_i3c_hci_quirks_init(struct i3c_hci *hci) { #if defined(CONFIG_X86) if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { hci->quirks |= HCI_QUIRK_AMD_PIO_MODE; hci->quirks |= HCI_QUIRK_AMD_OD_PP_TIMING; + hci->quirks |= HCI_QUIRK_AMD_RESP_BUF_THLD; } #endif } @@ -41,3 +44,12 @@ void amd_set_od_pp_timing(struct i3c_hci *hci) data |= W0_MASK(18, 16); reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data); } + +void amd_set_resp_buf_thld(struct i3c_hci *hci) +{ + u32 data; + + data = reg_read(QUEUE_THLD_CTRL); + data = data & ~W0_MASK(15, 8); + reg_write(QUEUE_THLD_CTRL, data); +}