From patchwork Thu Jul 25 10:45:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13741788 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B351E481A3; Thu, 25 Jul 2024 10:45:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904359; cv=none; b=RiPzNcAhGKwVFnRbayoRe6eDsFiFlxd8jMNbnVofTOyadPMJ327i6bbBeHhr3v1MQdyNDRpO86jia3uitF5bKvxwAg9tuEnW3SBFuuHMzXitmkba/aKr8WCJcVBhRNkg9GkWcVIga/lSF3tChYZphYV+rpQrelkiUvTfdk1QL8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904359; c=relaxed/simple; bh=Eqol7SL4+cxSJ2trAoS3fL1wCu/dWzgRAa0+jTTQMhU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KFbyrYq2fZv6roEZVvUBujtrcYka90B4a/I2ANtFztpoARJLOT71yCmN2/Lzd9S2nOzvHn8NGGSNx2/6lMW5/qOEpF6/srKKCNulpL8lf68RaPXoXbrU7l5XAQ0pGY1oOozqO4DZ1/Tx2DTo+KWelK2ofUtuZ6CbfPQLccrySM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DOM1qhEl; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DOM1qhEl" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46PA1UbZ019617; Thu, 25 Jul 2024 10:45:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= rUuWtYFiSTkqR8yKMC3h9SpZYDS1Z7yhQqO5LoflbCE=; b=DOM1qhElaj7AOq2u tP1r50dGGzjL6IvwhOEYnNiBVYxduPbu5rwrWIGsSNXx3NhIukFVWqNdLA1VOBfl NDhAVC8gsDfrzOMmh2xqCTYgozdzxXG44Dg9BIkQicxWvpXcIpOfTQeyVi7J/GAp p39KXAP9HhlgD9yZhUdzv9zl0STirEQ1YQnl/5Bz7cFYIJG2ztjMxwGe1O4clNJL 9pHvl8ohgg1ij9kFHBjuzVp0rZLe5ONAgqz5INeDwmszYor2Ux49akX64h2J8IbP i9nWPak7hur3Rzc63jXv+ZCeGlw6D4VvvTUisBU/KiTh/cwGZJlD52cKMsxhGFpj UlAigA== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40g487mvgp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:45:53 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46PAjpwf007671 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:45:51 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 25 Jul 2024 03:45:46 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan , Krzysztof Kozlowski Subject: [PATCH v5 1/5] dt-bindings: interconnect: Add Qualcomm IPQ5332 support Date: Thu, 25 Jul 2024 16:15:24 +0530 Message-ID: <20240725104528.3504967-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725104528.3504967-1-quic_varada@quicinc.com> References: <20240725104528.3504967-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mnRTQ4zLtfhEYHG7e4TEFbvmmzVqARAH X-Proofpoint-GUID: mnRTQ4zLtfhEYHG7e4TEFbvmmzVqARAH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_11,2024-07-25_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250073 Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ5332 Network-On-Chip interfaces. This will be used by the gcc-ipq5332 driver for providing interconnect services using the icc-clk framework. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v4: Add Reviewed-By: Krzysztof v3: Not taking Reviewed-By: Krzysztof, fixed copy paste error INTERCONNECT_QCOM_IPQ9574_H -> INTERCONNECT_QCOM_IPQ5332_H --- .../bindings/clock/qcom,ipq5332-gcc.yaml | 2 + .../dt-bindings/interconnect/qcom,ipq5332.h | 46 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,ipq5332.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index adc30d84fa8f..9193de681de2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -31,6 +31,8 @@ properties: - description: USB PCIE wrapper pipe clock source '#power-domain-cells': false + '#interconnect-cells': + const: 1 required: - compatible diff --git a/include/dt-bindings/interconnect/qcom,ipq5332.h b/include/dt-bindings/interconnect/qcom,ipq5332.h new file mode 100644 index 000000000000..16475bb07a48 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq5332.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ5332_H +#define INTERCONNECT_QCOM_IPQ5332_H + +#define MASTER_SNOC_PCIE3_1_M 0 +#define SLAVE_SNOC_PCIE3_1_M 1 +#define MASTER_ANOC_PCIE3_1_S 2 +#define SLAVE_ANOC_PCIE3_1_S 3 +#define MASTER_SNOC_PCIE3_2_M 4 +#define SLAVE_SNOC_PCIE3_2_M 5 +#define MASTER_ANOC_PCIE3_2_S 6 +#define SLAVE_ANOC_PCIE3_2_S 7 +#define MASTER_SNOC_USB 8 +#define SLAVE_SNOC_USB 9 +#define MASTER_NSSNOC_NSSCC 10 +#define SLAVE_NSSNOC_NSSCC 11 +#define MASTER_NSSNOC_SNOC_0 12 +#define SLAVE_NSSNOC_SNOC_0 13 +#define MASTER_NSSNOC_SNOC_1 14 +#define SLAVE_NSSNOC_SNOC_1 15 +#define MASTER_NSSNOC_ATB 16 +#define SLAVE_NSSNOC_ATB 17 +#define MASTER_NSSNOC_PCNOC_1 18 +#define SLAVE_NSSNOC_PCNOC_1 19 +#define MASTER_NSSNOC_QOSGEN_REF 20 +#define SLAVE_NSSNOC_QOSGEN_REF 21 +#define MASTER_NSSNOC_TIMEOUT_REF 22 +#define SLAVE_NSSNOC_TIMEOUT_REF 23 +#define MASTER_NSSNOC_XO_DCD 24 +#define SLAVE_NSSNOC_XO_DCD 25 + +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_CE_APB 6 +#define SLAVE_NSSNOC_CE_APB 7 +#define MASTER_NSSNOC_CE_AXI 8 +#define SLAVE_NSSNOC_CE_AXI 9 + +#define MASTER_CNOC_AHB 0 +#define SLAVE_CNOC_AHB 1 + +#endif /* INTERCONNECT_QCOM_IPQ5332_H */ From patchwork Thu Jul 25 10:45:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13741789 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22D2C481A3; Thu, 25 Jul 2024 10:46:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904364; cv=none; b=SEIe+bAiUrHCbKaKNbDx7Kf4Y/pzy7Ax79Ddv+rADi6TxA5N4E/wvjP8TJnjdycc/gtoLWibRF3lOTdf6xjacxhn9tN6NEedn1LGL5MOEgVKq0dFldwEaQWZZmW3LTl5FDBsm6KQwNizk2jZshYtgmYPi8qcJFLlMG+n38R0Ins= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904364; c=relaxed/simple; bh=X7SdgXP+Ykz0MNqMNEuIqRMBWfWQgWTopkdn4v2pSdY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YHLjdZjRwbkFLBN6lo8M1YQjPi7SoTmJmUUkw5+L/PAMsH205kCAoYxtf0wZf2TB7Y/2qRI15Q41d2U5G1XOxKkgqvlKiTzE8Zm2zuTaVK99JIVpEs0P3dxJu81GW9OcrHX0N9wo0BTs/XjrfmQDvz/ZtCBEKd0oPJcYIGHifH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Q8n8TJmp; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Q8n8TJmp" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46P7fZxe032510; Thu, 25 Jul 2024 10:45:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4DV1+yzPyU5o2ZWOQBgmNNOYk8keWOYIv4AoxwjIA2E=; b=Q8n8TJmpanxsLyWD +xk0zdjo7gG8rmLI90J/USjI5csOyYI2ntlU8VR2gRaNUs9N+EYDANT02I+whpWA iaUACJOGBONYUE2Yn7MFWI3k6S4hjIpopIFLXGPc51ZaGJiDTqVN8rPffMcXwSro WrqAwdvC86vkYRNBqSmj5cuq6uGCZlHoyZ+vMkdhLd3VIFm4G+qHnpC0DbbaLEAU QeS1NSeYiy0MIOFO8tM9MbzxxGBxiD+Nnb5G6WIDSt10beoAGlAav2I+Db3RmD4/ Qa3xnSBG2eCAD+seFaDuhWSDPJk3Me6qHellOMrh4+jzqFbByO6EJw5/GkudBsHY 21PX2A== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40k5nvt6wc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:45:57 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46PAjvpV004213 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:45:57 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 25 Jul 2024 03:45:51 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v5 2/5] dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details Date: Thu, 25 Jul 2024 16:15:25 +0530 Message-ID: <20240725104528.3504967-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725104528.3504967-1-quic_varada@quicinc.com> References: <20240725104528.3504967-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: y1TCRerbHuvHj5QVKmJ5uUvlu29EZ8G8 X-Proofpoint-ORIG-GUID: y1TCRerbHuvHj5QVKmJ5uUvlu29EZ8G8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_11,2024-07-25_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 clxscore=1015 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 phishscore=0 mlxlogscore=757 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250072 USB uses icc-clk framework to enable the NoC interface clock. Hence the 'iface' clock is removed from the list of clocks. Update the clock-names list accordingly. Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- v5: Use ipq4019-dwc3 clock details for ipq5332 instead of new one --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index efde47a5b145..aef42dacc202 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -164,6 +164,7 @@ allOf: contains: enum: - qcom,ipq4019-dwc3 + - qcom,ipq5332-dwc3 then: properties: clocks: @@ -267,7 +268,6 @@ allOf: contains: enum: - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 then: From patchwork Thu Jul 25 10:45:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13741790 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EC7A1991AB; Thu, 25 Jul 2024 10:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904369; cv=none; b=Pef96kSWWdzOWHgDMLHrkDyZIVHElCWIEPwsrBHpAWM5GKtZEtYtcjSGbaHrak46RMo+blIUk40USaFmyY4n4dIg7q+Jbpcjvl7uqvYZYAyBP6RdPLA1pwQHCjpZEFGUt8NXsx8YBQ1rwSFQRhcSR+3/9nXFHUlxaxFAD2UieHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904369; c=relaxed/simple; bh=p8Sk4FKBBnyJmxr1GaMxe/l0Q+UdaX8rXld+1o6On0Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MDAgb2zzwFlrGLxTJ4RfZZygcysld9HOGt9LgMrKU1oiU0/2AOkgUcifsSA8Xvm9srE6C96mO7Gq/twQHdJhCyw2AJIPrmS9cY3MGNYvrfYsAY1MHksfrX+p2w8gVTOcgusBjzDKZlZbZJmmLlw0sBopxFVF0vmFk+pz2c/MwXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ANYdnqpp; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ANYdnqpp" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46P48PfS022278; Thu, 25 Jul 2024 10:46:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= T/AlIFpe7hmeVTaurYUXsanjT0Y59TPOb/2pqC05RTI=; b=ANYdnqppZbcdOMgf vD51nF52fnwaekIrVDosZeku8gJ/EAPVZGhwkPYCHoq2miBJ7/vaYF95L3IeQDX3 9pqhnf4SHiNBP+ftEaGeIr0CLnw2ctsGUaCTYgDdQvJ7PYEVkAY4rQzPaZKpZJJB 3n4C+FX5owALUpTgqybjkz1l1X+/2GQDTXXY5ART5g7SeOkQgVb77F1cWVHMn/Wq HRGv5qsj0RTDKKHQyL1QUr4U0eLJo7uC4Hiv/3yIa1jQd5wpxctUGd3RJPEQcKRe vzVefMkhVLNDz9jsO6c3+cjfq/8oe0MxvJpyILH7Ja0pAjYoQ1Roxp7hf9F/mjng V6hNQQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40k3g22k9x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:46:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46PAk2oI019286 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:46:02 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 25 Jul 2024 03:45:57 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan , Dmitry Baryshkov Subject: [PATCH v5 3/5] clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src Date: Thu, 25 Jul 2024 16:15:26 +0530 Message-ID: <20240725104528.3504967-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725104528.3504967-1-quic_varada@quicinc.com> References: <20240725104528.3504967-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SPNCjSdP0x_QMD4uLmJBsZqX2sjh0VQs X-Proofpoint-ORIG-GUID: SPNCjSdP0x_QMD4uLmJBsZqX2sjh0VQs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_11,2024-07-25_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250073 gcc_qdss_tsctr_clk_src (enabled in the boot loaders and dependent on gpll4_main) was not registered as one of the ipq5332 clocks. Hence clk_disable_unused() disabled 'gpll4_main' assuming there were no consumers for 'gpll4_main' resulting in system freeze or reboots. Reviewed-by: Dmitry Baryshkov Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan --- v5: Add 'Reviewed-by: Dmitry Baryshkov' v4: Move gpll4_main change that removes CLK_IGNORE_UNUSED to next patch Add 'Fixes' tag to commit message --- drivers/clk/qcom/gcc-ipq5332.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index f98591148a97..6a4877d88829 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -3388,6 +3388,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr, [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, + [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr, [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, From patchwork Thu Jul 25 10:45:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13741791 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E83401991AB; Thu, 25 Jul 2024 10:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904375; cv=none; b=Y80TqXiJQMx8ztAQew4d43sLC1y1ib66S5y+tOJz1Xiy8/8z18wdEUg8WD45sfEzbs41i2vgL6ePNRhL/lt7zTAr2pen/Rt2dSo//7nn52X3woU8k+0jwwrGfEHJhSkkG1TX0+ycrjCK6K/RUx7XlIDpYmgxIklOuENCia3RfBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904375; c=relaxed/simple; bh=kQuvP/hIIoHz2ZH+UtUdLvtsuRleCLhV5s38dwoPd/I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ee1n31nyGBWGZjiIJvy9eUwJWR/QnU3teturyCxlNpL+20fsIr/cElCYjRWwrMg2idfRpGhIiuqNoWHtV4h4MXjbwkvTHwIhohG0NhKHC0xLwEefXWb9OJSURMtnXPSFfWnVzRGtwDkVNhGCpI2gUj2ccV8xaFNuRPQH63nS8VI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=IQ3OvLyd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IQ3OvLyd" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46P8ovCp015382; Thu, 25 Jul 2024 10:46:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= b+4SOmcQ3t5clOw5uhJ7I63u0QWihO0nameHvI508Jk=; b=IQ3OvLydDwa8Z/9n 9Cb6h2EmZxVCCrSP1mXbq3bzUXdbQPTaZycSjirfrJogpsI1cH3YVRlCmV2hIyYz DMnG7vIw1jy1CJ8RwswItNCB22wK893vFgf/DTp8G7KyN/pjxsaUuzoMdTv5JLzZ Y/N5y2D1v7EmruTh+q8kCyylWHAmuhBsgpxBnIg+ETsZtqpPHNpE9+Ed3dbV5l/7 WXx98nSk+kV/py7p/J35yNp8gDaT5fyo5KrNd5TneBGe142uzUtrVJ3NhTGpTIQ5 GViR94NTPYYvGHIEREyGSbiIMIzVqmE3Mre2JxG6nYuIDNZGLeZhBrTqe3wCP3oW tbSnIg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40jxxbk9yv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:46:09 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46PAk8it004407 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:46:08 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 25 Jul 2024 03:46:02 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan , Dmitry Baryshkov Subject: [PATCH v5 4/5] clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks Date: Thu, 25 Jul 2024 16:15:27 +0530 Message-ID: <20240725104528.3504967-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725104528.3504967-1-quic_varada@quicinc.com> References: <20240725104528.3504967-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: cMnsNUYWBPMuLii_H4R_P0xY60wflGLx X-Proofpoint-GUID: cMnsNUYWBPMuLii_H4R_P0xY60wflGLx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_11,2024-07-25_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250073 Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Remove CLK_IGNORE_UNUSED from gpll4_main as all consumers have been identified. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- v5: Add 'Reviewed-by: Dmitry Baryshkov' v4: Remove CLK_IGNORE_UNUSED from gpll4_main v3: Not taking Reviewed-by: Konrad as NAK-ed by Dmitry Remove CLK_IGNORE_UNUSED -> CLK_IS_CRITICAL change and fix that in a separate patch --- drivers/clk/qcom/gcc-ipq5332.c | 35 +++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index 6a4877d88829..9536b2b7d07c 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -4,12 +4,14 @@ */ #include +#include #include #include #include #include #include +#include #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -126,17 +128,6 @@ static struct clk_alpha_pll gpll4_main = { .parent_data = &gcc_parent_data_xo, .num_parents = 1, .ops = &clk_alpha_pll_stromer_ops, - /* - * There are no consumers for this GPLL in kernel yet, - * (will be added soon), so the clock framework - * disables this source. But some of the clocks - * initialized by boot loaders uses this source. So we - * need to keep this clock ON. Add the - * CLK_IGNORE_UNUSED flag so the clock will not be - * disabled. Once the consumer in kernel is added, we - * can get rid of this flag. - */ - .flags = CLK_IGNORE_UNUSED, }, }, }; @@ -3629,6 +3620,24 @@ static const struct qcom_reset_map gcc_ipq5332_resets[] = { [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 }, }; +#define IPQ_APPS_ID 5332 /* some unique value */ + +static struct qcom_icc_hws_data icc_ipq5332_hws[] = { + { MASTER_SNOC_PCIE3_1_M, SLAVE_SNOC_PCIE3_1_M, GCC_SNOC_PCIE3_1LANE_M_CLK }, + { MASTER_ANOC_PCIE3_1_S, SLAVE_ANOC_PCIE3_1_S, GCC_SNOC_PCIE3_1LANE_S_CLK }, + { MASTER_SNOC_PCIE3_2_M, SLAVE_SNOC_PCIE3_2_M, GCC_SNOC_PCIE3_2LANE_M_CLK }, + { MASTER_ANOC_PCIE3_2_S, SLAVE_ANOC_PCIE3_2_S, GCC_SNOC_PCIE3_2LANE_S_CLK }, + { MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK }, + { MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK }, + { MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK }, + { MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK }, + { MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK }, + { MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK }, + { MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK }, + { MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK }, + { MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK }, +}; + static const struct regmap_config gcc_ipq5332_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -3657,6 +3666,9 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = { .num_resets = ARRAY_SIZE(gcc_ipq5332_resets), .clk_hws = gcc_ipq5332_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws), + .icc_hws = icc_ipq5332_hws, + .num_icc_hws = ARRAY_SIZE(icc_ipq5332_hws), + .icc_first_node_id = IPQ_APPS_ID, }; static int gcc_ipq5332_probe(struct platform_device *pdev) @@ -3675,6 +3687,7 @@ static struct platform_driver gcc_ipq5332_driver = { .driver = { .name = "gcc-ipq5332", .of_match_table = gcc_ipq5332_match_table, + .sync_state = icc_sync_state, }, }; From patchwork Thu Jul 25 10:45:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13741792 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D07551991AB; Thu, 25 Jul 2024 10:46:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904381; cv=none; b=CM6zh9/wjiIOCuKzb6QJDHsJ3MTu1e2SAzuMRAAS1FwXgwpAoLMHxwVzvfQV2kgKEN94eI25evMgRw5v7ZOohFdADNVSBReNvjpdFNpSDou9EbxN4lWnk+dJI+Ov57NnJWYVh8/4XDsEmLjbs4/L6FyK/uZ1Ito2Ei86AFiWJBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721904381; c=relaxed/simple; bh=VgiJR7kEM+cnGMiBj+lSW8qPAhtGTOoj5UWbY5zfUyI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HU2v+NXF2wS+VjXNG4CbsdeBEYXvwik08H4WMsTLXh/FQN9dqwnWb+Q/yRWl6Z43h4j/S1r8nnXZxn5nn1CNFxwf11TGUKkTe1PQnhYowNdmYhZyCSlR2IeexrjXqoOvOECamhFbTTlkm+mhjOxQlWMwfconCcQ7R/yz34E38/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=M3fU1iAR; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="M3fU1iAR" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46P8KcL5012610; Thu, 25 Jul 2024 10:46:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9ifLbZTRgpqGEv2r30ppykhhVp36eH3TXwx0BaaMj7o=; b=M3fU1iARWTrBtbzj 4MsLWwPM3YQR3wS3nLEQ8j/F3n9gBBFbZmucsiNiaz4H3fis96sFpOv1RKsWhZvw MyAsbZeXZ5IRNpUc+MclGWwE38cPgN1AK1CjTnWaAkFUavMK6CA5e5a55pk3vR+Z 6zPXK7m/jp7hwg+cLfvuWhPXnZEf8FrhUuxPtV5DLer6RMogakoNJ+WmsGis+pKU 1zYJQhSzvtmcQT4Go9iErla96fKiaYwIu481XdusOKEdGLkZ5Sfj7SvUAJH8c1eS ahqe3Sa1cVzvsX8K8n/G0BGM4FRCrFzFzJkSs+sFTGR4rrAwvEUbNWmPNeZFl0iQ FhoOVg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40g5auvx2d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:46:14 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46PAkDWx008091 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2024 10:46:13 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 25 Jul 2024 03:46:08 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v5 5/5] arm64: dts: qcom: ipq5332: Add icc provider ability to gcc Date: Thu, 25 Jul 2024 16:15:28 +0530 Message-ID: <20240725104528.3504967-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725104528.3504967-1-quic_varada@quicinc.com> References: <20240725104528.3504967-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: U94Pio0_6tflttZhT4Ovh-kIndw6FAEY X-Proofpoint-GUID: U94Pio0_6tflttZhT4Ovh-kIndw6FAEY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_11,2024-07-25_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 mlxscore=0 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250073 IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. Linux itself handles these clocks. However, these should not be exposed as just clocks and align with other Qualcomm SoCs that handle these clocks from a interconnect provider. Hence include icc provider capability to the gcc node so that peripherals can use the interconnect facility to enable these clocks. Change USB to use the icc-clk framework for the iface clock. Reviewed-by: Konrad Dybcio Signed-off-by: Varadarajan Narayanan --- v3: Fix #include file order --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 573656587c0d..7e8f9d578382 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include / { @@ -208,6 +209,7 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, <0>, @@ -327,11 +329,9 @@ usb: usb@8af8800 { "dm_hs_phy_irq"; clocks = <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_SNOC_USB_CLK>, <&gcc GCC_USB0_SLEEP_CLK>, <&gcc GCC_USB0_MOCK_UTMI_CLK>; clock-names = "core", - "iface", "sleep", "mock_utmi"; @@ -342,6 +342,9 @@ usb: usb@8af8800 { #address-cells = <1>; #size-cells = <1>; ranges; + interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>, + <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>; + interconnect-names = "usb-ddr", "apps-usb"; status = "disabled";